root / hw / mips_mipssim.c @ 795928f6
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/*
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* QEMU/mipssim emulation
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*
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* Emulates a very simple machine model similar to the one used by the
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* proprietary MIPS emulator.
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*
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* Copyright (c) 2007 Thiemo Seufer
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h" |
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#include "mips.h" |
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#include "mips_cpudevs.h" |
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#include "pc.h" |
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#include "isa.h" |
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#include "net.h" |
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#include "sysemu.h" |
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#include "boards.h" |
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#include "mips-bios.h" |
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#include "loader.h" |
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#include "elf.h" |
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#include "sysbus.h" |
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#include "exec-memory.h" |
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static struct _loaderparams { |
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int ram_size;
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const char *kernel_filename; |
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const char *kernel_cmdline; |
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const char *initrd_filename; |
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} loaderparams; |
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typedef struct ResetData { |
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CPUState *env; |
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uint64_t vector; |
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} ResetData; |
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static int64_t load_kernel(void) |
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{ |
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int64_t entry, kernel_high; |
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long kernel_size;
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long initrd_size;
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ram_addr_t initrd_offset; |
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int big_endian;
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#ifdef TARGET_WORDS_BIGENDIAN
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big_endian = 1;
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#else
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big_endian = 0;
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#endif
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kernel_size = load_elf(loaderparams.kernel_filename, cpu_mips_kseg0_to_phys, |
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NULL, (uint64_t *)&entry, NULL, |
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(uint64_t *)&kernel_high, big_endian, |
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ELF_MACHINE, 1);
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if (kernel_size >= 0) { |
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if ((entry & ~0x7fffffffULL) == 0x80000000) |
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entry = (int32_t)entry; |
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} else {
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fprintf(stderr, "qemu: could not load kernel '%s'\n",
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loaderparams.kernel_filename); |
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exit(1);
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} |
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/* load initrd */
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initrd_size = 0;
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initrd_offset = 0;
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if (loaderparams.initrd_filename) {
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initrd_size = get_image_size (loaderparams.initrd_filename); |
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if (initrd_size > 0) { |
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initrd_offset = (kernel_high + ~TARGET_PAGE_MASK) & TARGET_PAGE_MASK; |
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if (initrd_offset + initrd_size > loaderparams.ram_size) {
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fprintf(stderr, |
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"qemu: memory too small for initial ram disk '%s'\n",
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loaderparams.initrd_filename); |
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exit(1);
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} |
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initrd_size = load_image_targphys(loaderparams.initrd_filename, |
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initrd_offset, loaderparams.ram_size - initrd_offset); |
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} |
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if (initrd_size == (target_ulong) -1) { |
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fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
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loaderparams.initrd_filename); |
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exit(1);
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} |
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} |
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return entry;
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} |
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static void main_cpu_reset(void *opaque) |
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{ |
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ResetData *s = (ResetData *)opaque; |
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CPUState *env = s->env; |
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cpu_reset(env); |
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env->active_tc.PC = s->vector & ~(target_ulong)1;
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if (s->vector & 1) { |
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env->hflags |= MIPS_HFLAG_M16; |
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} |
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} |
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static void mipsnet_init(int base, qemu_irq irq, NICInfo *nd) |
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{ |
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DeviceState *dev; |
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SysBusDevice *s; |
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dev = qdev_create(NULL, "mipsnet"); |
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qdev_set_nic_properties(dev, nd); |
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qdev_init_nofail(dev); |
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s = sysbus_from_qdev(dev); |
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sysbus_connect_irq(s, 0, irq);
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memory_region_add_subregion(get_system_io(), |
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base, |
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sysbus_mmio_get_region(s, 0));
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} |
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static void |
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mips_mipssim_init (ram_addr_t ram_size, |
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const char *boot_device, |
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const char *kernel_filename, const char *kernel_cmdline, |
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const char *initrd_filename, const char *cpu_model) |
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{ |
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char *filename;
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MemoryRegion *address_space_mem = get_system_memory(); |
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MemoryRegion *ram = g_new(MemoryRegion, 1);
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MemoryRegion *bios = g_new(MemoryRegion, 1);
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CPUState *env; |
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ResetData *reset_info; |
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int bios_size;
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/* Init CPUs. */
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if (cpu_model == NULL) { |
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#ifdef TARGET_MIPS64
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cpu_model = "5Kf";
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#else
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cpu_model = "24Kf";
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#endif
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} |
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env = cpu_init(cpu_model); |
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if (!env) {
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fprintf(stderr, "Unable to find CPU definition\n");
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exit(1);
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} |
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reset_info = g_malloc0(sizeof(ResetData));
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reset_info->env = env; |
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reset_info->vector = env->active_tc.PC; |
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qemu_register_reset(main_cpu_reset, reset_info); |
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/* Allocate RAM. */
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memory_region_init_ram(ram, NULL, "mips_mipssim.ram", ram_size); |
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memory_region_init_ram(bios, NULL, "mips_mipssim.bios", BIOS_SIZE); |
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memory_region_set_readonly(bios, true);
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memory_region_add_subregion(address_space_mem, 0, ram);
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/* Map the BIOS / boot exception handler. */
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memory_region_add_subregion(address_space_mem, 0x1fc00000LL, bios);
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/* Load a BIOS / boot exception handler image. */
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if (bios_name == NULL) |
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bios_name = BIOS_FILENAME; |
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filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
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if (filename) {
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bios_size = load_image_targphys(filename, 0x1fc00000LL, BIOS_SIZE);
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g_free(filename); |
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} else {
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bios_size = -1;
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} |
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if ((bios_size < 0 || bios_size > BIOS_SIZE) && !kernel_filename) { |
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/* Bail out if we have neither a kernel image nor boot vector code. */
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fprintf(stderr, |
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"qemu: Could not load MIPS bios '%s', and no -kernel argument was specified\n",
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filename); |
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exit(1);
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} else {
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/* We have a boot vector start address. */
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env->active_tc.PC = (target_long)(int32_t)0xbfc00000;
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} |
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if (kernel_filename) {
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loaderparams.ram_size = ram_size; |
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loaderparams.kernel_filename = kernel_filename; |
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loaderparams.kernel_cmdline = kernel_cmdline; |
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loaderparams.initrd_filename = initrd_filename; |
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reset_info->vector = load_kernel(); |
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} |
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/* Init CPU internal devices. */
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cpu_mips_irq_init_cpu(env); |
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cpu_mips_clock_init(env); |
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/* Register 64 KB of ISA IO space at 0x1fd00000. */
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isa_mmio_init(0x1fd00000, 0x00010000); |
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/* A single 16450 sits at offset 0x3f8. It is attached to
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MIPS CPU INT2, which is interrupt 4. */
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if (serial_hds[0]) |
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serial_init(0x3f8, env->irq[4], 115200, serial_hds[0]); |
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if (nd_table[0].vlan) |
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/* MIPSnet uses the MIPS CPU INT0, which is interrupt 2. */
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mipsnet_init(0x4200, env->irq[2], &nd_table[0]); |
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} |
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static QEMUMachine mips_mipssim_machine = {
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.name = "mipssim",
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.desc = "MIPS MIPSsim platform",
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.init = mips_mipssim_init, |
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}; |
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static void mips_mipssim_machine_init(void) |
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{ |
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qemu_register_machine(&mips_mipssim_machine); |
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} |
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machine_init(mips_mipssim_machine_init); |