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/*
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* QEMU TCX Frame buffer
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "console.h" |
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#include "pixel_ops.h" |
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#include "sysbus.h" |
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#include "qdev-addr.h" |
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|
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#define MAXX 1024 |
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#define MAXY 768 |
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#define TCX_DAC_NREGS 16 |
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#define TCX_THC_NREGS_8 0x081c |
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#define TCX_THC_NREGS_24 0x1000 |
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#define TCX_TEC_NREGS 0x1000 |
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typedef struct TCXState { |
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SysBusDevice busdev; |
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target_phys_addr_t addr; |
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DisplayState *ds; |
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uint8_t *vram; |
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uint32_t *vram24, *cplane; |
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MemoryRegion vram_mem; |
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MemoryRegion vram_8bit; |
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MemoryRegion vram_24bit; |
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MemoryRegion vram_cplane; |
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MemoryRegion dac; |
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MemoryRegion tec; |
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MemoryRegion thc24; |
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MemoryRegion thc8; |
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ram_addr_t vram24_offset, cplane_offset; |
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uint32_t vram_size; |
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uint32_t palette[256];
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uint8_t r[256], g[256], b[256]; |
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uint16_t width, height, depth; |
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uint8_t dac_index, dac_state; |
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} TCXState; |
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static void tcx_screen_dump(void *opaque, const char *filename); |
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static void tcx24_screen_dump(void *opaque, const char *filename); |
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static void tcx_set_dirty(TCXState *s) |
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{ |
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unsigned int i; |
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for (i = 0; i < MAXX * MAXY; i += TARGET_PAGE_SIZE) { |
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memory_region_set_dirty(&s->vram_mem, i); |
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} |
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} |
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static void tcx24_set_dirty(TCXState *s) |
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{ |
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unsigned int i; |
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for (i = 0; i < MAXX * MAXY * 4; i += TARGET_PAGE_SIZE) { |
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memory_region_set_dirty(&s->vram_mem, s->vram24_offset + i); |
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memory_region_set_dirty(&s->vram_mem, s->cplane_offset + i); |
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} |
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} |
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static void update_palette_entries(TCXState *s, int start, int end) |
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{ |
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int i;
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for(i = start; i < end; i++) {
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switch(ds_get_bits_per_pixel(s->ds)) {
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default:
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case 8: |
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s->palette[i] = rgb_to_pixel8(s->r[i], s->g[i], s->b[i]); |
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break;
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case 15: |
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s->palette[i] = rgb_to_pixel15(s->r[i], s->g[i], s->b[i]); |
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break;
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case 16: |
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s->palette[i] = rgb_to_pixel16(s->r[i], s->g[i], s->b[i]); |
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break;
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case 32: |
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if (is_surface_bgr(s->ds->surface))
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s->palette[i] = rgb_to_pixel32bgr(s->r[i], s->g[i], s->b[i]); |
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else
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s->palette[i] = rgb_to_pixel32(s->r[i], s->g[i], s->b[i]); |
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break;
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} |
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} |
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if (s->depth == 24) { |
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tcx24_set_dirty(s); |
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} else {
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tcx_set_dirty(s); |
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} |
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} |
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static void tcx_draw_line32(TCXState *s1, uint8_t *d, |
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const uint8_t *s, int width) |
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{ |
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int x;
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uint8_t val; |
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uint32_t *p = (uint32_t *)d; |
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for(x = 0; x < width; x++) { |
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val = *s++; |
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*p++ = s1->palette[val]; |
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} |
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} |
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static void tcx_draw_line16(TCXState *s1, uint8_t *d, |
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const uint8_t *s, int width) |
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{ |
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int x;
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uint8_t val; |
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uint16_t *p = (uint16_t *)d; |
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for(x = 0; x < width; x++) { |
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val = *s++; |
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*p++ = s1->palette[val]; |
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} |
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} |
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static void tcx_draw_line8(TCXState *s1, uint8_t *d, |
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const uint8_t *s, int width) |
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{ |
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int x;
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uint8_t val; |
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for(x = 0; x < width; x++) { |
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val = *s++; |
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*d++ = s1->palette[val]; |
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} |
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} |
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/*
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XXX Could be much more optimal:
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* detect if line/page/whole screen is in 24 bit mode
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* if destination is also BGR, use memcpy
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*/
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static inline void tcx24_draw_line32(TCXState *s1, uint8_t *d, |
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const uint8_t *s, int width, |
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const uint32_t *cplane,
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const uint32_t *s24)
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{ |
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int x, bgr, r, g, b;
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uint8_t val, *p8; |
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uint32_t *p = (uint32_t *)d; |
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uint32_t dval; |
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bgr = is_surface_bgr(s1->ds->surface); |
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for(x = 0; x < width; x++, s++, s24++) { |
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if ((be32_to_cpu(*cplane++) & 0xff000000) == 0x03000000) { |
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// 24-bit direct, BGR order
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p8 = (uint8_t *)s24; |
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p8++; |
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b = *p8++; |
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g = *p8++; |
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r = *p8; |
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if (bgr)
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dval = rgb_to_pixel32bgr(r, g, b); |
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else
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dval = rgb_to_pixel32(r, g, b); |
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} else {
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val = *s; |
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dval = s1->palette[val]; |
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} |
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*p++ = dval; |
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} |
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} |
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static inline int check_dirty(TCXState *s, ram_addr_t page, ram_addr_t page24, |
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ram_addr_t cpage) |
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{ |
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int ret;
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unsigned int off; |
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ret = memory_region_get_dirty(&s->vram_mem, page, DIRTY_MEMORY_VGA); |
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for (off = 0; off < TARGET_PAGE_SIZE * 4; off += TARGET_PAGE_SIZE) { |
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ret |= memory_region_get_dirty(&s->vram_mem, page24 + off, |
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DIRTY_MEMORY_VGA); |
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ret |= memory_region_get_dirty(&s->vram_mem, cpage + off, |
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DIRTY_MEMORY_VGA); |
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} |
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return ret;
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} |
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static inline void reset_dirty(TCXState *ts, ram_addr_t page_min, |
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ram_addr_t page_max, ram_addr_t page24, |
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ram_addr_t cpage) |
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{ |
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memory_region_reset_dirty(&ts->vram_mem, |
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page_min, page_max + TARGET_PAGE_SIZE, |
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DIRTY_MEMORY_VGA); |
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memory_region_reset_dirty(&ts->vram_mem, |
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page24 + page_min * 4,
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page24 + page_max * 4 + TARGET_PAGE_SIZE,
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DIRTY_MEMORY_VGA); |
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memory_region_reset_dirty(&ts->vram_mem, |
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cpage + page_min * 4,
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cpage + page_max * 4 + TARGET_PAGE_SIZE,
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DIRTY_MEMORY_VGA); |
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} |
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/* Fixed line length 1024 allows us to do nice tricks not possible on
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VGA... */
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static void tcx_update_display(void *opaque) |
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{ |
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TCXState *ts = opaque; |
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ram_addr_t page, page_min, page_max; |
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int y, y_start, dd, ds;
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uint8_t *d, *s; |
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void (*f)(TCXState *s1, uint8_t *dst, const uint8_t *src, int width); |
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if (ds_get_bits_per_pixel(ts->ds) == 0) |
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return;
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page = 0;
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y_start = -1;
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page_min = -1;
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page_max = 0;
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d = ds_get_data(ts->ds); |
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s = ts->vram; |
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dd = ds_get_linesize(ts->ds); |
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ds = 1024;
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switch (ds_get_bits_per_pixel(ts->ds)) {
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case 32: |
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f = tcx_draw_line32; |
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break;
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case 15: |
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case 16: |
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f = tcx_draw_line16; |
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break;
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default:
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case 8: |
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f = tcx_draw_line8; |
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break;
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case 0: |
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return;
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} |
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for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE) { |
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if (memory_region_get_dirty(&ts->vram_mem, page, DIRTY_MEMORY_VGA)) {
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if (y_start < 0) |
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y_start = y; |
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if (page < page_min)
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page_min = page; |
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if (page > page_max)
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page_max = page; |
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f(ts, d, s, ts->width); |
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d += dd; |
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s += ds; |
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f(ts, d, s, ts->width); |
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d += dd; |
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s += ds; |
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f(ts, d, s, ts->width); |
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d += dd; |
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s += ds; |
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f(ts, d, s, ts->width); |
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d += dd; |
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s += ds; |
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} else {
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if (y_start >= 0) { |
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/* flush to display */
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dpy_update(ts->ds, 0, y_start,
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ts->width, y - y_start); |
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y_start = -1;
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} |
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d += dd * 4;
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s += ds * 4;
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} |
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} |
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if (y_start >= 0) { |
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/* flush to display */
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dpy_update(ts->ds, 0, y_start,
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ts->width, y - y_start); |
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} |
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/* reset modified pages */
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if (page_max >= page_min) {
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memory_region_reset_dirty(&ts->vram_mem, |
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page_min, page_max + TARGET_PAGE_SIZE, |
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DIRTY_MEMORY_VGA); |
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} |
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} |
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static void tcx24_update_display(void *opaque) |
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{ |
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TCXState *ts = opaque; |
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ram_addr_t page, page_min, page_max, cpage, page24; |
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int y, y_start, dd, ds;
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uint8_t *d, *s; |
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uint32_t *cptr, *s24; |
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if (ds_get_bits_per_pixel(ts->ds) != 32) |
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return;
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page = 0;
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page24 = ts->vram24_offset; |
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cpage = ts->cplane_offset; |
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y_start = -1;
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page_min = -1;
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page_max = 0;
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d = ds_get_data(ts->ds); |
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s = ts->vram; |
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s24 = ts->vram24; |
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cptr = ts->cplane; |
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dd = ds_get_linesize(ts->ds); |
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ds = 1024;
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for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE, |
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page24 += TARGET_PAGE_SIZE, cpage += TARGET_PAGE_SIZE) { |
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if (check_dirty(ts, page, page24, cpage)) {
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if (y_start < 0) |
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y_start = y; |
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if (page < page_min)
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page_min = page; |
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if (page > page_max)
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page_max = page; |
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tcx24_draw_line32(ts, d, s, ts->width, cptr, s24); |
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d += dd; |
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s += ds; |
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cptr += ds; |
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s24 += ds; |
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tcx24_draw_line32(ts, d, s, ts->width, cptr, s24); |
337 |
d += dd; |
338 |
s += ds; |
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cptr += ds; |
340 |
s24 += ds; |
341 |
tcx24_draw_line32(ts, d, s, ts->width, cptr, s24); |
342 |
d += dd; |
343 |
s += ds; |
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cptr += ds; |
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s24 += ds; |
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tcx24_draw_line32(ts, d, s, ts->width, cptr, s24); |
347 |
d += dd; |
348 |
s += ds; |
349 |
cptr += ds; |
350 |
s24 += ds; |
351 |
} else {
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if (y_start >= 0) { |
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/* flush to display */
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dpy_update(ts->ds, 0, y_start,
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ts->width, y - y_start); |
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y_start = -1;
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} |
358 |
d += dd * 4;
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s += ds * 4;
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cptr += ds * 4;
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s24 += ds * 4;
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} |
363 |
} |
364 |
if (y_start >= 0) { |
365 |
/* flush to display */
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dpy_update(ts->ds, 0, y_start,
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ts->width, y - y_start); |
368 |
} |
369 |
/* reset modified pages */
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if (page_max >= page_min) {
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reset_dirty(ts, page_min, page_max, page24, cpage); |
372 |
} |
373 |
} |
374 |
|
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static void tcx_invalidate_display(void *opaque) |
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{ |
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TCXState *s = opaque; |
378 |
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tcx_set_dirty(s); |
380 |
qemu_console_resize(s->ds, s->width, s->height); |
381 |
} |
382 |
|
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static void tcx24_invalidate_display(void *opaque) |
384 |
{ |
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TCXState *s = opaque; |
386 |
|
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tcx_set_dirty(s); |
388 |
tcx24_set_dirty(s); |
389 |
qemu_console_resize(s->ds, s->width, s->height); |
390 |
} |
391 |
|
392 |
static int vmstate_tcx_post_load(void *opaque, int version_id) |
393 |
{ |
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TCXState *s = opaque; |
395 |
|
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update_palette_entries(s, 0, 256); |
397 |
if (s->depth == 24) { |
398 |
tcx24_set_dirty(s); |
399 |
} else {
|
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tcx_set_dirty(s); |
401 |
} |
402 |
|
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return 0; |
404 |
} |
405 |
|
406 |
static const VMStateDescription vmstate_tcx = { |
407 |
.name ="tcx",
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.version_id = 4,
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.minimum_version_id = 4,
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410 |
.minimum_version_id_old = 4,
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.post_load = vmstate_tcx_post_load, |
412 |
.fields = (VMStateField []) { |
413 |
VMSTATE_UINT16(height, TCXState), |
414 |
VMSTATE_UINT16(width, TCXState), |
415 |
VMSTATE_UINT16(depth, TCXState), |
416 |
VMSTATE_BUFFER(r, TCXState), |
417 |
VMSTATE_BUFFER(g, TCXState), |
418 |
VMSTATE_BUFFER(b, TCXState), |
419 |
VMSTATE_UINT8(dac_index, TCXState), |
420 |
VMSTATE_UINT8(dac_state, TCXState), |
421 |
VMSTATE_END_OF_LIST() |
422 |
} |
423 |
}; |
424 |
|
425 |
static void tcx_reset(DeviceState *d) |
426 |
{ |
427 |
TCXState *s = container_of(d, TCXState, busdev.qdev); |
428 |
|
429 |
/* Initialize palette */
|
430 |
memset(s->r, 0, 256); |
431 |
memset(s->g, 0, 256); |
432 |
memset(s->b, 0, 256); |
433 |
s->r[255] = s->g[255] = s->b[255] = 255; |
434 |
update_palette_entries(s, 0, 256); |
435 |
memset(s->vram, 0, MAXX*MAXY);
|
436 |
memory_region_reset_dirty(&s->vram_mem, 0, MAXX * MAXY * (1 + 4 + 4), |
437 |
DIRTY_MEMORY_VGA); |
438 |
s->dac_index = 0;
|
439 |
s->dac_state = 0;
|
440 |
} |
441 |
|
442 |
static uint64_t tcx_dac_readl(void *opaque, target_phys_addr_t addr, |
443 |
unsigned size)
|
444 |
{ |
445 |
return 0; |
446 |
} |
447 |
|
448 |
static void tcx_dac_writel(void *opaque, target_phys_addr_t addr, uint64_t val, |
449 |
unsigned size)
|
450 |
{ |
451 |
TCXState *s = opaque; |
452 |
|
453 |
switch (addr) {
|
454 |
case 0: |
455 |
s->dac_index = val >> 24;
|
456 |
s->dac_state = 0;
|
457 |
break;
|
458 |
case 4: |
459 |
switch (s->dac_state) {
|
460 |
case 0: |
461 |
s->r[s->dac_index] = val >> 24;
|
462 |
update_palette_entries(s, s->dac_index, s->dac_index + 1);
|
463 |
s->dac_state++; |
464 |
break;
|
465 |
case 1: |
466 |
s->g[s->dac_index] = val >> 24;
|
467 |
update_palette_entries(s, s->dac_index, s->dac_index + 1);
|
468 |
s->dac_state++; |
469 |
break;
|
470 |
case 2: |
471 |
s->b[s->dac_index] = val >> 24;
|
472 |
update_palette_entries(s, s->dac_index, s->dac_index + 1);
|
473 |
s->dac_index = (s->dac_index + 1) & 255; // Index autoincrement |
474 |
default:
|
475 |
s->dac_state = 0;
|
476 |
break;
|
477 |
} |
478 |
break;
|
479 |
default:
|
480 |
break;
|
481 |
} |
482 |
return;
|
483 |
} |
484 |
|
485 |
static const MemoryRegionOps tcx_dac_ops = { |
486 |
.read = tcx_dac_readl, |
487 |
.write = tcx_dac_writel, |
488 |
.endianness = DEVICE_NATIVE_ENDIAN, |
489 |
.valid = { |
490 |
.min_access_size = 4,
|
491 |
.max_access_size = 4,
|
492 |
}, |
493 |
}; |
494 |
|
495 |
static uint64_t dummy_readl(void *opaque, target_phys_addr_t addr, |
496 |
unsigned size)
|
497 |
{ |
498 |
return 0; |
499 |
} |
500 |
|
501 |
static void dummy_writel(void *opaque, target_phys_addr_t addr, |
502 |
uint64_t val, unsigned size)
|
503 |
{ |
504 |
} |
505 |
|
506 |
static const MemoryRegionOps dummy_ops = { |
507 |
.read = dummy_readl, |
508 |
.write = dummy_writel, |
509 |
.endianness = DEVICE_NATIVE_ENDIAN, |
510 |
.valid = { |
511 |
.min_access_size = 4,
|
512 |
.max_access_size = 4,
|
513 |
}, |
514 |
}; |
515 |
|
516 |
static int tcx_init1(SysBusDevice *dev) |
517 |
{ |
518 |
TCXState *s = FROM_SYSBUS(TCXState, dev); |
519 |
ram_addr_t vram_offset = 0;
|
520 |
int size;
|
521 |
uint8_t *vram_base; |
522 |
|
523 |
memory_region_init_ram(&s->vram_mem, NULL, "tcx.vram", |
524 |
s->vram_size * (1 + 4 + 4)); |
525 |
vram_base = memory_region_get_ram_ptr(&s->vram_mem); |
526 |
|
527 |
/* 8-bit plane */
|
528 |
s->vram = vram_base; |
529 |
size = s->vram_size; |
530 |
memory_region_init_alias(&s->vram_8bit, "tcx.vram.8bit",
|
531 |
&s->vram_mem, vram_offset, size); |
532 |
sysbus_init_mmio_region(dev, &s->vram_8bit); |
533 |
vram_offset += size; |
534 |
vram_base += size; |
535 |
|
536 |
/* DAC */
|
537 |
memory_region_init_io(&s->dac, &tcx_dac_ops, s, "tcx.dac", TCX_DAC_NREGS);
|
538 |
sysbus_init_mmio_region(dev, &s->dac); |
539 |
|
540 |
/* TEC (dummy) */
|
541 |
memory_region_init_io(&s->tec, &dummy_ops, s, "tcx.tec", TCX_TEC_NREGS);
|
542 |
sysbus_init_mmio_region(dev, &s->tec); |
543 |
/* THC: NetBSD writes here even with 8-bit display: dummy */
|
544 |
memory_region_init_io(&s->thc24, &dummy_ops, s, "tcx.thc24",
|
545 |
TCX_THC_NREGS_24); |
546 |
sysbus_init_mmio_region(dev, &s->thc24); |
547 |
|
548 |
if (s->depth == 24) { |
549 |
/* 24-bit plane */
|
550 |
size = s->vram_size * 4;
|
551 |
s->vram24 = (uint32_t *)vram_base; |
552 |
s->vram24_offset = vram_offset; |
553 |
memory_region_init_alias(&s->vram_24bit, "tcx.vram.24bit",
|
554 |
&s->vram_mem, vram_offset, size); |
555 |
sysbus_init_mmio_region(dev, &s->vram_24bit); |
556 |
vram_offset += size; |
557 |
vram_base += size; |
558 |
|
559 |
/* Control plane */
|
560 |
size = s->vram_size * 4;
|
561 |
s->cplane = (uint32_t *)vram_base; |
562 |
s->cplane_offset = vram_offset; |
563 |
memory_region_init_alias(&s->vram_cplane, "tcx.vram.cplane",
|
564 |
&s->vram_mem, vram_offset, size); |
565 |
sysbus_init_mmio_region(dev, &s->vram_cplane); |
566 |
|
567 |
s->ds = graphic_console_init(tcx24_update_display, |
568 |
tcx24_invalidate_display, |
569 |
tcx24_screen_dump, NULL, s);
|
570 |
} else {
|
571 |
/* THC 8 bit (dummy) */
|
572 |
memory_region_init_io(&s->thc8, &dummy_ops, s, "tcx.thc8",
|
573 |
TCX_THC_NREGS_8); |
574 |
sysbus_init_mmio_region(dev, &s->thc8); |
575 |
|
576 |
s->ds = graphic_console_init(tcx_update_display, |
577 |
tcx_invalidate_display, |
578 |
tcx_screen_dump, NULL, s);
|
579 |
} |
580 |
|
581 |
qemu_console_resize(s->ds, s->width, s->height); |
582 |
return 0; |
583 |
} |
584 |
|
585 |
static void tcx_screen_dump(void *opaque, const char *filename) |
586 |
{ |
587 |
TCXState *s = opaque; |
588 |
FILE *f; |
589 |
uint8_t *d, *d1, v; |
590 |
int y, x;
|
591 |
|
592 |
f = fopen(filename, "wb");
|
593 |
if (!f)
|
594 |
return;
|
595 |
fprintf(f, "P6\n%d %d\n%d\n", s->width, s->height, 255); |
596 |
d1 = s->vram; |
597 |
for(y = 0; y < s->height; y++) { |
598 |
d = d1; |
599 |
for(x = 0; x < s->width; x++) { |
600 |
v = *d; |
601 |
fputc(s->r[v], f); |
602 |
fputc(s->g[v], f); |
603 |
fputc(s->b[v], f); |
604 |
d++; |
605 |
} |
606 |
d1 += MAXX; |
607 |
} |
608 |
fclose(f); |
609 |
return;
|
610 |
} |
611 |
|
612 |
static void tcx24_screen_dump(void *opaque, const char *filename) |
613 |
{ |
614 |
TCXState *s = opaque; |
615 |
FILE *f; |
616 |
uint8_t *d, *d1, v; |
617 |
uint32_t *s24, *cptr, dval; |
618 |
int y, x;
|
619 |
|
620 |
f = fopen(filename, "wb");
|
621 |
if (!f)
|
622 |
return;
|
623 |
fprintf(f, "P6\n%d %d\n%d\n", s->width, s->height, 255); |
624 |
d1 = s->vram; |
625 |
s24 = s->vram24; |
626 |
cptr = s->cplane; |
627 |
for(y = 0; y < s->height; y++) { |
628 |
d = d1; |
629 |
for(x = 0; x < s->width; x++, d++, s24++) { |
630 |
if ((*cptr++ & 0xff000000) == 0x03000000) { // 24-bit direct |
631 |
dval = *s24 & 0x00ffffff;
|
632 |
fputc((dval >> 16) & 0xff, f); |
633 |
fputc((dval >> 8) & 0xff, f); |
634 |
fputc(dval & 0xff, f);
|
635 |
} else {
|
636 |
v = *d; |
637 |
fputc(s->r[v], f); |
638 |
fputc(s->g[v], f); |
639 |
fputc(s->b[v], f); |
640 |
} |
641 |
} |
642 |
d1 += MAXX; |
643 |
} |
644 |
fclose(f); |
645 |
return;
|
646 |
} |
647 |
|
648 |
static SysBusDeviceInfo tcx_info = {
|
649 |
.init = tcx_init1, |
650 |
.qdev.name = "SUNW,tcx",
|
651 |
.qdev.size = sizeof(TCXState),
|
652 |
.qdev.reset = tcx_reset, |
653 |
.qdev.vmsd = &vmstate_tcx, |
654 |
.qdev.props = (Property[]) { |
655 |
DEFINE_PROP_TADDR("addr", TCXState, addr, -1), |
656 |
DEFINE_PROP_HEX32("vram_size", TCXState, vram_size, -1), |
657 |
DEFINE_PROP_UINT16("width", TCXState, width, -1), |
658 |
DEFINE_PROP_UINT16("height", TCXState, height, -1), |
659 |
DEFINE_PROP_UINT16("depth", TCXState, depth, -1), |
660 |
DEFINE_PROP_END_OF_LIST(), |
661 |
} |
662 |
}; |
663 |
|
664 |
static void tcx_register_devices(void) |
665 |
{ |
666 |
sysbus_register_withprop(&tcx_info); |
667 |
} |
668 |
|
669 |
device_init(tcx_register_devices) |