Archipelago » qemu

/*

 * Xtensa ISA:

 * http://www.tensilica.com/products/literature-docs/documentation/xtensa-isa-databook.htm

 *

 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.

 * All rights reserved.

 *

 * Redistribution and use in source and binary forms, with or without

 * modification, are permitted provided that the following conditions are met:

 *     * Redistributions of source code must retain the above copyright

 *       notice, this list of conditions and the following disclaimer.

 *     * Redistributions in binary form must reproduce the above copyright

 *       notice, this list of conditions and the following disclaimer in the

 *       documentation and/or other materials provided with the distribution.

 *     * Neither the name of the Open Source and Linux Lab nor the

 *       names of its contributors may be used to endorse or promote products

 *       derived from this software without specific prior written permission.

 *

 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY

 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES

 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;

 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND

 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT

 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS

 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 */

#include <stdio.h>

#include "cpu.h"

#include "exec-all.h"

#include "disas.h"

#include "tcg-op.h"

#include "qemu-log.h"

#include "helpers.h"

#define GEN_HELPER 1

#include "helpers.h"

typedef struct DisasContext {

    const XtensaConfig *config;

    TranslationBlock *tb;

    uint32_t pc;

    uint32_t next_pc;

    int cring;

    int ring;

    uint32_t lbeg;

    uint32_t lend;

    int is_jmp;

    int singlestep_enabled;

    bool sar_5bit;

    bool sar_m32_5bit;

    bool sar_m32_allocated;

    TCGv_i32 sar_m32;

} DisasContext;

static TCGv_ptr cpu_env;

static TCGv_i32 cpu_pc;

static TCGv_i32 cpu_R[16];

static TCGv_i32 cpu_SR[256];

static TCGv_i32 cpu_UR[256];

#include "gen-icount.h"

static const char * const sregnames[256] = {

    [LBEG] = "LBEG",

    [LEND] = "LEND",

    [LCOUNT] = "LCOUNT",

    [SAR] = "SAR",

    [SCOMPARE1] = "SCOMPARE1",

    [WINDOW_BASE] = "WINDOW_BASE",

    [WINDOW_START] = "WINDOW_START",

    [EPC1] = "EPC1",

    [DEPC] = "DEPC",

    [EXCSAVE1] = "EXCSAVE1",

    [PS] = "PS",

    [EXCCAUSE] = "EXCCAUSE",

    [EXCVADDR] = "EXCVADDR",

};

static const char * const uregnames[256] = {

    [THREADPTR] = "THREADPTR",

    [FCR] = "FCR",

    [FSR] = "FSR",

};

void xtensa_translate_init(void)

{

    static const char * const regnames[] = {

        "ar0", "ar1", "ar2", "ar3",

        "ar4", "ar5", "ar6", "ar7",

        "ar8", "ar9", "ar10", "ar11",

        "ar12", "ar13", "ar14", "ar15",

    };

    int i;

    cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");

    cpu_pc = tcg_global_mem_new_i32(TCG_AREG0,

            offsetof(CPUState, pc), "pc");

    for (i = 0; i < 16; i++) {

        cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0,

                offsetof(CPUState, regs[i]),

                regnames[i]);

    }

    for (i = 0; i < 256; ++i) {

        if (sregnames[i]) {

            cpu_SR[i] = tcg_global_mem_new_i32(TCG_AREG0,

                    offsetof(CPUState, sregs[i]),

                    sregnames[i]);

        }

    }

    for (i = 0; i < 256; ++i) {

        if (uregnames[i]) {

            cpu_UR[i] = tcg_global_mem_new_i32(TCG_AREG0,

                    offsetof(CPUState, uregs[i]),

                    uregnames[i]);

        }

    }

#define GEN_HELPER 2

#include "helpers.h"

}

static inline bool option_enabled(DisasContext *dc, int opt)

{

    return xtensa_option_enabled(dc->config, opt);

}

static void init_sar_tracker(DisasContext *dc)

{

    dc->sar_5bit = false;

    dc->sar_m32_5bit = false;

    dc->sar_m32_allocated = false;

}

static void reset_sar_tracker(DisasContext *dc)

{

    if (dc->sar_m32_allocated) {

        tcg_temp_free(dc->sar_m32);

    }

}

static void gen_right_shift_sar(DisasContext *dc, TCGv_i32 sa)

{

    tcg_gen_andi_i32(cpu_SR[SAR], sa, 0x1f);

    if (dc->sar_m32_5bit) {

        tcg_gen_discard_i32(dc->sar_m32);

    }

    dc->sar_5bit = true;

    dc->sar_m32_5bit = false;

}

static void gen_left_shift_sar(DisasContext *dc, TCGv_i32 sa)

{

    TCGv_i32 tmp = tcg_const_i32(32);

    if (!dc->sar_m32_allocated) {

        dc->sar_m32 = tcg_temp_local_new_i32();

        dc->sar_m32_allocated = true;

    }

    tcg_gen_andi_i32(dc->sar_m32, sa, 0x1f);

    tcg_gen_sub_i32(cpu_SR[SAR], tmp, dc->sar_m32);

    dc->sar_5bit = false;

    dc->sar_m32_5bit = true;

    tcg_temp_free(tmp);

}

static void gen_exception(int excp)

{

    TCGv_i32 tmp = tcg_const_i32(excp);

    gen_helper_exception(tmp);

    tcg_temp_free(tmp);

}

static void gen_exception_cause(DisasContext *dc, uint32_t cause)

{

    TCGv_i32 tpc = tcg_const_i32(dc->pc);

    TCGv_i32 tcause = tcg_const_i32(cause);

    gen_helper_exception_cause(tpc, tcause);

    tcg_temp_free(tpc);

    tcg_temp_free(tcause);

}

static void gen_check_privilege(DisasContext *dc)

{

    if (dc->cring) {

        gen_exception_cause(dc, PRIVILEGED_CAUSE);

    }

}

static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot)

{

    tcg_gen_mov_i32(cpu_pc, dest);

    if (dc->singlestep_enabled) {

        gen_exception(EXCP_DEBUG);

    } else {

        if (slot >= 0) {

            tcg_gen_goto_tb(slot);

            tcg_gen_exit_tb((tcg_target_long)dc->tb + slot);

        } else {

            tcg_gen_exit_tb(0);

        }

    }

    dc->is_jmp = DISAS_UPDATE;

}

static void gen_jump(DisasContext *dc, TCGv dest)

{

    gen_jump_slot(dc, dest, -1);

}

static void gen_jumpi(DisasContext *dc, uint32_t dest, int slot)

{

    TCGv_i32 tmp = tcg_const_i32(dest);

    if (((dc->pc ^ dest) & TARGET_PAGE_MASK) != 0) {

        slot = -1;

    }

    gen_jump_slot(dc, tmp, slot);

    tcg_temp_free(tmp);

}

static void gen_callw_slot(DisasContext *dc, int callinc, TCGv_i32 dest,

        int slot)

{

    TCGv_i32 tcallinc = tcg_const_i32(callinc);

    tcg_gen_deposit_i32(cpu_SR[PS], cpu_SR[PS],

            tcallinc, PS_CALLINC_SHIFT, PS_CALLINC_LEN);

    tcg_temp_free(tcallinc);

    tcg_gen_movi_i32(cpu_R[callinc << 2],

            (callinc << 30) | (dc->next_pc & 0x3fffffff));

    gen_jump_slot(dc, dest, slot);

}

static void gen_callw(DisasContext *dc, int callinc, TCGv_i32 dest)

{

    gen_callw_slot(dc, callinc, dest, -1);

}

static void gen_callwi(DisasContext *dc, int callinc, uint32_t dest, int slot)

{

    TCGv_i32 tmp = tcg_const_i32(dest);

    if (((dc->pc ^ dest) & TARGET_PAGE_MASK) != 0) {

        slot = -1;

    }

    gen_callw_slot(dc, callinc, tmp, slot);

    tcg_temp_free(tmp);

}

static bool gen_check_loop_end(DisasContext *dc, int slot)

{

    if (option_enabled(dc, XTENSA_OPTION_LOOP) &&

            !(dc->tb->flags & XTENSA_TBFLAG_EXCM) &&

            dc->next_pc == dc->lend) {

        int label = gen_new_label();

        tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_SR[LCOUNT], 0, label);

        tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_SR[LCOUNT], 1);

        gen_jumpi(dc, dc->lbeg, slot);

        gen_set_label(label);

        gen_jumpi(dc, dc->next_pc, -1);

        return true;

    }

    return false;

}

static void gen_jumpi_check_loop_end(DisasContext *dc, int slot)

{

    if (!gen_check_loop_end(dc, slot)) {

        gen_jumpi(dc, dc->next_pc, slot);

    }

}

static void gen_brcond(DisasContext *dc, TCGCond cond,

        TCGv_i32 t0, TCGv_i32 t1, uint32_t offset)

{

    int label = gen_new_label();

    tcg_gen_brcond_i32(cond, t0, t1, label);

    gen_jumpi_check_loop_end(dc, 0);

    gen_set_label(label);

    gen_jumpi(dc, dc->pc + offset, 1);

}

static void gen_brcondi(DisasContext *dc, TCGCond cond,

        TCGv_i32 t0, uint32_t t1, uint32_t offset)

{

    TCGv_i32 tmp = tcg_const_i32(t1);

    gen_brcond(dc, cond, t0, tmp, offset);

    tcg_temp_free(tmp);

}

static void gen_rsr(DisasContext *dc, TCGv_i32 d, uint32_t sr)

{

    static void (* const rsr_handler[256])(DisasContext *dc,

            TCGv_i32 d, uint32_t sr) = {

    };

    if (sregnames[sr]) {

        if (rsr_handler[sr]) {

            rsr_handler[sr](dc, d, sr);

        } else {

            tcg_gen_mov_i32(d, cpu_SR[sr]);

        }

    } else {

        qemu_log("RSR %d not implemented, ", sr);

    }

}

static void gen_wsr_lbeg(DisasContext *dc, uint32_t sr, TCGv_i32 s)

{

    gen_helper_wsr_lbeg(s);

}

static void gen_wsr_lend(DisasContext *dc, uint32_t sr, TCGv_i32 s)

{

    gen_helper_wsr_lend(s);

}

static void gen_wsr_sar(DisasContext *dc, uint32_t sr, TCGv_i32 s)

{

    tcg_gen_andi_i32(cpu_SR[sr], s, 0x3f);

    if (dc->sar_m32_5bit) {

        tcg_gen_discard_i32(dc->sar_m32);

    }

    dc->sar_5bit = false;

    dc->sar_m32_5bit = false;

}

static void gen_wsr_windowbase(DisasContext *dc, uint32_t sr, TCGv_i32 v)

{

    gen_helper_wsr_windowbase(v);

}

static void gen_wsr_ps(DisasContext *dc, uint32_t sr, TCGv_i32 v)

{

    uint32_t mask = PS_WOE | PS_CALLINC | PS_OWB |

        PS_UM | PS_EXCM | PS_INTLEVEL;

    if (option_enabled(dc, XTENSA_OPTION_MMU)) {

        mask |= PS_RING;

    }

    tcg_gen_andi_i32(cpu_SR[sr], v, mask);

    /* This can change mmu index, so exit tb */

    gen_jumpi_check_loop_end(dc, -1);

}

static void gen_wsr(DisasContext *dc, uint32_t sr, TCGv_i32 s)

{

    static void (* const wsr_handler[256])(DisasContext *dc,

            uint32_t sr, TCGv_i32 v) = {

        [LBEG] = gen_wsr_lbeg,

        [LEND] = gen_wsr_lend,

        [SAR] = gen_wsr_sar,

        [WINDOW_BASE] = gen_wsr_windowbase,

        [PS] = gen_wsr_ps,

    };

    if (sregnames[sr]) {

        if (wsr_handler[sr]) {

            wsr_handler[sr](dc, sr, s);

        } else {

            tcg_gen_mov_i32(cpu_SR[sr], s);

        }

    } else {

        qemu_log("WSR %d not implemented, ", sr);

    }

}

static void disas_xtensa_insn(DisasContext *dc)

{

#define HAS_OPTION(opt) do { \

        if (!option_enabled(dc, opt)) { \

            qemu_log("Option %d is not enabled %s:%d\n", \

                    (opt), __FILE__, __LINE__); \

            goto invalid_opcode; \

        } \

    } while (0)

#define TBD() qemu_log("TBD(pc = %08x): %s:%d\n", dc->pc, __FILE__, __LINE__)

#define RESERVED() do { \

        qemu_log("RESERVED(pc = %08x, %02x%02x%02x): %s:%d\n", \

                dc->pc, b0, b1, b2, __FILE__, __LINE__); \

        goto invalid_opcode; \

    } while (0)

#ifdef TARGET_WORDS_BIGENDIAN

#define OP0 (((b0) & 0xf0) >> 4)

#define OP1 (((b2) & 0xf0) >> 4)

#define OP2 ((b2) & 0xf)

#define RRR_R ((b1) & 0xf)

#define RRR_S (((b1) & 0xf0) >> 4)

#define RRR_T ((b0) & 0xf)

#else

#define OP0 (((b0) & 0xf))

#define OP1 (((b2) & 0xf))

#define OP2 (((b2) & 0xf0) >> 4)

#define RRR_R (((b1) & 0xf0) >> 4)

#define RRR_S (((b1) & 0xf))

#define RRR_T (((b0) & 0xf0) >> 4)

#endif

#define RRRN_R RRR_R

#define RRRN_S RRR_S

#define RRRN_T RRR_T

#define RRI8_R RRR_R

#define RRI8_S RRR_S

#define RRI8_T RRR_T

#define RRI8_IMM8 (b2)

#define RRI8_IMM8_SE ((((b2) & 0x80) ? 0xffffff00 : 0) | RRI8_IMM8)

#ifdef TARGET_WORDS_BIGENDIAN

#define RI16_IMM16 (((b1) << 8) | (b2))

#else

#define RI16_IMM16 (((b2) << 8) | (b1))

#endif

#ifdef TARGET_WORDS_BIGENDIAN

#define CALL_N (((b0) & 0xc) >> 2)

#define CALL_OFFSET ((((b0) & 0x3) << 16) | ((b1) << 8) | (b2))

#else

#define CALL_N (((b0) & 0x30) >> 4)

#define CALL_OFFSET ((((b0) & 0xc0) >> 6) | ((b1) << 2) | ((b2) << 10))

#endif

#define CALL_OFFSET_SE \

    (((CALL_OFFSET & 0x20000) ? 0xfffc0000 : 0) | CALL_OFFSET)

#define CALLX_N CALL_N

#ifdef TARGET_WORDS_BIGENDIAN

#define CALLX_M ((b0) & 0x3)

#else

#define CALLX_M (((b0) & 0xc0) >> 6)

#endif

#define CALLX_S RRR_S

#define BRI12_M CALLX_M

#define BRI12_S RRR_S

#ifdef TARGET_WORDS_BIGENDIAN

#define BRI12_IMM12 ((((b1) & 0xf) << 8) | (b2))

#else

#define BRI12_IMM12 ((((b1) & 0xf0) >> 4) | ((b2) << 4))

#endif

#define BRI12_IMM12_SE (((BRI12_IMM12 & 0x800) ? 0xfffff000 : 0) | BRI12_IMM12)

#define BRI8_M BRI12_M

#define BRI8_R RRI8_R

#define BRI8_S RRI8_S

#define BRI8_IMM8 RRI8_IMM8

#define BRI8_IMM8_SE RRI8_IMM8_SE

#define RSR_SR (b1)

    uint8_t b0 = ldub_code(dc->pc);

    uint8_t b1 = ldub_code(dc->pc + 1);

    uint8_t b2 = ldub_code(dc->pc + 2);

    static const uint32_t B4CONST[] = {

        0xffffffff, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256

    };

    static const uint32_t B4CONSTU[] = {

        32768, 65536, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256

    };

    if (OP0 >= 8) {

        dc->next_pc = dc->pc + 2;

        HAS_OPTION(XTENSA_OPTION_CODE_DENSITY);

    } else {

        dc->next_pc = dc->pc + 3;

    }

    switch (OP0) {

    case 0: /*QRST*/

        switch (OP1) {

        case 0: /*RST0*/

            switch (OP2) {

            case 0: /*ST0*/

                if ((RRR_R & 0xc) == 0x8) {

                    HAS_OPTION(XTENSA_OPTION_BOOLEAN);

                }

                switch (RRR_R) {

                case 0: /*SNM0*/

                    switch (CALLX_M) {

                    case 0: /*ILL*/

                        gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);

                        break;

                    case 1: /*reserved*/

                        RESERVED();

                        break;

                    case 2: /*JR*/

                        switch (CALLX_N) {

                        case 0: /*RET*/

                        case 2: /*JX*/

                            gen_jump(dc, cpu_R[CALLX_S]);

                            break;

                        case 1: /*RETWw*/

                            HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);

                            {

                                TCGv_i32 tmp = tcg_const_i32(dc->pc);

                                gen_helper_retw(tmp, tmp);

                                gen_jump(dc, tmp);

                                tcg_temp_free(tmp);

                            }

                            break;

                        case 3: /*reserved*/

                            RESERVED();

                            break;

                        }

                        break;

                    case 3: /*CALLX*/

                        switch (CALLX_N) {

                        case 0: /*CALLX0*/

                            {

                                TCGv_i32 tmp = tcg_temp_new_i32();

                                tcg_gen_mov_i32(tmp, cpu_R[CALLX_S]);

                                tcg_gen_movi_i32(cpu_R[0], dc->next_pc);

                                gen_jump(dc, tmp);

                                tcg_temp_free(tmp);

                            }

                            break;

                        case 1: /*CALLX4w*/

                        case 2: /*CALLX8w*/

                        case 3: /*CALLX12w*/

                            HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);

                            {

                                TCGv_i32 tmp = tcg_temp_new_i32();

                                tcg_gen_mov_i32(tmp, cpu_R[CALLX_S]);

                                gen_callw(dc, CALLX_N, tmp);

                                tcg_temp_free(tmp);

                            }

                            break;

                        }

                        break;

                    }

                    break;

                case 1: /*MOVSPw*/

                    HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);

                    {

                        TCGv_i32 pc = tcg_const_i32(dc->pc);

                        gen_helper_movsp(pc);

                        tcg_gen_mov_i32(cpu_R[RRR_T], cpu_R[RRR_S]);

                        tcg_temp_free(pc);

                    }

                    break;

                case 2: /*SYNC*/

                    switch (RRR_T) {

                    case 0: /*ISYNC*/

                        break;

                    case 1: /*RSYNC*/

                        break;

                    case 2: /*ESYNC*/

                        break;

                    case 3: /*DSYNC*/

                        break;

                    case 8: /*EXCW*/

                        HAS_OPTION(XTENSA_OPTION_EXCEPTION);

                        break;

                    case 12: /*MEMW*/

                        break;

                    case 13: /*EXTW*/

                        break;

                    case 15: /*NOP*/

                        break;

                    default: /*reserved*/

                        RESERVED();

                        break;

                    }

                    break;

                case 3: /*RFEIx*/

                    switch (RRR_T) {

                    case 0: /*RFETx*/

                        HAS_OPTION(XTENSA_OPTION_EXCEPTION);

                        switch (RRR_S) {

                        case 0: /*RFEx*/

                            gen_check_privilege(dc);

                            tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);

                            gen_jump(dc, cpu_SR[EPC1]);

                            break;

                        case 1: /*RFUEx*/

                            RESERVED();

                            break;

                        case 2: /*RFDEx*/

                            gen_check_privilege(dc);

                            gen_jump(dc, cpu_SR[

                                    dc->config->ndepc ? DEPC : EPC1]);

                            break;

                        case 4: /*RFWOw*/

                        case 5: /*RFWUw*/

                            HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);

                            gen_check_privilege(dc);

                            {

                                TCGv_i32 tmp = tcg_const_i32(1);

                                tcg_gen_andi_i32(

                                        cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);

                                tcg_gen_shl_i32(tmp, tmp, cpu_SR[WINDOW_BASE]);

                                if (RRR_S == 4) {

                                    tcg_gen_andc_i32(cpu_SR[WINDOW_START],

                                            cpu_SR[WINDOW_START], tmp);

                                } else {

                                    tcg_gen_or_i32(cpu_SR[WINDOW_START],

                                            cpu_SR[WINDOW_START], tmp);

                                }

                                gen_helper_restore_owb();

                                gen_jump(dc, cpu_SR[EPC1]);

                                tcg_temp_free(tmp);

                            }

                            break;

                        default: /*reserved*/

                            RESERVED();

                            break;

                        }

                        break;

                    case 1: /*RFIx*/

                        HAS_OPTION(XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT);

                        TBD();

                        break;

                    case 2: /*RFME*/

                        TBD();

                        break;

                    default: /*reserved*/

                        RESERVED();

                        break;

                    }

                    break;

                case 4: /*BREAKx*/

                    HAS_OPTION(XTENSA_OPTION_EXCEPTION);

                    TBD();

                    break;

                case 5: /*SYSCALLx*/

                    HAS_OPTION(XTENSA_OPTION_EXCEPTION);

                    switch (RRR_S) {

                    case 0: /*SYSCALLx*/

                        gen_exception_cause(dc, SYSCALL_CAUSE);

                        break;

                    case 1: /*SIMCALL*/

                        TBD();

                        break;

                    default:

                        RESERVED();

                        break;

                    }

                    break;

                case 6: /*RSILx*/

                    HAS_OPTION(XTENSA_OPTION_INTERRUPT);

                    gen_check_privilege(dc);

                    tcg_gen_mov_i32(cpu_R[RRR_T], cpu_SR[PS]);

                    tcg_gen_ori_i32(cpu_SR[PS], cpu_SR[PS], RRR_S);

                    tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS],

                            RRR_S | ~PS_INTLEVEL);

                    break;

                case 7: /*WAITIx*/

                    HAS_OPTION(XTENSA_OPTION_INTERRUPT);

                    TBD();

                    break;

                case 8: /*ANY4p*/

                    HAS_OPTION(XTENSA_OPTION_BOOLEAN);

                    TBD();

                    break;

                case 9: /*ALL4p*/

                    HAS_OPTION(XTENSA_OPTION_BOOLEAN);

                    TBD();

                    break;

                case 10: /*ANY8p*/

                    HAS_OPTION(XTENSA_OPTION_BOOLEAN);

                    TBD();

                    break;

                case 11: /*ALL8p*/

                    HAS_OPTION(XTENSA_OPTION_BOOLEAN);

                    TBD();

                    break;

                default: /*reserved*/

                    RESERVED();

                    break;

                }

                break;

            case 1: /*AND*/

                tcg_gen_and_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);

                break;

            case 2: /*OR*/

                tcg_gen_or_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);

                break;

            case 3: /*XOR*/

                tcg_gen_xor_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);

                break;

            case 4: /*ST1*/

                switch (RRR_R) {

                case 0: /*SSR*/

                    gen_right_shift_sar(dc, cpu_R[RRR_S]);

                    break;

                case 1: /*SSL*/

                    gen_left_shift_sar(dc, cpu_R[RRR_S]);

                    break;

                case 2: /*SSA8L*/

                    {

                        TCGv_i32 tmp = tcg_temp_new_i32();

                        tcg_gen_shli_i32(tmp, cpu_R[RRR_S], 3);

                        gen_right_shift_sar(dc, tmp);

                        tcg_temp_free(tmp);

                    }

                    break;

                case 3: /*SSA8B*/

                    {

                        TCGv_i32 tmp = tcg_temp_new_i32();

                        tcg_gen_shli_i32(tmp, cpu_R[RRR_S], 3);

                        gen_left_shift_sar(dc, tmp);

                        tcg_temp_free(tmp);

                    }

                    break;

                case 4: /*SSAI*/

                    {

                        TCGv_i32 tmp = tcg_const_i32(

                                RRR_S | ((RRR_T & 1) << 4));

                        gen_right_shift_sar(dc, tmp);

                        tcg_temp_free(tmp);

                    }

                    break;

                case 6: /*RER*/

                    TBD();

                    break;

                case 7: /*WER*/

                    TBD();

                    break;

                case 8: /*ROTWw*/

                    HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);

                    gen_check_privilege(dc);

                    {

                        TCGv_i32 tmp = tcg_const_i32(

                                RRR_T | ((RRR_T & 8) ? 0xfffffff0 : 0));

                        gen_helper_rotw(tmp);

                        tcg_temp_free(tmp);

                    }

                    break;

                case 14: /*NSAu*/

                    HAS_OPTION(XTENSA_OPTION_MISC_OP);

                    gen_helper_nsa(cpu_R[RRR_T], cpu_R[RRR_S]);

                    break;

                case 15: /*NSAUu*/

                    HAS_OPTION(XTENSA_OPTION_MISC_OP);

                    gen_helper_nsau(cpu_R[RRR_T], cpu_R[RRR_S]);

                    break;

                default: /*reserved*/

                    RESERVED();

                    break;

                }

                break;

            case 5: /*TLB*/

                TBD();

                break;

            case 6: /*RT0*/

                switch (RRR_S) {

                case 0: /*NEG*/

                    tcg_gen_neg_i32(cpu_R[RRR_R], cpu_R[RRR_T]);

                    break;

                case 1: /*ABS*/

                    {

                        int label = gen_new_label();

                        tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_T]);

                        tcg_gen_brcondi_i32(

                                TCG_COND_GE, cpu_R[RRR_R], 0, label);

                        tcg_gen_neg_i32(cpu_R[RRR_R], cpu_R[RRR_T]);

                        gen_set_label(label);

                    }

                    break;

                default: /*reserved*/

                    RESERVED();

                    break;

                }

                break;

            case 7: /*reserved*/

                RESERVED();

                break;

            case 8: /*ADD*/

                tcg_gen_add_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);

                break;

            case 9: /*ADD**/

            case 10:

            case 11:

                {

                    TCGv_i32 tmp = tcg_temp_new_i32();

                    tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 8);

                    tcg_gen_add_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]);

                    tcg_temp_free(tmp);

                }

                break;

            case 12: /*SUB*/

                tcg_gen_sub_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);

                break;

            case 13: /*SUB**/

            case 14:

            case 15:

                {

                    TCGv_i32 tmp = tcg_temp_new_i32();

                    tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 12);

                    tcg_gen_sub_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]);

                    tcg_temp_free(tmp);

                }

                break;

            }

            break;

        case 1: /*RST1*/

            switch (OP2) {

            case 0: /*SLLI*/

            case 1:

                tcg_gen_shli_i32(cpu_R[RRR_R], cpu_R[RRR_S],

                        32 - (RRR_T | ((OP2 & 1) << 4)));

                break;