root / target-i386 / machine.c @ 79e9ebeb
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#include "hw/hw.h" |
|---|---|
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#include "hw/boards.h" |
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#include "hw/i386/pc.h" |
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#include "hw/isa/isa.h" |
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|
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#include "cpu.h" |
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#include "sysemu/kvm.h" |
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|
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static const VMStateDescription vmstate_segment = { |
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.name = "segment",
|
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.version_id = 1,
|
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.minimum_version_id = 1,
|
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.minimum_version_id_old = 1,
|
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.fields = (VMStateField []) {
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VMSTATE_UINT32(selector, SegmentCache), |
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VMSTATE_UINTTL(base, SegmentCache), |
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VMSTATE_UINT32(limit, SegmentCache), |
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VMSTATE_UINT32(flags, SegmentCache), |
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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|
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#define VMSTATE_SEGMENT(_field, _state) { \
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.name = (stringify(_field)), \ |
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.size = sizeof(SegmentCache), \
|
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.vmsd = &vmstate_segment, \ |
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.flags = VMS_STRUCT, \ |
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.offset = offsetof(_state, _field) \ |
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+ type_check(SegmentCache,typeof_field(_state, _field)) \ |
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} |
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|
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#define VMSTATE_SEGMENT_ARRAY(_field, _state, _n) \
|
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VMSTATE_STRUCT_ARRAY(_field, _state, _n, 0, vmstate_segment, SegmentCache)
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|
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static const VMStateDescription vmstate_xmm_reg = { |
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.name = "xmm_reg",
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.version_id = 1,
|
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.minimum_version_id = 1,
|
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.minimum_version_id_old = 1,
|
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.fields = (VMStateField []) {
|
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VMSTATE_UINT64(XMM_Q(0), XMMReg),
|
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VMSTATE_UINT64(XMM_Q(1), XMMReg),
|
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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|
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#define VMSTATE_XMM_REGS(_field, _state, _n) \
|
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VMSTATE_STRUCT_ARRAY(_field, _state, _n, 0, vmstate_xmm_reg, XMMReg)
|
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|
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/* YMMH format is the same as XMM */
|
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static const VMStateDescription vmstate_ymmh_reg = { |
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.name = "ymmh_reg",
|
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.version_id = 1,
|
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.minimum_version_id = 1,
|
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.minimum_version_id_old = 1,
|
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.fields = (VMStateField []) {
|
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VMSTATE_UINT64(XMM_Q(0), XMMReg),
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VMSTATE_UINT64(XMM_Q(1), XMMReg),
|
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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|
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#define VMSTATE_YMMH_REGS_VARS(_field, _state, _n, _v) \
|
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VMSTATE_STRUCT_ARRAY(_field, _state, _n, _v, vmstate_ymmh_reg, XMMReg) |
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|
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static const VMStateDescription vmstate_bnd_regs = { |
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.name = "bnd_regs",
|
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.version_id = 1,
|
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.minimum_version_id = 1,
|
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.minimum_version_id_old = 1,
|
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.fields = (VMStateField[]) {
|
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VMSTATE_UINT64(lb, BNDReg), |
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VMSTATE_UINT64(ub, BNDReg), |
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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|
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#define VMSTATE_BND_REGS(_field, _state, _n) \
|
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VMSTATE_STRUCT_ARRAY(_field, _state, _n, 0, vmstate_bnd_regs, BNDReg)
|
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|
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static const VMStateDescription vmstate_mtrr_var = { |
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.name = "mtrr_var",
|
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.version_id = 1,
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.minimum_version_id = 1,
|
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.minimum_version_id_old = 1,
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.fields = (VMStateField []) {
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VMSTATE_UINT64(base, MTRRVar), |
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VMSTATE_UINT64(mask, MTRRVar), |
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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|
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#define VMSTATE_MTRR_VARS(_field, _state, _n, _v) \
|
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VMSTATE_STRUCT_ARRAY(_field, _state, _n, _v, vmstate_mtrr_var, MTRRVar) |
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|
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static void put_fpreg_error(QEMUFile *f, void *opaque, size_t size) |
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{
|
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fprintf(stderr, "call put_fpreg() with invalid arguments\n");
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exit(0);
|
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} |
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|
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/* XXX: add that in a FPU generic layer */
|
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union x86_longdouble {
|
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uint64_t mant; |
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uint16_t exp; |
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}; |
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|
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#define MANTD1(fp) (fp & ((1LL << 52) - 1)) |
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#define EXPBIAS1 1023 |
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#define EXPD1(fp) ((fp >> 52) & 0x7FF) |
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#define SIGND1(fp) ((fp >> 32) & 0x80000000) |
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|
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static void fp64_to_fp80(union x86_longdouble *p, uint64_t temp) |
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{
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int e;
|
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/* mantissa */
|
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p->mant = (MANTD1(temp) << 11) | (1LL << 63); |
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/* exponent + sign */
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e = EXPD1(temp) - EXPBIAS1 + 16383;
|
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e |= SIGND1(temp) >> 16;
|
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p->exp = e; |
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} |
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|
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static int get_fpreg(QEMUFile *f, void *opaque, size_t size) |
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{
|
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FPReg *fp_reg = opaque; |
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uint64_t mant; |
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uint16_t exp; |
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|
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qemu_get_be64s(f, &mant); |
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qemu_get_be16s(f, &exp); |
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fp_reg->d = cpu_set_fp80(mant, exp); |
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return 0; |
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} |
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|
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static void put_fpreg(QEMUFile *f, void *opaque, size_t size) |
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{
|
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FPReg *fp_reg = opaque; |
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uint64_t mant; |
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uint16_t exp; |
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/* we save the real CPU data (in case of MMX usage only 'mant'
|
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contains the MMX register */
|
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cpu_get_fp80(&mant, &exp, fp_reg->d); |
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qemu_put_be64s(f, &mant); |
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qemu_put_be16s(f, &exp); |
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} |
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|
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static const VMStateInfo vmstate_fpreg = { |
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.name = "fpreg",
|
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.get = get_fpreg, |
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.put = put_fpreg, |
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}; |
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|
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static int get_fpreg_1_mmx(QEMUFile *f, void *opaque, size_t size) |
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{
|
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union x86_longdouble *p = opaque;
|
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uint64_t mant; |
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|
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qemu_get_be64s(f, &mant); |
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p->mant = mant; |
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p->exp = 0xffff;
|
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return 0; |
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} |
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|
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static const VMStateInfo vmstate_fpreg_1_mmx = { |
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.name = "fpreg_1_mmx",
|
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.get = get_fpreg_1_mmx, |
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.put = put_fpreg_error, |
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}; |
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|
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static int get_fpreg_1_no_mmx(QEMUFile *f, void *opaque, size_t size) |
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{
|
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union x86_longdouble *p = opaque;
|
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uint64_t mant; |
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|
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qemu_get_be64s(f, &mant); |
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fp64_to_fp80(p, mant); |
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return 0; |
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} |
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|
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static const VMStateInfo vmstate_fpreg_1_no_mmx = { |
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.name = "fpreg_1_no_mmx",
|
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.get = get_fpreg_1_no_mmx, |
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.put = put_fpreg_error, |
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}; |
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|
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static bool fpregs_is_0(void *opaque, int version_id) |
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{
|
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X86CPU *cpu = opaque; |
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CPUX86State *env = &cpu->env; |
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|
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return (env->fpregs_format_vmstate == 0); |
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} |
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|
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static bool fpregs_is_1_mmx(void *opaque, int version_id) |
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{
|
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X86CPU *cpu = opaque; |
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CPUX86State *env = &cpu->env; |
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int guess_mmx;
|
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|
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guess_mmx = ((env->fptag_vmstate == 0xff) &&
|
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(env->fpus_vmstate & 0x3800) == 0); |
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return (guess_mmx && (env->fpregs_format_vmstate == 1)); |
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} |
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|
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static bool fpregs_is_1_no_mmx(void *opaque, int version_id) |
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{
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X86CPU *cpu = opaque; |
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CPUX86State *env = &cpu->env; |
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int guess_mmx;
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|
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guess_mmx = ((env->fptag_vmstate == 0xff) &&
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(env->fpus_vmstate & 0x3800) == 0); |
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return (!guess_mmx && (env->fpregs_format_vmstate == 1)); |
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} |
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|
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#define VMSTATE_FP_REGS(_field, _state, _n) \
|
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VMSTATE_ARRAY_TEST(_field, _state, _n, fpregs_is_0, vmstate_fpreg, FPReg), \ |
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VMSTATE_ARRAY_TEST(_field, _state, _n, fpregs_is_1_mmx, vmstate_fpreg_1_mmx, FPReg), \ |
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VMSTATE_ARRAY_TEST(_field, _state, _n, fpregs_is_1_no_mmx, vmstate_fpreg_1_no_mmx, FPReg) |
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|
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static bool version_is_5(void *opaque, int version_id) |
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{
|
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return version_id == 5; |
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} |
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|
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#ifdef TARGET_X86_64
|
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static bool less_than_7(void *opaque, int version_id) |
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{
|
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return version_id < 7; |
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} |
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|
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static int get_uint64_as_uint32(QEMUFile *f, void *pv, size_t size) |
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{
|
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uint64_t *v = pv; |
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*v = qemu_get_be32(f); |
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return 0; |
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} |
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|
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static void put_uint64_as_uint32(QEMUFile *f, void *pv, size_t size) |
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{
|
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uint64_t *v = pv; |
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qemu_put_be32(f, *v); |
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} |
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|
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static const VMStateInfo vmstate_hack_uint64_as_uint32 = { |
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.name = "uint64_as_uint32",
|
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.get = get_uint64_as_uint32, |
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.put = put_uint64_as_uint32, |
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}; |
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|
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#define VMSTATE_HACK_UINT32(_f, _s, _t) \
|
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VMSTATE_SINGLE_TEST(_f, _s, _t, 0, vmstate_hack_uint64_as_uint32, uint64_t)
|
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#endif
|
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|
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static void cpu_pre_save(void *opaque) |
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{
|
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X86CPU *cpu = opaque; |
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CPUX86State *env = &cpu->env; |
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int i;
|
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|
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/* FPU */
|
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env->fpus_vmstate = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11; |
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env->fptag_vmstate = 0;
|
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for(i = 0; i < 8; i++) { |
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env->fptag_vmstate |= ((!env->fptags[i]) << i); |
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} |
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|
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env->fpregs_format_vmstate = 0;
|
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|
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/*
|
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* Real mode guest segments register DPL should be zero.
|
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* Older KVM version were setting it wrongly.
|
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* Fixing it will allow live migration to host with unrestricted guest
|
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* support (otherwise the migration will fail with invalid guest state
|
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* error).
|
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*/
|
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if (!(env->cr[0] & CR0_PE_MASK) && |
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(env->segs[R_CS].flags >> DESC_DPL_SHIFT & 3) != 0) { |
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env->segs[R_CS].flags &= ~(env->segs[R_CS].flags & DESC_DPL_MASK); |
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env->segs[R_DS].flags &= ~(env->segs[R_DS].flags & DESC_DPL_MASK); |
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env->segs[R_ES].flags &= ~(env->segs[R_ES].flags & DESC_DPL_MASK); |
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env->segs[R_FS].flags &= ~(env->segs[R_FS].flags & DESC_DPL_MASK); |
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env->segs[R_GS].flags &= ~(env->segs[R_GS].flags & DESC_DPL_MASK); |
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env->segs[R_SS].flags &= ~(env->segs[R_SS].flags & DESC_DPL_MASK); |
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} |
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|
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} |
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|
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static int cpu_post_load(void *opaque, int version_id) |
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{
|
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X86CPU *cpu = opaque; |
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CPUX86State *env = &cpu->env; |
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int i;
|
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|
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/*
|
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* Real mode guest segments register DPL should be zero.
|
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* Older KVM version were setting it wrongly.
|
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* Fixing it will allow live migration from such host that don't have
|
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* restricted guest support to a host with unrestricted guest support
|
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* (otherwise the migration will fail with invalid guest state
|
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* error).
|
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*/
|
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if (!(env->cr[0] & CR0_PE_MASK) && |
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(env->segs[R_CS].flags >> DESC_DPL_SHIFT & 3) != 0) { |
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env->segs[R_CS].flags &= ~(env->segs[R_CS].flags & DESC_DPL_MASK); |
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env->segs[R_DS].flags &= ~(env->segs[R_DS].flags & DESC_DPL_MASK); |
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env->segs[R_ES].flags &= ~(env->segs[R_ES].flags & DESC_DPL_MASK); |
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env->segs[R_FS].flags &= ~(env->segs[R_FS].flags & DESC_DPL_MASK); |
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env->segs[R_GS].flags &= ~(env->segs[R_GS].flags & DESC_DPL_MASK); |
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env->segs[R_SS].flags &= ~(env->segs[R_SS].flags & DESC_DPL_MASK); |
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} |
| 313 |
|
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/* XXX: restore FPU round state */
|
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env->fpstt = (env->fpus_vmstate >> 11) & 7; |
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env->fpus = env->fpus_vmstate & ~0x3800;
|
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env->fptag_vmstate ^= 0xff;
|
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for(i = 0; i < 8; i++) { |
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env->fptags[i] = (env->fptag_vmstate >> i) & 1;
|
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} |
| 321 |
|
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cpu_breakpoint_remove_all(env, BP_CPU); |
| 323 |
cpu_watchpoint_remove_all(env, BP_CPU); |
| 324 |
for (i = 0; i < DR7_MAX_BP; i++) { |
| 325 |
hw_breakpoint_insert(env, i); |
| 326 |
} |
| 327 |
tlb_flush(env, 1);
|
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|
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return 0; |
| 330 |
} |
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|
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static bool async_pf_msr_needed(void *opaque) |
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{
|
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X86CPU *cpu = opaque; |
| 335 |
|
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return cpu->env.async_pf_en_msr != 0; |
| 337 |
} |
| 338 |
|
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static bool pv_eoi_msr_needed(void *opaque) |
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{
|
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X86CPU *cpu = opaque; |
| 342 |
|
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return cpu->env.pv_eoi_en_msr != 0; |
| 344 |
} |
| 345 |
|
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static bool steal_time_msr_needed(void *opaque) |
| 347 |
{
|
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X86CPU *cpu = opaque; |
| 349 |
|
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return cpu->env.steal_time_msr != 0; |
| 351 |
} |
| 352 |
|
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static const VMStateDescription vmstate_steal_time_msr = { |
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.name = "cpu/steal_time_msr",
|
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.version_id = 1,
|
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.minimum_version_id = 1,
|
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.minimum_version_id_old = 1,
|
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.fields = (VMStateField []) {
|
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VMSTATE_UINT64(env.steal_time_msr, X86CPU), |
| 360 |
VMSTATE_END_OF_LIST() |
| 361 |
} |
| 362 |
}; |
| 363 |
|
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static const VMStateDescription vmstate_async_pf_msr = { |
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.name = "cpu/async_pf_msr",
|
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.version_id = 1,
|
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.minimum_version_id = 1,
|
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.minimum_version_id_old = 1,
|
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.fields = (VMStateField []) {
|
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VMSTATE_UINT64(env.async_pf_en_msr, X86CPU), |
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VMSTATE_END_OF_LIST() |
| 372 |
} |
| 373 |
}; |
| 374 |
|
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static const VMStateDescription vmstate_pv_eoi_msr = { |
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.name = "cpu/async_pv_eoi_msr",
|
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.version_id = 1,
|
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.minimum_version_id = 1,
|
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.minimum_version_id_old = 1,
|
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.fields = (VMStateField []) {
|
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VMSTATE_UINT64(env.pv_eoi_en_msr, X86CPU), |
| 382 |
VMSTATE_END_OF_LIST() |
| 383 |
} |
| 384 |
}; |
| 385 |
|
| 386 |
static bool fpop_ip_dp_needed(void *opaque) |
| 387 |
{
|
| 388 |
X86CPU *cpu = opaque; |
| 389 |
CPUX86State *env = &cpu->env; |
| 390 |
|
| 391 |
return env->fpop != 0 || env->fpip != 0 || env->fpdp != 0; |
| 392 |
} |
| 393 |
|
| 394 |
static const VMStateDescription vmstate_fpop_ip_dp = { |
| 395 |
.name = "cpu/fpop_ip_dp",
|
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.version_id = 1,
|
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.minimum_version_id = 1,
|
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.minimum_version_id_old = 1,
|
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.fields = (VMStateField []) {
|
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VMSTATE_UINT16(env.fpop, X86CPU), |
| 401 |
VMSTATE_UINT64(env.fpip, X86CPU), |
| 402 |
VMSTATE_UINT64(env.fpdp, X86CPU), |
| 403 |
VMSTATE_END_OF_LIST() |
| 404 |
} |
| 405 |
}; |
| 406 |
|
| 407 |
static bool tsc_adjust_needed(void *opaque) |
| 408 |
{
|
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X86CPU *cpu = opaque; |
| 410 |
CPUX86State *env = &cpu->env; |
| 411 |
|
| 412 |
return env->tsc_adjust != 0; |
| 413 |
} |
| 414 |
|
| 415 |
static const VMStateDescription vmstate_msr_tsc_adjust = { |
| 416 |
.name = "cpu/msr_tsc_adjust",
|
| 417 |
.version_id = 1,
|
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.minimum_version_id = 1,
|
| 419 |
.minimum_version_id_old = 1,
|
| 420 |
.fields = (VMStateField[]) {
|
| 421 |
VMSTATE_UINT64(env.tsc_adjust, X86CPU), |
| 422 |
VMSTATE_END_OF_LIST() |
| 423 |
} |
| 424 |
}; |
| 425 |
|
| 426 |
static bool tscdeadline_needed(void *opaque) |
| 427 |
{
|
| 428 |
X86CPU *cpu = opaque; |
| 429 |
CPUX86State *env = &cpu->env; |
| 430 |
|
| 431 |
return env->tsc_deadline != 0; |
| 432 |
} |
| 433 |
|
| 434 |
static const VMStateDescription vmstate_msr_tscdeadline = { |
| 435 |
.name = "cpu/msr_tscdeadline",
|
| 436 |
.version_id = 1,
|
| 437 |
.minimum_version_id = 1,
|
| 438 |
.minimum_version_id_old = 1,
|
| 439 |
.fields = (VMStateField []) {
|
| 440 |
VMSTATE_UINT64(env.tsc_deadline, X86CPU), |
| 441 |
VMSTATE_END_OF_LIST() |
| 442 |
} |
| 443 |
}; |
| 444 |
|
| 445 |
static bool misc_enable_needed(void *opaque) |
| 446 |
{
|
| 447 |
X86CPU *cpu = opaque; |
| 448 |
CPUX86State *env = &cpu->env; |
| 449 |
|
| 450 |
return env->msr_ia32_misc_enable != MSR_IA32_MISC_ENABLE_DEFAULT;
|
| 451 |
} |
| 452 |
|
| 453 |
static bool feature_control_needed(void *opaque) |
| 454 |
{
|
| 455 |
X86CPU *cpu = opaque; |
| 456 |
CPUX86State *env = &cpu->env; |
| 457 |
|
| 458 |
return env->msr_ia32_feature_control != 0; |
| 459 |
} |
| 460 |
|
| 461 |
static const VMStateDescription vmstate_msr_ia32_misc_enable = { |
| 462 |
.name = "cpu/msr_ia32_misc_enable",
|
| 463 |
.version_id = 1,
|
| 464 |
.minimum_version_id = 1,
|
| 465 |
.minimum_version_id_old = 1,
|
| 466 |
.fields = (VMStateField []) {
|
| 467 |
VMSTATE_UINT64(env.msr_ia32_misc_enable, X86CPU), |
| 468 |
VMSTATE_END_OF_LIST() |
| 469 |
} |
| 470 |
}; |
| 471 |
|
| 472 |
static const VMStateDescription vmstate_msr_ia32_feature_control = { |
| 473 |
.name = "cpu/msr_ia32_feature_control",
|
| 474 |
.version_id = 1,
|
| 475 |
.minimum_version_id = 1,
|
| 476 |
.minimum_version_id_old = 1,
|
| 477 |
.fields = (VMStateField []) {
|
| 478 |
VMSTATE_UINT64(env.msr_ia32_feature_control, X86CPU), |
| 479 |
VMSTATE_END_OF_LIST() |
| 480 |
} |
| 481 |
}; |
| 482 |
|
| 483 |
static bool pmu_enable_needed(void *opaque) |
| 484 |
{
|
| 485 |
X86CPU *cpu = opaque; |
| 486 |
CPUX86State *env = &cpu->env; |
| 487 |
int i;
|
| 488 |
|
| 489 |
if (env->msr_fixed_ctr_ctrl || env->msr_global_ctrl ||
|
| 490 |
env->msr_global_status || env->msr_global_ovf_ctrl) {
|
| 491 |
return true; |
| 492 |
} |
| 493 |
for (i = 0; i < MAX_FIXED_COUNTERS; i++) { |
| 494 |
if (env->msr_fixed_counters[i]) {
|
| 495 |
return true; |
| 496 |
} |
| 497 |
} |
| 498 |
for (i = 0; i < MAX_GP_COUNTERS; i++) { |
| 499 |
if (env->msr_gp_counters[i] || env->msr_gp_evtsel[i]) {
|
| 500 |
return true; |
| 501 |
} |
| 502 |
} |
| 503 |
|
| 504 |
return false; |
| 505 |
} |
| 506 |
|
| 507 |
static const VMStateDescription vmstate_msr_architectural_pmu = { |
| 508 |
.name = "cpu/msr_architectural_pmu",
|
| 509 |
.version_id = 1,
|
| 510 |
.minimum_version_id = 1,
|
| 511 |
.minimum_version_id_old = 1,
|
| 512 |
.fields = (VMStateField []) {
|
| 513 |
VMSTATE_UINT64(env.msr_fixed_ctr_ctrl, X86CPU), |
| 514 |
VMSTATE_UINT64(env.msr_global_ctrl, X86CPU), |
| 515 |
VMSTATE_UINT64(env.msr_global_status, X86CPU), |
| 516 |
VMSTATE_UINT64(env.msr_global_ovf_ctrl, X86CPU), |
| 517 |
VMSTATE_UINT64_ARRAY(env.msr_fixed_counters, X86CPU, MAX_FIXED_COUNTERS), |
| 518 |
VMSTATE_UINT64_ARRAY(env.msr_gp_counters, X86CPU, MAX_GP_COUNTERS), |
| 519 |
VMSTATE_UINT64_ARRAY(env.msr_gp_evtsel, X86CPU, MAX_GP_COUNTERS), |
| 520 |
VMSTATE_END_OF_LIST() |
| 521 |
} |
| 522 |
}; |
| 523 |
|
| 524 |
static bool mpx_needed(void *opaque) |
| 525 |
{
|
| 526 |
X86CPU *cpu = opaque; |
| 527 |
CPUX86State *env = &cpu->env; |
| 528 |
unsigned int i; |
| 529 |
|
| 530 |
for (i = 0; i < 4; i++) { |
| 531 |
if (env->bnd_regs[i].lb || env->bnd_regs[i].ub) {
|
| 532 |
return true; |
| 533 |
} |
| 534 |
} |
| 535 |
|
| 536 |
if (env->bndcs_regs.cfgu || env->bndcs_regs.sts) {
|
| 537 |
return true; |
| 538 |
} |
| 539 |
|
| 540 |
return !!env->msr_bndcfgs;
|
| 541 |
} |
| 542 |
|
| 543 |
static const VMStateDescription vmstate_mpx = { |
| 544 |
.name = "cpu/mpx",
|
| 545 |
.version_id = 1,
|
| 546 |
.minimum_version_id = 1,
|
| 547 |
.minimum_version_id_old = 1,
|
| 548 |
.fields = (VMStateField[]) {
|
| 549 |
VMSTATE_BND_REGS(env.bnd_regs, X86CPU, 4),
|
| 550 |
VMSTATE_UINT64(env.bndcs_regs.cfgu, X86CPU), |
| 551 |
VMSTATE_UINT64(env.bndcs_regs.sts, X86CPU), |
| 552 |
VMSTATE_UINT64(env.msr_bndcfgs, X86CPU), |
| 553 |
VMSTATE_END_OF_LIST() |
| 554 |
} |
| 555 |
}; |
| 556 |
|
| 557 |
const VMStateDescription vmstate_x86_cpu = {
|
| 558 |
.name = "cpu",
|
| 559 |
.version_id = 12,
|
| 560 |
.minimum_version_id = 3,
|
| 561 |
.minimum_version_id_old = 3,
|
| 562 |
.pre_save = cpu_pre_save, |
| 563 |
.post_load = cpu_post_load, |
| 564 |
.fields = (VMStateField []) {
|
| 565 |
VMSTATE_UINTTL_ARRAY(env.regs, X86CPU, CPU_NB_REGS), |
| 566 |
VMSTATE_UINTTL(env.eip, X86CPU), |
| 567 |
VMSTATE_UINTTL(env.eflags, X86CPU), |
| 568 |
VMSTATE_UINT32(env.hflags, X86CPU), |
| 569 |
/* FPU */
|
| 570 |
VMSTATE_UINT16(env.fpuc, X86CPU), |
| 571 |
VMSTATE_UINT16(env.fpus_vmstate, X86CPU), |
| 572 |
VMSTATE_UINT16(env.fptag_vmstate, X86CPU), |
| 573 |
VMSTATE_UINT16(env.fpregs_format_vmstate, X86CPU), |
| 574 |
VMSTATE_FP_REGS(env.fpregs, X86CPU, 8),
|
| 575 |
|
| 576 |
VMSTATE_SEGMENT_ARRAY(env.segs, X86CPU, 6),
|
| 577 |
VMSTATE_SEGMENT(env.ldt, X86CPU), |
| 578 |
VMSTATE_SEGMENT(env.tr, X86CPU), |
| 579 |
VMSTATE_SEGMENT(env.gdt, X86CPU), |
| 580 |
VMSTATE_SEGMENT(env.idt, X86CPU), |
| 581 |
|
| 582 |
VMSTATE_UINT32(env.sysenter_cs, X86CPU), |
| 583 |
#ifdef TARGET_X86_64
|
| 584 |
/* Hack: In v7 size changed from 32 to 64 bits on x86_64 */
|
| 585 |
VMSTATE_HACK_UINT32(env.sysenter_esp, X86CPU, less_than_7), |
| 586 |
VMSTATE_HACK_UINT32(env.sysenter_eip, X86CPU, less_than_7), |
| 587 |
VMSTATE_UINTTL_V(env.sysenter_esp, X86CPU, 7),
|
| 588 |
VMSTATE_UINTTL_V(env.sysenter_eip, X86CPU, 7),
|
| 589 |
#else
|
| 590 |
VMSTATE_UINTTL(env.sysenter_esp, X86CPU), |
| 591 |
VMSTATE_UINTTL(env.sysenter_eip, X86CPU), |
| 592 |
#endif
|
| 593 |
|
| 594 |
VMSTATE_UINTTL(env.cr[0], X86CPU),
|
| 595 |
VMSTATE_UINTTL(env.cr[2], X86CPU),
|
| 596 |
VMSTATE_UINTTL(env.cr[3], X86CPU),
|
| 597 |
VMSTATE_UINTTL(env.cr[4], X86CPU),
|
| 598 |
VMSTATE_UINTTL_ARRAY(env.dr, X86CPU, 8),
|
| 599 |
/* MMU */
|
| 600 |
VMSTATE_INT32(env.a20_mask, X86CPU), |
| 601 |
/* XMM */
|
| 602 |
VMSTATE_UINT32(env.mxcsr, X86CPU), |
| 603 |
VMSTATE_XMM_REGS(env.xmm_regs, X86CPU, CPU_NB_REGS), |
| 604 |
|
| 605 |
#ifdef TARGET_X86_64
|
| 606 |
VMSTATE_UINT64(env.efer, X86CPU), |
| 607 |
VMSTATE_UINT64(env.star, X86CPU), |
| 608 |
VMSTATE_UINT64(env.lstar, X86CPU), |
| 609 |
VMSTATE_UINT64(env.cstar, X86CPU), |
| 610 |
VMSTATE_UINT64(env.fmask, X86CPU), |
| 611 |
VMSTATE_UINT64(env.kernelgsbase, X86CPU), |
| 612 |
#endif
|
| 613 |
VMSTATE_UINT32_V(env.smbase, X86CPU, 4),
|
| 614 |
|
| 615 |
VMSTATE_UINT64_V(env.pat, X86CPU, 5),
|
| 616 |
VMSTATE_UINT32_V(env.hflags2, X86CPU, 5),
|
| 617 |
|
| 618 |
VMSTATE_UINT32_TEST(parent_obj.halted, X86CPU, version_is_5), |
| 619 |
VMSTATE_UINT64_V(env.vm_hsave, X86CPU, 5),
|
| 620 |
VMSTATE_UINT64_V(env.vm_vmcb, X86CPU, 5),
|
| 621 |
VMSTATE_UINT64_V(env.tsc_offset, X86CPU, 5),
|
| 622 |
VMSTATE_UINT64_V(env.intercept, X86CPU, 5),
|
| 623 |
VMSTATE_UINT16_V(env.intercept_cr_read, X86CPU, 5),
|
| 624 |
VMSTATE_UINT16_V(env.intercept_cr_write, X86CPU, 5),
|
| 625 |
VMSTATE_UINT16_V(env.intercept_dr_read, X86CPU, 5),
|
| 626 |
VMSTATE_UINT16_V(env.intercept_dr_write, X86CPU, 5),
|
| 627 |
VMSTATE_UINT32_V(env.intercept_exceptions, X86CPU, 5),
|
| 628 |
VMSTATE_UINT8_V(env.v_tpr, X86CPU, 5),
|
| 629 |
/* MTRRs */
|
| 630 |
VMSTATE_UINT64_ARRAY_V(env.mtrr_fixed, X86CPU, 11, 8), |
| 631 |
VMSTATE_UINT64_V(env.mtrr_deftype, X86CPU, 8),
|
| 632 |
VMSTATE_MTRR_VARS(env.mtrr_var, X86CPU, 8, 8), |
| 633 |
/* KVM-related states */
|
| 634 |
VMSTATE_INT32_V(env.interrupt_injected, X86CPU, 9),
|
| 635 |
VMSTATE_UINT32_V(env.mp_state, X86CPU, 9),
|
| 636 |
VMSTATE_UINT64_V(env.tsc, X86CPU, 9),
|
| 637 |
VMSTATE_INT32_V(env.exception_injected, X86CPU, 11),
|
| 638 |
VMSTATE_UINT8_V(env.soft_interrupt, X86CPU, 11),
|
| 639 |
VMSTATE_UINT8_V(env.nmi_injected, X86CPU, 11),
|
| 640 |
VMSTATE_UINT8_V(env.nmi_pending, X86CPU, 11),
|
| 641 |
VMSTATE_UINT8_V(env.has_error_code, X86CPU, 11),
|
| 642 |
VMSTATE_UINT32_V(env.sipi_vector, X86CPU, 11),
|
| 643 |
/* MCE */
|
| 644 |
VMSTATE_UINT64_V(env.mcg_cap, X86CPU, 10),
|
| 645 |
VMSTATE_UINT64_V(env.mcg_status, X86CPU, 10),
|
| 646 |
VMSTATE_UINT64_V(env.mcg_ctl, X86CPU, 10),
|
| 647 |
VMSTATE_UINT64_ARRAY_V(env.mce_banks, X86CPU, MCE_BANKS_DEF * 4, 10), |
| 648 |
/* rdtscp */
|
| 649 |
VMSTATE_UINT64_V(env.tsc_aux, X86CPU, 11),
|
| 650 |
/* KVM pvclock msr */
|
| 651 |
VMSTATE_UINT64_V(env.system_time_msr, X86CPU, 11),
|
| 652 |
VMSTATE_UINT64_V(env.wall_clock_msr, X86CPU, 11),
|
| 653 |
/* XSAVE related fields */
|
| 654 |
VMSTATE_UINT64_V(env.xcr0, X86CPU, 12),
|
| 655 |
VMSTATE_UINT64_V(env.xstate_bv, X86CPU, 12),
|
| 656 |
VMSTATE_YMMH_REGS_VARS(env.ymmh_regs, X86CPU, CPU_NB_REGS, 12),
|
| 657 |
VMSTATE_END_OF_LIST() |
| 658 |
/* The above list is not sorted /wrt version numbers, watch out! */
|
| 659 |
}, |
| 660 |
.subsections = (VMStateSubsection []) {
|
| 661 |
{
|
| 662 |
.vmsd = &vmstate_async_pf_msr, |
| 663 |
.needed = async_pf_msr_needed, |
| 664 |
} , {
|
| 665 |
.vmsd = &vmstate_pv_eoi_msr, |
| 666 |
.needed = pv_eoi_msr_needed, |
| 667 |
} , {
|
| 668 |
.vmsd = &vmstate_steal_time_msr, |
| 669 |
.needed = steal_time_msr_needed, |
| 670 |
} , {
|
| 671 |
.vmsd = &vmstate_fpop_ip_dp, |
| 672 |
.needed = fpop_ip_dp_needed, |
| 673 |
}, {
|
| 674 |
.vmsd = &vmstate_msr_tsc_adjust, |
| 675 |
.needed = tsc_adjust_needed, |
| 676 |
}, {
|
| 677 |
.vmsd = &vmstate_msr_tscdeadline, |
| 678 |
.needed = tscdeadline_needed, |
| 679 |
}, {
|
| 680 |
.vmsd = &vmstate_msr_ia32_misc_enable, |
| 681 |
.needed = misc_enable_needed, |
| 682 |
}, {
|
| 683 |
.vmsd = &vmstate_msr_ia32_feature_control, |
| 684 |
.needed = feature_control_needed, |
| 685 |
}, {
|
| 686 |
.vmsd = &vmstate_msr_architectural_pmu, |
| 687 |
.needed = pmu_enable_needed, |
| 688 |
} , {
|
| 689 |
.vmsd = &vmstate_mpx, |
| 690 |
.needed = mpx_needed, |
| 691 |
} , {
|
| 692 |
/* empty */
|
| 693 |
} |
| 694 |
} |
| 695 |
}; |