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1 | 6af0bf9c | bellard | /*
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2 | 6af0bf9c | bellard | * MIPS emulation micro-operations for qemu.
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3 | 6af0bf9c | bellard | *
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4 | 6af0bf9c | bellard | * Copyright (c) 2004-2005 Jocelyn Mayer
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5 | 6ea83fed | bellard | * Copyright (c) 2006 Marius Groeger (FPU operations)
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6 | 6af0bf9c | bellard | *
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7 | 6af0bf9c | bellard | * This library is free software; you can redistribute it and/or
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8 | 6af0bf9c | bellard | * modify it under the terms of the GNU Lesser General Public
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9 | 6af0bf9c | bellard | * License as published by the Free Software Foundation; either
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10 | 6af0bf9c | bellard | * version 2 of the License, or (at your option) any later version.
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11 | 6af0bf9c | bellard | *
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12 | 6af0bf9c | bellard | * This library is distributed in the hope that it will be useful,
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13 | 6af0bf9c | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 | 6af0bf9c | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 | 6af0bf9c | bellard | * Lesser General Public License for more details.
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16 | 6af0bf9c | bellard | *
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17 | 6af0bf9c | bellard | * You should have received a copy of the GNU Lesser General Public
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18 | 6af0bf9c | bellard | * License along with this library; if not, write to the Free Software
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19 | 6af0bf9c | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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20 | 6af0bf9c | bellard | */
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21 | 6af0bf9c | bellard | |
22 | 6af0bf9c | bellard | #include "config.h" |
23 | 6af0bf9c | bellard | #include "exec.h" |
24 | 6af0bf9c | bellard | |
25 | 1b351e52 | bellard | #ifndef CALL_FROM_TB0
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26 | 1b351e52 | bellard | #define CALL_FROM_TB0(func) func();
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27 | 1b351e52 | bellard | #endif
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28 | 1b351e52 | bellard | #ifndef CALL_FROM_TB1
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29 | 1b351e52 | bellard | #define CALL_FROM_TB1(func, arg0) func(arg0);
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30 | 1b351e52 | bellard | #endif
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31 | 1b351e52 | bellard | #ifndef CALL_FROM_TB1_CONST16
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32 | 1b351e52 | bellard | #define CALL_FROM_TB1_CONST16(func, arg0) CALL_FROM_TB1(func, arg0);
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33 | 1b351e52 | bellard | #endif
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34 | 1b351e52 | bellard | #ifndef CALL_FROM_TB2
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35 | 1b351e52 | bellard | #define CALL_FROM_TB2(func, arg0, arg1) func(arg0, arg1);
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36 | 1b351e52 | bellard | #endif
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37 | 1b351e52 | bellard | #ifndef CALL_FROM_TB2_CONST16
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38 | 1b351e52 | bellard | #define CALL_FROM_TB2_CONST16(func, arg0, arg1) \
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39 | 1b351e52 | bellard | CALL_FROM_TB2(func, arg0, arg1); |
40 | 1b351e52 | bellard | #endif
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41 | 1b351e52 | bellard | #ifndef CALL_FROM_TB3
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42 | 1b351e52 | bellard | #define CALL_FROM_TB3(func, arg0, arg1, arg2) func(arg0, arg1, arg2);
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43 | 1b351e52 | bellard | #endif
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44 | 1b351e52 | bellard | #ifndef CALL_FROM_TB4
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45 | 1b351e52 | bellard | #define CALL_FROM_TB4(func, arg0, arg1, arg2, arg3) \
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46 | 1b351e52 | bellard | func(arg0, arg1, arg2, arg3); |
47 | 1b351e52 | bellard | #endif
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48 | 1b351e52 | bellard | |
49 | 6af0bf9c | bellard | #define REG 1 |
50 | 6af0bf9c | bellard | #include "op_template.c" |
51 | 6af0bf9c | bellard | #undef REG
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52 | 6af0bf9c | bellard | #define REG 2 |
53 | 6af0bf9c | bellard | #include "op_template.c" |
54 | 6af0bf9c | bellard | #undef REG
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55 | 6af0bf9c | bellard | #define REG 3 |
56 | 6af0bf9c | bellard | #include "op_template.c" |
57 | 6af0bf9c | bellard | #undef REG
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58 | 6af0bf9c | bellard | #define REG 4 |
59 | 6af0bf9c | bellard | #include "op_template.c" |
60 | 6af0bf9c | bellard | #undef REG
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61 | 6af0bf9c | bellard | #define REG 5 |
62 | 6af0bf9c | bellard | #include "op_template.c" |
63 | 6af0bf9c | bellard | #undef REG
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64 | 6af0bf9c | bellard | #define REG 6 |
65 | 6af0bf9c | bellard | #include "op_template.c" |
66 | 6af0bf9c | bellard | #undef REG
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67 | 6af0bf9c | bellard | #define REG 7 |
68 | 6af0bf9c | bellard | #include "op_template.c" |
69 | 6af0bf9c | bellard | #undef REG
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70 | 6af0bf9c | bellard | #define REG 8 |
71 | 6af0bf9c | bellard | #include "op_template.c" |
72 | 6af0bf9c | bellard | #undef REG
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73 | 6af0bf9c | bellard | #define REG 9 |
74 | 6af0bf9c | bellard | #include "op_template.c" |
75 | 6af0bf9c | bellard | #undef REG
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76 | 6af0bf9c | bellard | #define REG 10 |
77 | 6af0bf9c | bellard | #include "op_template.c" |
78 | 6af0bf9c | bellard | #undef REG
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79 | 6af0bf9c | bellard | #define REG 11 |
80 | 6af0bf9c | bellard | #include "op_template.c" |
81 | 6af0bf9c | bellard | #undef REG
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82 | 6af0bf9c | bellard | #define REG 12 |
83 | 6af0bf9c | bellard | #include "op_template.c" |
84 | 6af0bf9c | bellard | #undef REG
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85 | 6af0bf9c | bellard | #define REG 13 |
86 | 6af0bf9c | bellard | #include "op_template.c" |
87 | 6af0bf9c | bellard | #undef REG
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88 | 6af0bf9c | bellard | #define REG 14 |
89 | 6af0bf9c | bellard | #include "op_template.c" |
90 | 6af0bf9c | bellard | #undef REG
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91 | 6af0bf9c | bellard | #define REG 15 |
92 | 6af0bf9c | bellard | #include "op_template.c" |
93 | 6af0bf9c | bellard | #undef REG
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94 | 6af0bf9c | bellard | #define REG 16 |
95 | 6af0bf9c | bellard | #include "op_template.c" |
96 | 6af0bf9c | bellard | #undef REG
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97 | 6af0bf9c | bellard | #define REG 17 |
98 | 6af0bf9c | bellard | #include "op_template.c" |
99 | 6af0bf9c | bellard | #undef REG
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100 | 6af0bf9c | bellard | #define REG 18 |
101 | 6af0bf9c | bellard | #include "op_template.c" |
102 | 6af0bf9c | bellard | #undef REG
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103 | 6af0bf9c | bellard | #define REG 19 |
104 | 6af0bf9c | bellard | #include "op_template.c" |
105 | 6af0bf9c | bellard | #undef REG
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106 | 6af0bf9c | bellard | #define REG 20 |
107 | 6af0bf9c | bellard | #include "op_template.c" |
108 | 6af0bf9c | bellard | #undef REG
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109 | 6af0bf9c | bellard | #define REG 21 |
110 | 6af0bf9c | bellard | #include "op_template.c" |
111 | 6af0bf9c | bellard | #undef REG
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112 | 6af0bf9c | bellard | #define REG 22 |
113 | 6af0bf9c | bellard | #include "op_template.c" |
114 | 6af0bf9c | bellard | #undef REG
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115 | 6af0bf9c | bellard | #define REG 23 |
116 | 6af0bf9c | bellard | #include "op_template.c" |
117 | 6af0bf9c | bellard | #undef REG
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118 | 6af0bf9c | bellard | #define REG 24 |
119 | 6af0bf9c | bellard | #include "op_template.c" |
120 | 6af0bf9c | bellard | #undef REG
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121 | 6af0bf9c | bellard | #define REG 25 |
122 | 6af0bf9c | bellard | #include "op_template.c" |
123 | 6af0bf9c | bellard | #undef REG
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124 | 6af0bf9c | bellard | #define REG 26 |
125 | 6af0bf9c | bellard | #include "op_template.c" |
126 | 6af0bf9c | bellard | #undef REG
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127 | 6af0bf9c | bellard | #define REG 27 |
128 | 6af0bf9c | bellard | #include "op_template.c" |
129 | 6af0bf9c | bellard | #undef REG
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130 | 6af0bf9c | bellard | #define REG 28 |
131 | 6af0bf9c | bellard | #include "op_template.c" |
132 | 6af0bf9c | bellard | #undef REG
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133 | 6af0bf9c | bellard | #define REG 29 |
134 | 6af0bf9c | bellard | #include "op_template.c" |
135 | 6af0bf9c | bellard | #undef REG
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136 | 6af0bf9c | bellard | #define REG 30 |
137 | 6af0bf9c | bellard | #include "op_template.c" |
138 | 6af0bf9c | bellard | #undef REG
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139 | 6af0bf9c | bellard | #define REG 31 |
140 | 6af0bf9c | bellard | #include "op_template.c" |
141 | 6af0bf9c | bellard | #undef REG
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142 | 6af0bf9c | bellard | |
143 | 6af0bf9c | bellard | #define TN T0
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144 | 6af0bf9c | bellard | #include "op_template.c" |
145 | 6af0bf9c | bellard | #undef TN
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146 | 6af0bf9c | bellard | #define TN T1
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147 | 6af0bf9c | bellard | #include "op_template.c" |
148 | 6af0bf9c | bellard | #undef TN
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149 | 6af0bf9c | bellard | #define TN T2
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150 | 6af0bf9c | bellard | #include "op_template.c" |
151 | 6af0bf9c | bellard | #undef TN
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152 | 6af0bf9c | bellard | |
153 | 6ea83fed | bellard | #ifdef MIPS_USES_FPU
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154 | 6ea83fed | bellard | |
155 | 6ea83fed | bellard | #define SFREG 0 |
156 | 6ea83fed | bellard | #define DFREG 0 |
157 | 6ea83fed | bellard | #include "fop_template.c" |
158 | 6ea83fed | bellard | #undef SFREG
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159 | 6ea83fed | bellard | #undef DFREG
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160 | 6ea83fed | bellard | #define SFREG 1 |
161 | 6ea83fed | bellard | #include "fop_template.c" |
162 | 6ea83fed | bellard | #undef SFREG
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163 | 6ea83fed | bellard | #define SFREG 2 |
164 | 6ea83fed | bellard | #define DFREG 2 |
165 | 6ea83fed | bellard | #include "fop_template.c" |
166 | 6ea83fed | bellard | #undef SFREG
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167 | 6ea83fed | bellard | #undef DFREG
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168 | 6ea83fed | bellard | #define SFREG 3 |
169 | 6ea83fed | bellard | #include "fop_template.c" |
170 | 6ea83fed | bellard | #undef SFREG
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171 | 6ea83fed | bellard | #define SFREG 4 |
172 | 6ea83fed | bellard | #define DFREG 4 |
173 | 6ea83fed | bellard | #include "fop_template.c" |
174 | 6ea83fed | bellard | #undef SFREG
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175 | 6ea83fed | bellard | #undef DFREG
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176 | 6ea83fed | bellard | #define SFREG 5 |
177 | 6ea83fed | bellard | #include "fop_template.c" |
178 | 6ea83fed | bellard | #undef SFREG
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179 | 6ea83fed | bellard | #define SFREG 6 |
180 | 6ea83fed | bellard | #define DFREG 6 |
181 | 6ea83fed | bellard | #include "fop_template.c" |
182 | 6ea83fed | bellard | #undef SFREG
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183 | 6ea83fed | bellard | #undef DFREG
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184 | 6ea83fed | bellard | #define SFREG 7 |
185 | 6ea83fed | bellard | #include "fop_template.c" |
186 | 6ea83fed | bellard | #undef SFREG
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187 | 6ea83fed | bellard | #define SFREG 8 |
188 | 6ea83fed | bellard | #define DFREG 8 |
189 | 6ea83fed | bellard | #include "fop_template.c" |
190 | 6ea83fed | bellard | #undef SFREG
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191 | 6ea83fed | bellard | #undef DFREG
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192 | 6ea83fed | bellard | #define SFREG 9 |
193 | 6ea83fed | bellard | #include "fop_template.c" |
194 | 6ea83fed | bellard | #undef SFREG
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195 | 6ea83fed | bellard | #define SFREG 10 |
196 | 6ea83fed | bellard | #define DFREG 10 |
197 | 6ea83fed | bellard | #include "fop_template.c" |
198 | 6ea83fed | bellard | #undef SFREG
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199 | 6ea83fed | bellard | #undef DFREG
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200 | 6ea83fed | bellard | #define SFREG 11 |
201 | 6ea83fed | bellard | #include "fop_template.c" |
202 | 6ea83fed | bellard | #undef SFREG
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203 | 6ea83fed | bellard | #define SFREG 12 |
204 | 6ea83fed | bellard | #define DFREG 12 |
205 | 6ea83fed | bellard | #include "fop_template.c" |
206 | 6ea83fed | bellard | #undef SFREG
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207 | 6ea83fed | bellard | #undef DFREG
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208 | 6ea83fed | bellard | #define SFREG 13 |
209 | 6ea83fed | bellard | #include "fop_template.c" |
210 | 6ea83fed | bellard | #undef SFREG
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211 | 6ea83fed | bellard | #define SFREG 14 |
212 | 6ea83fed | bellard | #define DFREG 14 |
213 | 6ea83fed | bellard | #include "fop_template.c" |
214 | 6ea83fed | bellard | #undef SFREG
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215 | 6ea83fed | bellard | #undef DFREG
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216 | 6ea83fed | bellard | #define SFREG 15 |
217 | 6ea83fed | bellard | #include "fop_template.c" |
218 | 6ea83fed | bellard | #undef SFREG
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219 | 6ea83fed | bellard | #define SFREG 16 |
220 | 6ea83fed | bellard | #define DFREG 16 |
221 | 6ea83fed | bellard | #include "fop_template.c" |
222 | 6ea83fed | bellard | #undef SFREG
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223 | 6ea83fed | bellard | #undef DFREG
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224 | 6ea83fed | bellard | #define SFREG 17 |
225 | 6ea83fed | bellard | #include "fop_template.c" |
226 | 6ea83fed | bellard | #undef SFREG
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227 | 6ea83fed | bellard | #define SFREG 18 |
228 | 6ea83fed | bellard | #define DFREG 18 |
229 | 6ea83fed | bellard | #include "fop_template.c" |
230 | 6ea83fed | bellard | #undef SFREG
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231 | 6ea83fed | bellard | #undef DFREG
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232 | 6ea83fed | bellard | #define SFREG 19 |
233 | 6ea83fed | bellard | #include "fop_template.c" |
234 | 6ea83fed | bellard | #undef SFREG
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235 | 6ea83fed | bellard | #define SFREG 20 |
236 | 6ea83fed | bellard | #define DFREG 20 |
237 | 6ea83fed | bellard | #include "fop_template.c" |
238 | 6ea83fed | bellard | #undef SFREG
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239 | 6ea83fed | bellard | #undef DFREG
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240 | 6ea83fed | bellard | #define SFREG 21 |
241 | 6ea83fed | bellard | #include "fop_template.c" |
242 | 6ea83fed | bellard | #undef SFREG
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243 | 6ea83fed | bellard | #define SFREG 22 |
244 | 6ea83fed | bellard | #define DFREG 22 |
245 | 6ea83fed | bellard | #include "fop_template.c" |
246 | 6ea83fed | bellard | #undef SFREG
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247 | 6ea83fed | bellard | #undef DFREG
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248 | 6ea83fed | bellard | #define SFREG 23 |
249 | 6ea83fed | bellard | #include "fop_template.c" |
250 | 6ea83fed | bellard | #undef SFREG
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251 | 6ea83fed | bellard | #define SFREG 24 |
252 | 6ea83fed | bellard | #define DFREG 24 |
253 | 6ea83fed | bellard | #include "fop_template.c" |
254 | 6ea83fed | bellard | #undef SFREG
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255 | 6ea83fed | bellard | #undef DFREG
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256 | 6ea83fed | bellard | #define SFREG 25 |
257 | 6ea83fed | bellard | #include "fop_template.c" |
258 | 6ea83fed | bellard | #undef SFREG
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259 | 6ea83fed | bellard | #define SFREG 26 |
260 | 6ea83fed | bellard | #define DFREG 26 |
261 | 6ea83fed | bellard | #include "fop_template.c" |
262 | 6ea83fed | bellard | #undef SFREG
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263 | 6ea83fed | bellard | #undef DFREG
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264 | 6ea83fed | bellard | #define SFREG 27 |
265 | 6ea83fed | bellard | #include "fop_template.c" |
266 | 6ea83fed | bellard | #undef SFREG
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267 | 6ea83fed | bellard | #define SFREG 28 |
268 | 6ea83fed | bellard | #define DFREG 28 |
269 | 6ea83fed | bellard | #include "fop_template.c" |
270 | 6ea83fed | bellard | #undef SFREG
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271 | 6ea83fed | bellard | #undef DFREG
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272 | 6ea83fed | bellard | #define SFREG 29 |
273 | 6ea83fed | bellard | #include "fop_template.c" |
274 | 6ea83fed | bellard | #undef SFREG
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275 | 6ea83fed | bellard | #define SFREG 30 |
276 | 6ea83fed | bellard | #define DFREG 30 |
277 | 6ea83fed | bellard | #include "fop_template.c" |
278 | 6ea83fed | bellard | #undef SFREG
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279 | 6ea83fed | bellard | #undef DFREG
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280 | 6ea83fed | bellard | #define SFREG 31 |
281 | 6ea83fed | bellard | #include "fop_template.c" |
282 | 6ea83fed | bellard | #undef SFREG
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283 | 6ea83fed | bellard | |
284 | 6ea83fed | bellard | #define FTN
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285 | 6ea83fed | bellard | #include "fop_template.c" |
286 | 6ea83fed | bellard | #undef FTN
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287 | 6ea83fed | bellard | |
288 | 6ea83fed | bellard | #endif
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289 | 6ea83fed | bellard | |
290 | 6af0bf9c | bellard | void op_dup_T0 (void) |
291 | 6af0bf9c | bellard | { |
292 | 6af0bf9c | bellard | T2 = T0; |
293 | 6af0bf9c | bellard | RETURN(); |
294 | 6af0bf9c | bellard | } |
295 | 6af0bf9c | bellard | |
296 | 6af0bf9c | bellard | void op_load_HI (void) |
297 | 6af0bf9c | bellard | { |
298 | 6af0bf9c | bellard | T0 = env->HI; |
299 | 6af0bf9c | bellard | RETURN(); |
300 | 6af0bf9c | bellard | } |
301 | 6af0bf9c | bellard | |
302 | 6af0bf9c | bellard | void op_store_HI (void) |
303 | 6af0bf9c | bellard | { |
304 | 6af0bf9c | bellard | env->HI = T0; |
305 | 6af0bf9c | bellard | RETURN(); |
306 | 6af0bf9c | bellard | } |
307 | 6af0bf9c | bellard | |
308 | 6af0bf9c | bellard | void op_load_LO (void) |
309 | 6af0bf9c | bellard | { |
310 | 6af0bf9c | bellard | T0 = env->LO; |
311 | 6af0bf9c | bellard | RETURN(); |
312 | 6af0bf9c | bellard | } |
313 | 6af0bf9c | bellard | |
314 | 6af0bf9c | bellard | void op_store_LO (void) |
315 | 6af0bf9c | bellard | { |
316 | 6af0bf9c | bellard | env->LO = T0; |
317 | 6af0bf9c | bellard | RETURN(); |
318 | 6af0bf9c | bellard | } |
319 | 6af0bf9c | bellard | |
320 | 6af0bf9c | bellard | /* Load and store */
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321 | 6af0bf9c | bellard | #define MEMSUFFIX _raw
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322 | 6af0bf9c | bellard | #include "op_mem.c" |
323 | 6af0bf9c | bellard | #undef MEMSUFFIX
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324 | 6af0bf9c | bellard | #if !defined(CONFIG_USER_ONLY)
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325 | 6af0bf9c | bellard | #define MEMSUFFIX _user
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326 | 6af0bf9c | bellard | #include "op_mem.c" |
327 | 6af0bf9c | bellard | #undef MEMSUFFIX
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328 | 6af0bf9c | bellard | |
329 | 6af0bf9c | bellard | #define MEMSUFFIX _kernel
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330 | 6af0bf9c | bellard | #include "op_mem.c" |
331 | 6af0bf9c | bellard | #undef MEMSUFFIX
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332 | 6af0bf9c | bellard | #endif
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333 | 6af0bf9c | bellard | |
334 | 6af0bf9c | bellard | /* Arithmetic */
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335 | 6af0bf9c | bellard | void op_add (void) |
336 | 6af0bf9c | bellard | { |
337 | 6af0bf9c | bellard | T0 += T1; |
338 | 6af0bf9c | bellard | RETURN(); |
339 | 6af0bf9c | bellard | } |
340 | 6af0bf9c | bellard | |
341 | 6af0bf9c | bellard | void op_addo (void) |
342 | 6af0bf9c | bellard | { |
343 | 6af0bf9c | bellard | target_ulong tmp; |
344 | 6af0bf9c | bellard | |
345 | 6af0bf9c | bellard | tmp = T0; |
346 | 6af0bf9c | bellard | T0 += T1; |
347 | 76e050c2 | bellard | if (((tmp ^ T1 ^ (-1)) & (T0 ^ T1)) >> 31) { |
348 | 76e050c2 | bellard | /* operands of same sign, result different sign */
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349 | 4ad40f36 | bellard | CALL_FROM_TB1(do_raise_exception_direct, EXCP_OVERFLOW); |
350 | 6af0bf9c | bellard | } |
351 | 6af0bf9c | bellard | RETURN(); |
352 | 6af0bf9c | bellard | } |
353 | 6af0bf9c | bellard | |
354 | 6af0bf9c | bellard | void op_sub (void) |
355 | 6af0bf9c | bellard | { |
356 | 6af0bf9c | bellard | T0 -= T1; |
357 | 6af0bf9c | bellard | RETURN(); |
358 | 6af0bf9c | bellard | } |
359 | 6af0bf9c | bellard | |
360 | 6af0bf9c | bellard | void op_subo (void) |
361 | 6af0bf9c | bellard | { |
362 | 6af0bf9c | bellard | target_ulong tmp; |
363 | 6af0bf9c | bellard | |
364 | 6af0bf9c | bellard | tmp = T0; |
365 | 6af0bf9c | bellard | T0 = (int32_t)T0 - (int32_t)T1; |
366 | 76e050c2 | bellard | if (((tmp ^ T1) & (tmp ^ T0)) >> 31) { |
367 | 76e050c2 | bellard | /* operands of different sign, first operand and result different sign */
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368 | 4ad40f36 | bellard | CALL_FROM_TB1(do_raise_exception_direct, EXCP_OVERFLOW); |
369 | 6af0bf9c | bellard | } |
370 | 6af0bf9c | bellard | RETURN(); |
371 | 6af0bf9c | bellard | } |
372 | 6af0bf9c | bellard | |
373 | 6af0bf9c | bellard | void op_mul (void) |
374 | 6af0bf9c | bellard | { |
375 | 6af0bf9c | bellard | T0 = (int32_t)T0 * (int32_t)T1; |
376 | 6af0bf9c | bellard | RETURN(); |
377 | 6af0bf9c | bellard | } |
378 | 6af0bf9c | bellard | |
379 | 6af0bf9c | bellard | void op_div (void) |
380 | 6af0bf9c | bellard | { |
381 | 6af0bf9c | bellard | if (T1 != 0) { |
382 | 6af0bf9c | bellard | env->LO = (int32_t)T0 / (int32_t)T1; |
383 | 6af0bf9c | bellard | env->HI = (int32_t)T0 % (int32_t)T1; |
384 | 6af0bf9c | bellard | } |
385 | 6af0bf9c | bellard | RETURN(); |
386 | 6af0bf9c | bellard | } |
387 | 6af0bf9c | bellard | |
388 | 6af0bf9c | bellard | void op_divu (void) |
389 | 6af0bf9c | bellard | { |
390 | 6af0bf9c | bellard | if (T1 != 0) { |
391 | 6af0bf9c | bellard | env->LO = T0 / T1; |
392 | 6af0bf9c | bellard | env->HI = T0 % T1; |
393 | 6af0bf9c | bellard | } |
394 | 6af0bf9c | bellard | RETURN(); |
395 | 6af0bf9c | bellard | } |
396 | 6af0bf9c | bellard | |
397 | 6af0bf9c | bellard | /* Logical */
|
398 | 6af0bf9c | bellard | void op_and (void) |
399 | 6af0bf9c | bellard | { |
400 | 6af0bf9c | bellard | T0 &= T1; |
401 | 6af0bf9c | bellard | RETURN(); |
402 | 6af0bf9c | bellard | } |
403 | 6af0bf9c | bellard | |
404 | 6af0bf9c | bellard | void op_nor (void) |
405 | 6af0bf9c | bellard | { |
406 | 6af0bf9c | bellard | T0 = ~(T0 | T1); |
407 | 6af0bf9c | bellard | RETURN(); |
408 | 6af0bf9c | bellard | } |
409 | 6af0bf9c | bellard | |
410 | 6af0bf9c | bellard | void op_or (void) |
411 | 6af0bf9c | bellard | { |
412 | 6af0bf9c | bellard | T0 |= T1; |
413 | 6af0bf9c | bellard | RETURN(); |
414 | 6af0bf9c | bellard | } |
415 | 6af0bf9c | bellard | |
416 | 6af0bf9c | bellard | void op_xor (void) |
417 | 6af0bf9c | bellard | { |
418 | 6af0bf9c | bellard | T0 ^= T1; |
419 | 6af0bf9c | bellard | RETURN(); |
420 | 6af0bf9c | bellard | } |
421 | 6af0bf9c | bellard | |
422 | 6af0bf9c | bellard | void op_sll (void) |
423 | 6af0bf9c | bellard | { |
424 | 6af0bf9c | bellard | T0 = T0 << T1; |
425 | 6af0bf9c | bellard | RETURN(); |
426 | 6af0bf9c | bellard | } |
427 | 6af0bf9c | bellard | |
428 | 6af0bf9c | bellard | void op_sra (void) |
429 | 6af0bf9c | bellard | { |
430 | 6af0bf9c | bellard | T0 = (int32_t)T0 >> T1; |
431 | 6af0bf9c | bellard | RETURN(); |
432 | 6af0bf9c | bellard | } |
433 | 6af0bf9c | bellard | |
434 | 6af0bf9c | bellard | void op_srl (void) |
435 | 6af0bf9c | bellard | { |
436 | 6af0bf9c | bellard | T0 = T0 >> T1; |
437 | 6af0bf9c | bellard | RETURN(); |
438 | 6af0bf9c | bellard | } |
439 | 6af0bf9c | bellard | |
440 | 7a387fff | ths | void op_rotr (void) |
441 | 7a387fff | ths | { |
442 | 7a387fff | ths | target_ulong tmp; |
443 | 7a387fff | ths | |
444 | 7a387fff | ths | if (T1) {
|
445 | 7a387fff | ths | tmp = T0 << (0x20 - T1);
|
446 | 7a387fff | ths | T0 = (T0 >> T1) | tmp; |
447 | 7a387fff | ths | } else
|
448 | 7a387fff | ths | T0 = T1; |
449 | 7a387fff | ths | RETURN(); |
450 | 7a387fff | ths | } |
451 | 7a387fff | ths | |
452 | 6af0bf9c | bellard | void op_sllv (void) |
453 | 6af0bf9c | bellard | { |
454 | 6af0bf9c | bellard | T0 = T1 << (T0 & 0x1F);
|
455 | 6af0bf9c | bellard | RETURN(); |
456 | 6af0bf9c | bellard | } |
457 | 6af0bf9c | bellard | |
458 | 6af0bf9c | bellard | void op_srav (void) |
459 | 6af0bf9c | bellard | { |
460 | 6af0bf9c | bellard | T0 = (int32_t)T1 >> (T0 & 0x1F);
|
461 | 6af0bf9c | bellard | RETURN(); |
462 | 6af0bf9c | bellard | } |
463 | 6af0bf9c | bellard | |
464 | 6af0bf9c | bellard | void op_srlv (void) |
465 | 6af0bf9c | bellard | { |
466 | 6af0bf9c | bellard | T0 = T1 >> (T0 & 0x1F);
|
467 | 6af0bf9c | bellard | RETURN(); |
468 | 6af0bf9c | bellard | } |
469 | 6af0bf9c | bellard | |
470 | 7a387fff | ths | void op_rotrv (void) |
471 | 7a387fff | ths | { |
472 | 7a387fff | ths | target_ulong tmp; |
473 | 7a387fff | ths | |
474 | 7a387fff | ths | T0 &= 0x1F;
|
475 | 7a387fff | ths | if (T0) {
|
476 | 7a387fff | ths | tmp = T1 << (0x20 - T0);
|
477 | 7a387fff | ths | T0 = (T1 >> T0) | tmp; |
478 | 7a387fff | ths | } else
|
479 | 7a387fff | ths | T0 = T1; |
480 | 7a387fff | ths | RETURN(); |
481 | 7a387fff | ths | } |
482 | 7a387fff | ths | |
483 | 6af0bf9c | bellard | void op_clo (void) |
484 | 6af0bf9c | bellard | { |
485 | 6af0bf9c | bellard | int n;
|
486 | 6af0bf9c | bellard | |
487 | 6af0bf9c | bellard | if (T0 == (target_ulong)-1) { |
488 | 6af0bf9c | bellard | T0 = 32;
|
489 | 6af0bf9c | bellard | } else {
|
490 | 6af0bf9c | bellard | for (n = 0; n < 32; n++) { |
491 | 6af0bf9c | bellard | if (!(T0 & (1 << 31))) |
492 | 6af0bf9c | bellard | break;
|
493 | 6af0bf9c | bellard | T0 = T0 << 1;
|
494 | 6af0bf9c | bellard | } |
495 | 6af0bf9c | bellard | T0 = n; |
496 | 6af0bf9c | bellard | } |
497 | 6af0bf9c | bellard | RETURN(); |
498 | 6af0bf9c | bellard | } |
499 | 6af0bf9c | bellard | |
500 | 6af0bf9c | bellard | void op_clz (void) |
501 | 6af0bf9c | bellard | { |
502 | 6af0bf9c | bellard | int n;
|
503 | 6af0bf9c | bellard | |
504 | 6af0bf9c | bellard | if (T0 == 0) { |
505 | 6af0bf9c | bellard | T0 = 32;
|
506 | 6af0bf9c | bellard | } else {
|
507 | 6af0bf9c | bellard | for (n = 0; n < 32; n++) { |
508 | 6af0bf9c | bellard | if (T0 & (1 << 31)) |
509 | 6af0bf9c | bellard | break;
|
510 | 6af0bf9c | bellard | T0 = T0 << 1;
|
511 | 6af0bf9c | bellard | } |
512 | 6af0bf9c | bellard | T0 = n; |
513 | 6af0bf9c | bellard | } |
514 | 6af0bf9c | bellard | RETURN(); |
515 | 6af0bf9c | bellard | } |
516 | 6af0bf9c | bellard | |
517 | 6af0bf9c | bellard | /* 64 bits arithmetic */
|
518 | 6af0bf9c | bellard | #if (HOST_LONG_BITS == 64) |
519 | 6af0bf9c | bellard | static inline uint64_t get_HILO (void) |
520 | 6af0bf9c | bellard | { |
521 | 6af0bf9c | bellard | return ((uint64_t)env->HI << 32) | (uint64_t)env->LO; |
522 | 6af0bf9c | bellard | } |
523 | 6af0bf9c | bellard | |
524 | 6af0bf9c | bellard | static inline void set_HILO (uint64_t HILO) |
525 | 6af0bf9c | bellard | { |
526 | 6af0bf9c | bellard | env->LO = HILO & 0xFFFFFFFF;
|
527 | 6af0bf9c | bellard | env->HI = HILO >> 32;
|
528 | 6af0bf9c | bellard | } |
529 | 6af0bf9c | bellard | |
530 | 6af0bf9c | bellard | void op_mult (void) |
531 | 6af0bf9c | bellard | { |
532 | 4ad40f36 | bellard | set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
533 | 6af0bf9c | bellard | RETURN(); |
534 | 6af0bf9c | bellard | } |
535 | 6af0bf9c | bellard | |
536 | 6af0bf9c | bellard | void op_multu (void) |
537 | 6af0bf9c | bellard | { |
538 | 6af0bf9c | bellard | set_HILO((uint64_t)T0 * (uint64_t)T1); |
539 | 6af0bf9c | bellard | RETURN(); |
540 | 6af0bf9c | bellard | } |
541 | 6af0bf9c | bellard | |
542 | 6af0bf9c | bellard | void op_madd (void) |
543 | 6af0bf9c | bellard | { |
544 | 6af0bf9c | bellard | int64_t tmp; |
545 | 6af0bf9c | bellard | |
546 | 4ad40f36 | bellard | tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
547 | 6af0bf9c | bellard | set_HILO((int64_t)get_HILO() + tmp); |
548 | 6af0bf9c | bellard | RETURN(); |
549 | 6af0bf9c | bellard | } |
550 | 6af0bf9c | bellard | |
551 | 6af0bf9c | bellard | void op_maddu (void) |
552 | 6af0bf9c | bellard | { |
553 | 6af0bf9c | bellard | uint64_t tmp; |
554 | 6af0bf9c | bellard | |
555 | 6af0bf9c | bellard | tmp = ((uint64_t)T0 * (uint64_t)T1); |
556 | 6af0bf9c | bellard | set_HILO(get_HILO() + tmp); |
557 | 6af0bf9c | bellard | RETURN(); |
558 | 6af0bf9c | bellard | } |
559 | 6af0bf9c | bellard | |
560 | 6af0bf9c | bellard | void op_msub (void) |
561 | 6af0bf9c | bellard | { |
562 | 6af0bf9c | bellard | int64_t tmp; |
563 | 6af0bf9c | bellard | |
564 | 4ad40f36 | bellard | tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
565 | 6af0bf9c | bellard | set_HILO((int64_t)get_HILO() - tmp); |
566 | 6af0bf9c | bellard | RETURN(); |
567 | 6af0bf9c | bellard | } |
568 | 6af0bf9c | bellard | |
569 | 6af0bf9c | bellard | void op_msubu (void) |
570 | 6af0bf9c | bellard | { |
571 | 6af0bf9c | bellard | uint64_t tmp; |
572 | 6af0bf9c | bellard | |
573 | 6af0bf9c | bellard | tmp = ((uint64_t)T0 * (uint64_t)T1); |
574 | 6af0bf9c | bellard | set_HILO(get_HILO() - tmp); |
575 | 6af0bf9c | bellard | RETURN(); |
576 | 6af0bf9c | bellard | } |
577 | 6af0bf9c | bellard | #else
|
578 | 6af0bf9c | bellard | void op_mult (void) |
579 | 6af0bf9c | bellard | { |
580 | 6af0bf9c | bellard | CALL_FROM_TB0(do_mult); |
581 | 6af0bf9c | bellard | RETURN(); |
582 | 6af0bf9c | bellard | } |
583 | 6af0bf9c | bellard | |
584 | 6af0bf9c | bellard | void op_multu (void) |
585 | 6af0bf9c | bellard | { |
586 | 6af0bf9c | bellard | CALL_FROM_TB0(do_multu); |
587 | 6af0bf9c | bellard | RETURN(); |
588 | 6af0bf9c | bellard | } |
589 | 6af0bf9c | bellard | |
590 | 6af0bf9c | bellard | void op_madd (void) |
591 | 6af0bf9c | bellard | { |
592 | 6af0bf9c | bellard | CALL_FROM_TB0(do_madd); |
593 | 6af0bf9c | bellard | RETURN(); |
594 | 6af0bf9c | bellard | } |
595 | 6af0bf9c | bellard | |
596 | 6af0bf9c | bellard | void op_maddu (void) |
597 | 6af0bf9c | bellard | { |
598 | 6af0bf9c | bellard | CALL_FROM_TB0(do_maddu); |
599 | 6af0bf9c | bellard | RETURN(); |
600 | 6af0bf9c | bellard | } |
601 | 6af0bf9c | bellard | |
602 | 6af0bf9c | bellard | void op_msub (void) |
603 | 6af0bf9c | bellard | { |
604 | 6af0bf9c | bellard | CALL_FROM_TB0(do_msub); |
605 | 6af0bf9c | bellard | RETURN(); |
606 | 6af0bf9c | bellard | } |
607 | 6af0bf9c | bellard | |
608 | 6af0bf9c | bellard | void op_msubu (void) |
609 | 6af0bf9c | bellard | { |
610 | 6af0bf9c | bellard | CALL_FROM_TB0(do_msubu); |
611 | 6af0bf9c | bellard | RETURN(); |
612 | 6af0bf9c | bellard | } |
613 | 6af0bf9c | bellard | #endif
|
614 | 6af0bf9c | bellard | |
615 | 6af0bf9c | bellard | /* Conditional moves */
|
616 | 6af0bf9c | bellard | void op_movn (void) |
617 | 6af0bf9c | bellard | { |
618 | 6af0bf9c | bellard | if (T1 != 0) |
619 | 6af0bf9c | bellard | env->gpr[PARAM1] = T0; |
620 | 6af0bf9c | bellard | RETURN(); |
621 | 6af0bf9c | bellard | } |
622 | 6af0bf9c | bellard | |
623 | 6af0bf9c | bellard | void op_movz (void) |
624 | 6af0bf9c | bellard | { |
625 | 6af0bf9c | bellard | if (T1 == 0) |
626 | 6af0bf9c | bellard | env->gpr[PARAM1] = T0; |
627 | 6af0bf9c | bellard | RETURN(); |
628 | 6af0bf9c | bellard | } |
629 | 6af0bf9c | bellard | |
630 | 7a387fff | ths | void op_movf (void) |
631 | 7a387fff | ths | { |
632 | 7a387fff | ths | if (!(env->fcr31 & PARAM1))
|
633 | 7a387fff | ths | env->gpr[PARAM2] = env->gpr[PARAM3]; |
634 | 7a387fff | ths | RETURN(); |
635 | 7a387fff | ths | } |
636 | 7a387fff | ths | |
637 | 7a387fff | ths | void op_movt (void) |
638 | 7a387fff | ths | { |
639 | 7a387fff | ths | if (env->fcr31 & PARAM1)
|
640 | 7a387fff | ths | env->gpr[PARAM2] = env->gpr[PARAM3]; |
641 | 7a387fff | ths | RETURN(); |
642 | 7a387fff | ths | } |
643 | 7a387fff | ths | |
644 | 6af0bf9c | bellard | /* Tests */
|
645 | 6af0bf9c | bellard | #define OP_COND(name, cond) \
|
646 | 6af0bf9c | bellard | void glue(op_, name) (void) \ |
647 | 6af0bf9c | bellard | { \ |
648 | 6af0bf9c | bellard | if (cond) { \
|
649 | 6af0bf9c | bellard | T0 = 1; \
|
650 | 6af0bf9c | bellard | } else { \
|
651 | 6af0bf9c | bellard | T0 = 0; \
|
652 | 6af0bf9c | bellard | } \ |
653 | 6af0bf9c | bellard | RETURN(); \ |
654 | 6af0bf9c | bellard | } |
655 | 6af0bf9c | bellard | |
656 | 6af0bf9c | bellard | OP_COND(eq, T0 == T1); |
657 | 6af0bf9c | bellard | OP_COND(ne, T0 != T1); |
658 | 6af0bf9c | bellard | OP_COND(ge, (int32_t)T0 >= (int32_t)T1); |
659 | 6af0bf9c | bellard | OP_COND(geu, T0 >= T1); |
660 | 6af0bf9c | bellard | OP_COND(lt, (int32_t)T0 < (int32_t)T1); |
661 | 6af0bf9c | bellard | OP_COND(ltu, T0 < T1); |
662 | 6af0bf9c | bellard | OP_COND(gez, (int32_t)T0 >= 0);
|
663 | 6af0bf9c | bellard | OP_COND(gtz, (int32_t)T0 > 0);
|
664 | 6af0bf9c | bellard | OP_COND(lez, (int32_t)T0 <= 0);
|
665 | 6af0bf9c | bellard | OP_COND(ltz, (int32_t)T0 < 0);
|
666 | 6af0bf9c | bellard | |
667 | 7a387fff | ths | /* Branches */
|
668 | 6af0bf9c | bellard | //#undef USE_DIRECT_JUMP
|
669 | c53be334 | bellard | |
670 | c53be334 | bellard | void OPPROTO op_goto_tb0(void) |
671 | c53be334 | bellard | { |
672 | c53be334 | bellard | GOTO_TB(op_goto_tb0, PARAM1, 0);
|
673 | 7a387fff | ths | RETURN(); |
674 | c53be334 | bellard | } |
675 | c53be334 | bellard | |
676 | c53be334 | bellard | void OPPROTO op_goto_tb1(void) |
677 | c53be334 | bellard | { |
678 | c53be334 | bellard | GOTO_TB(op_goto_tb1, PARAM1, 1);
|
679 | 7a387fff | ths | RETURN(); |
680 | c53be334 | bellard | } |
681 | 6af0bf9c | bellard | |
682 | 6af0bf9c | bellard | /* Branch to register */
|
683 | 6af0bf9c | bellard | void op_save_breg_target (void) |
684 | 6af0bf9c | bellard | { |
685 | 6af0bf9c | bellard | env->btarget = T2; |
686 | 7a387fff | ths | RETURN(); |
687 | 6af0bf9c | bellard | } |
688 | 6af0bf9c | bellard | |
689 | 6af0bf9c | bellard | void op_restore_breg_target (void) |
690 | 6af0bf9c | bellard | { |
691 | 6af0bf9c | bellard | T2 = env->btarget; |
692 | 7a387fff | ths | RETURN(); |
693 | 6af0bf9c | bellard | } |
694 | 6af0bf9c | bellard | |
695 | 6af0bf9c | bellard | void op_breg (void) |
696 | 6af0bf9c | bellard | { |
697 | 6af0bf9c | bellard | env->PC = T2; |
698 | 6af0bf9c | bellard | RETURN(); |
699 | 6af0bf9c | bellard | } |
700 | 6af0bf9c | bellard | |
701 | 6af0bf9c | bellard | void op_save_btarget (void) |
702 | 6af0bf9c | bellard | { |
703 | 6af0bf9c | bellard | env->btarget = PARAM1; |
704 | 6af0bf9c | bellard | RETURN(); |
705 | 6af0bf9c | bellard | } |
706 | 6af0bf9c | bellard | |
707 | 6af0bf9c | bellard | /* Conditional branch */
|
708 | 6af0bf9c | bellard | void op_set_bcond (void) |
709 | 6af0bf9c | bellard | { |
710 | 6af0bf9c | bellard | T2 = T0; |
711 | 6af0bf9c | bellard | RETURN(); |
712 | 6af0bf9c | bellard | } |
713 | 6af0bf9c | bellard | |
714 | 6af0bf9c | bellard | void op_save_bcond (void) |
715 | 6af0bf9c | bellard | { |
716 | 6af0bf9c | bellard | env->bcond = T2; |
717 | 6af0bf9c | bellard | RETURN(); |
718 | 6af0bf9c | bellard | } |
719 | 6af0bf9c | bellard | |
720 | 6af0bf9c | bellard | void op_restore_bcond (void) |
721 | 6af0bf9c | bellard | { |
722 | 6af0bf9c | bellard | T2 = env->bcond; |
723 | 6af0bf9c | bellard | RETURN(); |
724 | 6af0bf9c | bellard | } |
725 | 6af0bf9c | bellard | |
726 | c53be334 | bellard | void op_jnz_T2 (void) |
727 | 6af0bf9c | bellard | { |
728 | c53be334 | bellard | if (T2)
|
729 | c53be334 | bellard | GOTO_LABEL_PARAM(1);
|
730 | 6af0bf9c | bellard | RETURN(); |
731 | 6af0bf9c | bellard | } |
732 | 6af0bf9c | bellard | |
733 | 6af0bf9c | bellard | /* CP0 functions */
|
734 | 873eb012 | ths | void op_mfc0_index (void) |
735 | 6af0bf9c | bellard | { |
736 | 873eb012 | ths | T0 = env->CP0_index; |
737 | 873eb012 | ths | RETURN(); |
738 | 873eb012 | ths | } |
739 | 873eb012 | ths | |
740 | 873eb012 | ths | void op_mfc0_random (void) |
741 | 873eb012 | ths | { |
742 | 873eb012 | ths | CALL_FROM_TB0(do_mfc0_random); |
743 | 873eb012 | ths | RETURN(); |
744 | 873eb012 | ths | } |
745 | 873eb012 | ths | |
746 | 873eb012 | ths | void op_mfc0_entrylo0 (void) |
747 | 873eb012 | ths | { |
748 | 873eb012 | ths | T0 = env->CP0_EntryLo0; |
749 | 873eb012 | ths | RETURN(); |
750 | 873eb012 | ths | } |
751 | 873eb012 | ths | |
752 | 873eb012 | ths | void op_mfc0_entrylo1 (void) |
753 | 873eb012 | ths | { |
754 | 873eb012 | ths | T0 = env->CP0_EntryLo1; |
755 | 873eb012 | ths | RETURN(); |
756 | 873eb012 | ths | } |
757 | 873eb012 | ths | |
758 | 873eb012 | ths | void op_mfc0_context (void) |
759 | 873eb012 | ths | { |
760 | 873eb012 | ths | T0 = env->CP0_Context; |
761 | 873eb012 | ths | RETURN(); |
762 | 873eb012 | ths | } |
763 | 873eb012 | ths | |
764 | 873eb012 | ths | void op_mfc0_pagemask (void) |
765 | 873eb012 | ths | { |
766 | 873eb012 | ths | T0 = env->CP0_PageMask; |
767 | 873eb012 | ths | RETURN(); |
768 | 873eb012 | ths | } |
769 | 873eb012 | ths | |
770 | 7a387fff | ths | void op_mfc0_pagegrain (void) |
771 | 7a387fff | ths | { |
772 | 7a387fff | ths | T0 = env->CP0_PageGrain; |
773 | 7a387fff | ths | RETURN(); |
774 | 7a387fff | ths | } |
775 | 7a387fff | ths | |
776 | 873eb012 | ths | void op_mfc0_wired (void) |
777 | 873eb012 | ths | { |
778 | 873eb012 | ths | T0 = env->CP0_Wired; |
779 | 873eb012 | ths | RETURN(); |
780 | 873eb012 | ths | } |
781 | 873eb012 | ths | |
782 | 7a387fff | ths | void op_mfc0_hwrena (void) |
783 | 7a387fff | ths | { |
784 | 7a387fff | ths | T0 = env->CP0_HWREna; |
785 | 7a387fff | ths | RETURN(); |
786 | 7a387fff | ths | } |
787 | 7a387fff | ths | |
788 | 873eb012 | ths | void op_mfc0_badvaddr (void) |
789 | 873eb012 | ths | { |
790 | 873eb012 | ths | T0 = env->CP0_BadVAddr; |
791 | 873eb012 | ths | RETURN(); |
792 | 873eb012 | ths | } |
793 | 873eb012 | ths | |
794 | 873eb012 | ths | void op_mfc0_count (void) |
795 | 873eb012 | ths | { |
796 | 873eb012 | ths | CALL_FROM_TB0(do_mfc0_count); |
797 | 873eb012 | ths | RETURN(); |
798 | 873eb012 | ths | } |
799 | 873eb012 | ths | |
800 | 873eb012 | ths | void op_mfc0_entryhi (void) |
801 | 873eb012 | ths | { |
802 | 873eb012 | ths | T0 = env->CP0_EntryHi; |
803 | 873eb012 | ths | RETURN(); |
804 | 873eb012 | ths | } |
805 | 873eb012 | ths | |
806 | 873eb012 | ths | void op_mfc0_compare (void) |
807 | 873eb012 | ths | { |
808 | 873eb012 | ths | T0 = env->CP0_Compare; |
809 | 873eb012 | ths | RETURN(); |
810 | 873eb012 | ths | } |
811 | 873eb012 | ths | |
812 | 873eb012 | ths | void op_mfc0_status (void) |
813 | 873eb012 | ths | { |
814 | 873eb012 | ths | T0 = env->CP0_Status; |
815 | 873eb012 | ths | if (env->hflags & MIPS_HFLAG_UM)
|
816 | 873eb012 | ths | T0 |= (1 << CP0St_UM);
|
817 | 873eb012 | ths | if (env->hflags & MIPS_HFLAG_ERL)
|
818 | 873eb012 | ths | T0 |= (1 << CP0St_ERL);
|
819 | 873eb012 | ths | if (env->hflags & MIPS_HFLAG_EXL)
|
820 | 873eb012 | ths | T0 |= (1 << CP0St_EXL);
|
821 | 873eb012 | ths | RETURN(); |
822 | 873eb012 | ths | } |
823 | 873eb012 | ths | |
824 | 7a387fff | ths | void op_mfc0_intctl (void) |
825 | 7a387fff | ths | { |
826 | 7a387fff | ths | T0 = env->CP0_IntCtl; |
827 | 7a387fff | ths | RETURN(); |
828 | 7a387fff | ths | } |
829 | 7a387fff | ths | |
830 | 7a387fff | ths | void op_mfc0_srsctl (void) |
831 | 7a387fff | ths | { |
832 | 7a387fff | ths | T0 = env->CP0_SRSCtl; |
833 | 7a387fff | ths | RETURN(); |
834 | 7a387fff | ths | } |
835 | 7a387fff | ths | |
836 | 873eb012 | ths | void op_mfc0_cause (void) |
837 | 873eb012 | ths | { |
838 | 873eb012 | ths | T0 = env->CP0_Cause; |
839 | 873eb012 | ths | RETURN(); |
840 | 873eb012 | ths | } |
841 | 873eb012 | ths | |
842 | 873eb012 | ths | void op_mfc0_epc (void) |
843 | 873eb012 | ths | { |
844 | 873eb012 | ths | T0 = env->CP0_EPC; |
845 | 873eb012 | ths | RETURN(); |
846 | 873eb012 | ths | } |
847 | 873eb012 | ths | |
848 | 873eb012 | ths | void op_mfc0_prid (void) |
849 | 873eb012 | ths | { |
850 | 873eb012 | ths | T0 = env->CP0_PRid; |
851 | 873eb012 | ths | RETURN(); |
852 | 873eb012 | ths | } |
853 | 873eb012 | ths | |
854 | 7a387fff | ths | void op_mfc0_ebase (void) |
855 | 7a387fff | ths | { |
856 | 7a387fff | ths | T0 = env->CP0_EBase; |
857 | 7a387fff | ths | RETURN(); |
858 | 7a387fff | ths | } |
859 | 7a387fff | ths | |
860 | 873eb012 | ths | void op_mfc0_config0 (void) |
861 | 873eb012 | ths | { |
862 | 873eb012 | ths | T0 = env->CP0_Config0; |
863 | 873eb012 | ths | RETURN(); |
864 | 873eb012 | ths | } |
865 | 873eb012 | ths | |
866 | 873eb012 | ths | void op_mfc0_config1 (void) |
867 | 873eb012 | ths | { |
868 | 873eb012 | ths | T0 = env->CP0_Config1; |
869 | 873eb012 | ths | RETURN(); |
870 | 873eb012 | ths | } |
871 | 873eb012 | ths | |
872 | 7a387fff | ths | void op_mfc0_config2 (void) |
873 | 7a387fff | ths | { |
874 | 7a387fff | ths | T0 = env->CP0_Config2; |
875 | 7a387fff | ths | RETURN(); |
876 | 7a387fff | ths | } |
877 | 7a387fff | ths | |
878 | 7a387fff | ths | void op_mfc0_config3 (void) |
879 | 7a387fff | ths | { |
880 | 7a387fff | ths | T0 = env->CP0_Config3; |
881 | 7a387fff | ths | RETURN(); |
882 | 7a387fff | ths | } |
883 | 7a387fff | ths | |
884 | 873eb012 | ths | void op_mfc0_lladdr (void) |
885 | 873eb012 | ths | { |
886 | 873eb012 | ths | T0 = env->CP0_LLAddr >> 4;
|
887 | 873eb012 | ths | RETURN(); |
888 | 873eb012 | ths | } |
889 | 873eb012 | ths | |
890 | 7a387fff | ths | void op_mfc0_watchlo0 (void) |
891 | 873eb012 | ths | { |
892 | 873eb012 | ths | T0 = env->CP0_WatchLo; |
893 | 873eb012 | ths | RETURN(); |
894 | 873eb012 | ths | } |
895 | 873eb012 | ths | |
896 | 7a387fff | ths | void op_mfc0_watchhi0 (void) |
897 | 873eb012 | ths | { |
898 | 873eb012 | ths | T0 = env->CP0_WatchHi; |
899 | 873eb012 | ths | RETURN(); |
900 | 873eb012 | ths | } |
901 | 873eb012 | ths | |
902 | 7a387fff | ths | void op_mfc0_xcontext (void) |
903 | 7a387fff | ths | { |
904 | 7a387fff | ths | T0 = env->CP0_XContext; |
905 | 7a387fff | ths | RETURN(); |
906 | 7a387fff | ths | } |
907 | 7a387fff | ths | |
908 | 7a387fff | ths | void op_mfc0_framemask (void) |
909 | 7a387fff | ths | { |
910 | 7a387fff | ths | T0 = env->CP0_Framemask; |
911 | 7a387fff | ths | RETURN(); |
912 | 7a387fff | ths | } |
913 | 7a387fff | ths | |
914 | 873eb012 | ths | void op_mfc0_debug (void) |
915 | 873eb012 | ths | { |
916 | 873eb012 | ths | T0 = env->CP0_Debug; |
917 | 873eb012 | ths | if (env->hflags & MIPS_HFLAG_DM)
|
918 | 873eb012 | ths | T0 |= 1 << CP0DB_DM;
|
919 | 873eb012 | ths | RETURN(); |
920 | 873eb012 | ths | } |
921 | 873eb012 | ths | |
922 | 873eb012 | ths | void op_mfc0_depc (void) |
923 | 873eb012 | ths | { |
924 | 873eb012 | ths | T0 = env->CP0_DEPC; |
925 | 873eb012 | ths | RETURN(); |
926 | 873eb012 | ths | } |
927 | 873eb012 | ths | |
928 | 7a387fff | ths | void op_mfc0_performance0 (void) |
929 | 7a387fff | ths | { |
930 | 7a387fff | ths | T0 = env->CP0_Performance0; |
931 | 7a387fff | ths | RETURN(); |
932 | 7a387fff | ths | } |
933 | 7a387fff | ths | |
934 | 873eb012 | ths | void op_mfc0_taglo (void) |
935 | 873eb012 | ths | { |
936 | 873eb012 | ths | T0 = env->CP0_TagLo; |
937 | 873eb012 | ths | RETURN(); |
938 | 873eb012 | ths | } |
939 | 873eb012 | ths | |
940 | 873eb012 | ths | void op_mfc0_datalo (void) |
941 | 873eb012 | ths | { |
942 | 873eb012 | ths | T0 = env->CP0_DataLo; |
943 | 873eb012 | ths | RETURN(); |
944 | 873eb012 | ths | } |
945 | 873eb012 | ths | |
946 | 7a387fff | ths | void op_mfc0_taghi (void) |
947 | 7a387fff | ths | { |
948 | 7a387fff | ths | T0 = env->CP0_TagHi; |
949 | 7a387fff | ths | RETURN(); |
950 | 7a387fff | ths | } |
951 | 7a387fff | ths | |
952 | 7a387fff | ths | void op_mfc0_datahi (void) |
953 | 7a387fff | ths | { |
954 | 7a387fff | ths | T0 = env->CP0_DataHi; |
955 | 7a387fff | ths | RETURN(); |
956 | 7a387fff | ths | } |
957 | 7a387fff | ths | |
958 | 873eb012 | ths | void op_mfc0_errorepc (void) |
959 | 873eb012 | ths | { |
960 | 873eb012 | ths | T0 = env->CP0_ErrorEPC; |
961 | 873eb012 | ths | RETURN(); |
962 | 873eb012 | ths | } |
963 | 873eb012 | ths | |
964 | 873eb012 | ths | void op_mfc0_desave (void) |
965 | 873eb012 | ths | { |
966 | 873eb012 | ths | T0 = env->CP0_DESAVE; |
967 | 6af0bf9c | bellard | RETURN(); |
968 | 6af0bf9c | bellard | } |
969 | 6af0bf9c | bellard | |
970 | 8c0fdd85 | ths | void op_mtc0_index (void) |
971 | 6af0bf9c | bellard | { |
972 | 7a387fff | ths | env->CP0_index = (env->CP0_index & 0x80000000) | (T0 & (MIPS_TLB_NB - 1)); |
973 | 8c0fdd85 | ths | RETURN(); |
974 | 8c0fdd85 | ths | } |
975 | 8c0fdd85 | ths | |
976 | 8c0fdd85 | ths | void op_mtc0_entrylo0 (void) |
977 | 8c0fdd85 | ths | { |
978 | 7a387fff | ths | /* Large physaddr not implemented */
|
979 | 7a387fff | ths | /* 1k pages not implemented */
|
980 | 7a387fff | ths | env->CP0_EntryLo0 = T0 & 0x3FFFFFFFUL;
|
981 | 8c0fdd85 | ths | RETURN(); |
982 | 8c0fdd85 | ths | } |
983 | 8c0fdd85 | ths | |
984 | 8c0fdd85 | ths | void op_mtc0_entrylo1 (void) |
985 | 8c0fdd85 | ths | { |
986 | 7a387fff | ths | /* Large physaddr not implemented */
|
987 | 7a387fff | ths | /* 1k pages not implemented */
|
988 | 7a387fff | ths | env->CP0_EntryLo1 = T0 & 0x3FFFFFFFUL;
|
989 | 8c0fdd85 | ths | RETURN(); |
990 | 8c0fdd85 | ths | } |
991 | 8c0fdd85 | ths | |
992 | 8c0fdd85 | ths | void op_mtc0_context (void) |
993 | 8c0fdd85 | ths | { |
994 | 7a387fff | ths | env->CP0_Context = (env->CP0_Context & ~0x007FFFFF) | (T0 & 0x007FFFF0); |
995 | 8c0fdd85 | ths | RETURN(); |
996 | 8c0fdd85 | ths | } |
997 | 8c0fdd85 | ths | |
998 | 8c0fdd85 | ths | void op_mtc0_pagemask (void) |
999 | 8c0fdd85 | ths | { |
1000 | 7a387fff | ths | /* 1k pages not implemented */
|
1001 | 7a387fff | ths | env->CP0_PageMask = T0 & 0x1FFFE000;
|
1002 | 7a387fff | ths | RETURN(); |
1003 | 7a387fff | ths | } |
1004 | 7a387fff | ths | |
1005 | 7a387fff | ths | void op_mtc0_pagegrain (void) |
1006 | 7a387fff | ths | { |
1007 | 7a387fff | ths | /* SmartMIPS not implemented */
|
1008 | 7a387fff | ths | /* Large physaddr not implemented */
|
1009 | 7a387fff | ths | /* 1k pages not implemented */
|
1010 | 7a387fff | ths | env->CP0_PageGrain = 0;
|
1011 | 8c0fdd85 | ths | RETURN(); |
1012 | 8c0fdd85 | ths | } |
1013 | 8c0fdd85 | ths | |
1014 | 8c0fdd85 | ths | void op_mtc0_wired (void) |
1015 | 8c0fdd85 | ths | { |
1016 | 7a387fff | ths | env->CP0_Wired = T0 & (MIPS_TLB_NB - 1);
|
1017 | 7a387fff | ths | RETURN(); |
1018 | 7a387fff | ths | } |
1019 | 7a387fff | ths | |
1020 | 7a387fff | ths | void op_mtc0_hwrena (void) |
1021 | 7a387fff | ths | { |
1022 | 7a387fff | ths | env->CP0_HWREna = T0 & 0x0000000F;
|
1023 | 8c0fdd85 | ths | RETURN(); |
1024 | 8c0fdd85 | ths | } |
1025 | 8c0fdd85 | ths | |
1026 | 8c0fdd85 | ths | void op_mtc0_count (void) |
1027 | 8c0fdd85 | ths | { |
1028 | 8c0fdd85 | ths | CALL_FROM_TB2(cpu_mips_store_count, env, T0); |
1029 | 8c0fdd85 | ths | RETURN(); |
1030 | 8c0fdd85 | ths | } |
1031 | 8c0fdd85 | ths | |
1032 | 8c0fdd85 | ths | void op_mtc0_entryhi (void) |
1033 | 8c0fdd85 | ths | { |
1034 | 8c0fdd85 | ths | uint32_t old, val; |
1035 | 8c0fdd85 | ths | |
1036 | 7a387fff | ths | /* 1k pages not implemented */
|
1037 | 7a387fff | ths | /* Ignore MIPS64 TLB for now */
|
1038 | 8c0fdd85 | ths | val = T0 & 0xFFFFE0FF;
|
1039 | 8c0fdd85 | ths | old = env->CP0_EntryHi; |
1040 | 8c0fdd85 | ths | env->CP0_EntryHi = val; |
1041 | 8c0fdd85 | ths | /* If the ASID changes, flush qemu's TLB. */
|
1042 | 8c0fdd85 | ths | if ((old & 0xFF) != (val & 0xFF)) |
1043 | 8c0fdd85 | ths | CALL_FROM_TB2(cpu_mips_tlb_flush, env, 1);
|
1044 | 8c0fdd85 | ths | RETURN(); |
1045 | 8c0fdd85 | ths | } |
1046 | 8c0fdd85 | ths | |
1047 | 8c0fdd85 | ths | void op_mtc0_compare (void) |
1048 | 8c0fdd85 | ths | { |
1049 | 8c0fdd85 | ths | CALL_FROM_TB2(cpu_mips_store_compare, env, T0); |
1050 | 8c0fdd85 | ths | RETURN(); |
1051 | 8c0fdd85 | ths | } |
1052 | 8c0fdd85 | ths | |
1053 | 8c0fdd85 | ths | void op_mtc0_status (void) |
1054 | 8c0fdd85 | ths | { |
1055 | 8c0fdd85 | ths | uint32_t val, old, mask; |
1056 | 8c0fdd85 | ths | |
1057 | 8c0fdd85 | ths | val = T0 & 0xFA78FF01;
|
1058 | 8c0fdd85 | ths | old = env->CP0_Status; |
1059 | 8c0fdd85 | ths | if (T0 & (1 << CP0St_UM)) |
1060 | 8c0fdd85 | ths | env->hflags |= MIPS_HFLAG_UM; |
1061 | 8c0fdd85 | ths | else
|
1062 | 8c0fdd85 | ths | env->hflags &= ~MIPS_HFLAG_UM; |
1063 | 8c0fdd85 | ths | if (T0 & (1 << CP0St_ERL)) |
1064 | 8c0fdd85 | ths | env->hflags |= MIPS_HFLAG_ERL; |
1065 | 8c0fdd85 | ths | else
|
1066 | 8c0fdd85 | ths | env->hflags &= ~MIPS_HFLAG_ERL; |
1067 | 8c0fdd85 | ths | if (T0 & (1 << CP0St_EXL)) |
1068 | 8c0fdd85 | ths | env->hflags |= MIPS_HFLAG_EXL; |
1069 | 8c0fdd85 | ths | else
|
1070 | 8c0fdd85 | ths | env->hflags &= ~MIPS_HFLAG_EXL; |
1071 | 8c0fdd85 | ths | env->CP0_Status = val; |
1072 | 8c0fdd85 | ths | /* If we unmasked an asserted IRQ, raise it */
|
1073 | 8c0fdd85 | ths | mask = 0x0000FF00;
|
1074 | 8c0fdd85 | ths | if (loglevel & CPU_LOG_TB_IN_ASM)
|
1075 | 8c0fdd85 | ths | CALL_FROM_TB2(do_mtc0_status_debug, old, val); |
1076 | 8c0fdd85 | ths | if ((val & (1 << CP0St_IE)) && !(old & (1 << CP0St_IE)) && |
1077 | 8c0fdd85 | ths | !(env->hflags & MIPS_HFLAG_EXL) && |
1078 | 8c0fdd85 | ths | !(env->hflags & MIPS_HFLAG_ERL) && |
1079 | 8c0fdd85 | ths | !(env->hflags & MIPS_HFLAG_DM) && |
1080 | 8c0fdd85 | ths | (env->CP0_Status & env->CP0_Cause & mask)) { |
1081 | 8c0fdd85 | ths | env->interrupt_request |= CPU_INTERRUPT_HARD; |
1082 | 8c0fdd85 | ths | if (logfile)
|
1083 | 8c0fdd85 | ths | CALL_FROM_TB0(do_mtc0_status_irqraise_debug); |
1084 | 8c0fdd85 | ths | } else if (!(val & (1 << CP0St_IE)) && (old & (1 << CP0St_IE))) { |
1085 | 8c0fdd85 | ths | env->interrupt_request &= ~CPU_INTERRUPT_HARD; |
1086 | 8c0fdd85 | ths | } |
1087 | 8c0fdd85 | ths | RETURN(); |
1088 | 8c0fdd85 | ths | } |
1089 | 8c0fdd85 | ths | |
1090 | 7a387fff | ths | void op_mtc0_intctl (void) |
1091 | 7a387fff | ths | { |
1092 | 7a387fff | ths | /* vectored interrupts not implemented */
|
1093 | 7a387fff | ths | env->CP0_IntCtl = 0;
|
1094 | 7a387fff | ths | RETURN(); |
1095 | 7a387fff | ths | } |
1096 | 7a387fff | ths | |
1097 | 7a387fff | ths | void op_mtc0_srsctl (void) |
1098 | 7a387fff | ths | { |
1099 | 7a387fff | ths | /* shadow registers not implemented */
|
1100 | 7a387fff | ths | env->CP0_SRSCtl = 0;
|
1101 | 7a387fff | ths | RETURN(); |
1102 | 7a387fff | ths | } |
1103 | 7a387fff | ths | |
1104 | 8c0fdd85 | ths | void op_mtc0_cause (void) |
1105 | 8c0fdd85 | ths | { |
1106 | 8c0fdd85 | ths | uint32_t val, old; |
1107 | 8c0fdd85 | ths | |
1108 | 8c0fdd85 | ths | val = (env->CP0_Cause & 0xB000F87C) | (T0 & 0x000C00300); |
1109 | 8c0fdd85 | ths | old = env->CP0_Cause; |
1110 | 8c0fdd85 | ths | env->CP0_Cause = val; |
1111 | 8c0fdd85 | ths | #if 0
|
1112 | 8c0fdd85 | ths | {
|
1113 | 8c0fdd85 | ths | int i, mask;
|
1114 | 8c0fdd85 | ths | /* Check if we ever asserted a software IRQ */
|
1115 | 8c0fdd85 | ths | for (i = 0; i < 2; i++) {
|
1116 | 8c0fdd85 | ths | mask = 0x100 << i;
|
1117 | 8c0fdd85 | ths | if ((val & mask) & !(old & mask))
|
1118 | 8c0fdd85 | ths | CALL_FROM_TB1(mips_set_irq, i);
|
1119 | 8c0fdd85 | ths | }
|
1120 | 8c0fdd85 | ths | }
|
1121 | 8c0fdd85 | ths | #endif
|
1122 | 8c0fdd85 | ths | RETURN(); |
1123 | 8c0fdd85 | ths | } |
1124 | 8c0fdd85 | ths | |
1125 | 8c0fdd85 | ths | void op_mtc0_epc (void) |
1126 | 8c0fdd85 | ths | { |
1127 | 8c0fdd85 | ths | env->CP0_EPC = T0; |
1128 | 8c0fdd85 | ths | RETURN(); |
1129 | 8c0fdd85 | ths | } |
1130 | 8c0fdd85 | ths | |
1131 | 7a387fff | ths | void op_mtc0_ebase (void) |
1132 | 7a387fff | ths | { |
1133 | 7a387fff | ths | /* vectored interrupts not implemented */
|
1134 | 7a387fff | ths | /* Multi-CPU not implemented */
|
1135 | 7a387fff | ths | env->CP0_EBase = 0x80000000 | (T0 & 0x3FFFF000); |
1136 | 7a387fff | ths | RETURN(); |
1137 | 7a387fff | ths | } |
1138 | 7a387fff | ths | |
1139 | 8c0fdd85 | ths | void op_mtc0_config0 (void) |
1140 | 8c0fdd85 | ths | { |
1141 | 8c0fdd85 | ths | #if defined(MIPS_USES_R4K_TLB)
|
1142 | 7a387fff | ths | /* Fixed mapping MMU not implemented */
|
1143 | 7a387fff | ths | env->CP0_Config0 = (env->CP0_Config0 & 0x8017FF88) | (T0 & 0x00000001); |
1144 | 8c0fdd85 | ths | #else
|
1145 | 7a387fff | ths | env->CP0_Config0 = (env->CP0_Config0 & 0xFE17FF88) | (T0 & 0x00000001); |
1146 | 8c0fdd85 | ths | #endif
|
1147 | 8c0fdd85 | ths | RETURN(); |
1148 | 8c0fdd85 | ths | } |
1149 | 8c0fdd85 | ths | |
1150 | 7a387fff | ths | void op_mtc0_config2 (void) |
1151 | 7a387fff | ths | { |
1152 | 7a387fff | ths | /* tertiary/secondary caches not implemented */
|
1153 | 7a387fff | ths | env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
|
1154 | 7a387fff | ths | RETURN(); |
1155 | 7a387fff | ths | } |
1156 | 7a387fff | ths | |
1157 | 7a387fff | ths | void op_mtc0_watchlo0 (void) |
1158 | 8c0fdd85 | ths | { |
1159 | 8c0fdd85 | ths | env->CP0_WatchLo = T0; |
1160 | 8c0fdd85 | ths | RETURN(); |
1161 | 8c0fdd85 | ths | } |
1162 | 8c0fdd85 | ths | |
1163 | 7a387fff | ths | void op_mtc0_watchhi0 (void) |
1164 | 8c0fdd85 | ths | { |
1165 | 8c0fdd85 | ths | env->CP0_WatchHi = T0 & 0x40FF0FF8;
|
1166 | 8c0fdd85 | ths | RETURN(); |
1167 | 8c0fdd85 | ths | } |
1168 | 8c0fdd85 | ths | |
1169 | 7a387fff | ths | void op_mtc0_xcontext (void) |
1170 | 7a387fff | ths | { |
1171 | 7a387fff | ths | env->CP0_XContext = T0; /* XXX */
|
1172 | 7a387fff | ths | RETURN(); |
1173 | 7a387fff | ths | } |
1174 | 7a387fff | ths | |
1175 | 7a387fff | ths | void op_mtc0_framemask (void) |
1176 | 7a387fff | ths | { |
1177 | 7a387fff | ths | env->CP0_Framemask = T0; /* XXX */
|
1178 | 7a387fff | ths | RETURN(); |
1179 | 7a387fff | ths | } |
1180 | 7a387fff | ths | |
1181 | 8c0fdd85 | ths | void op_mtc0_debug (void) |
1182 | 8c0fdd85 | ths | { |
1183 | 8c0fdd85 | ths | env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (T0 & 0x13300120); |
1184 | 8c0fdd85 | ths | if (T0 & (1 << CP0DB_DM)) |
1185 | 8c0fdd85 | ths | env->hflags |= MIPS_HFLAG_DM; |
1186 | 8c0fdd85 | ths | else
|
1187 | 8c0fdd85 | ths | env->hflags &= ~MIPS_HFLAG_DM; |
1188 | 8c0fdd85 | ths | RETURN(); |
1189 | 8c0fdd85 | ths | } |
1190 | 8c0fdd85 | ths | |
1191 | 8c0fdd85 | ths | void op_mtc0_depc (void) |
1192 | 8c0fdd85 | ths | { |
1193 | 8c0fdd85 | ths | env->CP0_DEPC = T0; |
1194 | 8c0fdd85 | ths | RETURN(); |
1195 | 8c0fdd85 | ths | } |
1196 | 8c0fdd85 | ths | |
1197 | 7a387fff | ths | void op_mtc0_performance0 (void) |
1198 | 7a387fff | ths | { |
1199 | 7a387fff | ths | env->CP0_Performance0 = T0; /* XXX */
|
1200 | 7a387fff | ths | RETURN(); |
1201 | 7a387fff | ths | } |
1202 | 7a387fff | ths | |
1203 | 8c0fdd85 | ths | void op_mtc0_taglo (void) |
1204 | 8c0fdd85 | ths | { |
1205 | 8c0fdd85 | ths | env->CP0_TagLo = T0 & 0xFFFFFCF6;
|
1206 | 8c0fdd85 | ths | RETURN(); |
1207 | 8c0fdd85 | ths | } |
1208 | 8c0fdd85 | ths | |
1209 | 7a387fff | ths | void op_mtc0_datalo (void) |
1210 | 7a387fff | ths | { |
1211 | 7a387fff | ths | env->CP0_DataLo = T0; /* XXX */
|
1212 | 7a387fff | ths | RETURN(); |
1213 | 7a387fff | ths | } |
1214 | 7a387fff | ths | |
1215 | 7a387fff | ths | void op_mtc0_taghi (void) |
1216 | 7a387fff | ths | { |
1217 | 7a387fff | ths | env->CP0_TagHi = T0; /* XXX */
|
1218 | 7a387fff | ths | RETURN(); |
1219 | 7a387fff | ths | } |
1220 | 7a387fff | ths | |
1221 | 7a387fff | ths | void op_mtc0_datahi (void) |
1222 | 7a387fff | ths | { |
1223 | 7a387fff | ths | env->CP0_DataHi = T0; /* XXX */
|
1224 | 7a387fff | ths | RETURN(); |
1225 | 7a387fff | ths | } |
1226 | 7a387fff | ths | |
1227 | 8c0fdd85 | ths | void op_mtc0_errorepc (void) |
1228 | 8c0fdd85 | ths | { |
1229 | 8c0fdd85 | ths | env->CP0_ErrorEPC = T0; |
1230 | 8c0fdd85 | ths | RETURN(); |
1231 | 8c0fdd85 | ths | } |
1232 | 8c0fdd85 | ths | |
1233 | 8c0fdd85 | ths | void op_mtc0_desave (void) |
1234 | 8c0fdd85 | ths | { |
1235 | 8c0fdd85 | ths | env->CP0_DESAVE = T0; |
1236 | 6af0bf9c | bellard | RETURN(); |
1237 | 6af0bf9c | bellard | } |
1238 | 6af0bf9c | bellard | |
1239 | 6ea83fed | bellard | #ifdef MIPS_USES_FPU
|
1240 | 6ea83fed | bellard | |
1241 | 6ea83fed | bellard | #if 0
|
1242 | 6ea83fed | bellard | # define DEBUG_FPU_STATE() CALL_FROM_TB1(dump_fpu, env)
|
1243 | 6ea83fed | bellard | #else
|
1244 | 6ea83fed | bellard | # define DEBUG_FPU_STATE() do { } while(0) |
1245 | 6ea83fed | bellard | #endif
|
1246 | 6ea83fed | bellard | |
1247 | 6ea83fed | bellard | void op_cp1_enabled(void) |
1248 | 6ea83fed | bellard | { |
1249 | 6ea83fed | bellard | if (!(env->CP0_Status & (1 << CP0St_CU1))) { |
1250 | 6ea83fed | bellard | CALL_FROM_TB2(do_raise_exception_err, EXCP_CpU, 1);
|
1251 | 6ea83fed | bellard | } |
1252 | 6ea83fed | bellard | RETURN(); |
1253 | 6ea83fed | bellard | } |
1254 | 6ea83fed | bellard | |
1255 | 6ea83fed | bellard | /* CP1 functions */
|
1256 | 6ea83fed | bellard | void op_cfc1 (void) |
1257 | 6ea83fed | bellard | { |
1258 | 6ea83fed | bellard | if (T1 == 0) { |
1259 | 6ea83fed | bellard | T0 = env->fcr0; |
1260 | 6ea83fed | bellard | } |
1261 | 6ea83fed | bellard | else {
|
1262 | 6ea83fed | bellard | /* fetch fcr31, masking unused bits */
|
1263 | 6ea83fed | bellard | T0 = env->fcr31 & 0x0183FFFF;
|
1264 | 6ea83fed | bellard | } |
1265 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
1266 | 6ea83fed | bellard | RETURN(); |
1267 | 6ea83fed | bellard | } |
1268 | 6ea83fed | bellard | |
1269 | 6ea83fed | bellard | /* convert MIPS rounding mode in FCR31 to IEEE library */
|
1270 | 6ea83fed | bellard | unsigned int ieee_rm[] = { |
1271 | 6ea83fed | bellard | float_round_nearest_even, |
1272 | 6ea83fed | bellard | float_round_to_zero, |
1273 | 6ea83fed | bellard | float_round_up, |
1274 | 6ea83fed | bellard | float_round_down |
1275 | 6ea83fed | bellard | }; |
1276 | 6ea83fed | bellard | |
1277 | 6ea83fed | bellard | #define RESTORE_ROUNDING_MODE \
|
1278 | 6ea83fed | bellard | set_float_rounding_mode(ieee_rm[env->fcr31 & 3], &env->fp_status)
|
1279 | 6ea83fed | bellard | |
1280 | 6ea83fed | bellard | void op_ctc1 (void) |
1281 | 6ea83fed | bellard | { |
1282 | 6ea83fed | bellard | if (T1 == 0) { |
1283 | 6ea83fed | bellard | /* XXX should this throw an exception?
|
1284 | 6ea83fed | bellard | * don't write to FCR0.
|
1285 | 6ea83fed | bellard | * env->fcr0 = T0;
|
1286 | 6ea83fed | bellard | */
|
1287 | 6ea83fed | bellard | } |
1288 | 6ea83fed | bellard | else {
|
1289 | 6ea83fed | bellard | /* store new fcr31, masking unused bits */
|
1290 | 6ea83fed | bellard | env->fcr31 = T0 & 0x0183FFFF;
|
1291 | 6ea83fed | bellard | |
1292 | 6ea83fed | bellard | /* set rounding mode */
|
1293 | 6ea83fed | bellard | RESTORE_ROUNDING_MODE; |
1294 | 6ea83fed | bellard | |
1295 | 6ea83fed | bellard | #ifndef CONFIG_SOFTFLOAT
|
1296 | 6ea83fed | bellard | /* no floating point exception for native float */
|
1297 | 6ea83fed | bellard | SET_FP_ENABLE(env->fcr31, 0);
|
1298 | 6ea83fed | bellard | #endif
|
1299 | 6ea83fed | bellard | } |
1300 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
1301 | 6ea83fed | bellard | RETURN(); |
1302 | 6ea83fed | bellard | } |
1303 | 6ea83fed | bellard | |
1304 | 6ea83fed | bellard | void op_mfc1 (void) |
1305 | 6ea83fed | bellard | { |
1306 | 6ea83fed | bellard | T0 = WT0; |
1307 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
1308 | 6ea83fed | bellard | RETURN(); |
1309 | 6ea83fed | bellard | } |
1310 | 6ea83fed | bellard | |
1311 | 6ea83fed | bellard | void op_mtc1 (void) |
1312 | 6ea83fed | bellard | { |
1313 | 6ea83fed | bellard | WT0 = T0; |
1314 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
1315 | 6ea83fed | bellard | RETURN(); |
1316 | 6ea83fed | bellard | } |
1317 | 6ea83fed | bellard | |
1318 | 6ea83fed | bellard | /* Float support.
|
1319 | 6ea83fed | bellard | Single precition routines have a "s" suffix, double precision a
|
1320 | 6ea83fed | bellard | "d" suffix. */
|
1321 | 6ea83fed | bellard | |
1322 | 6ea83fed | bellard | #define FLOAT_OP(name, p) void OPPROTO op_float_##name##_##p(void) |
1323 | 6ea83fed | bellard | |
1324 | dd016883 | bellard | FLOAT_OP(cvtd, s) |
1325 | dd016883 | bellard | { |
1326 | dd016883 | bellard | FDT2 = float32_to_float64(WT0, &env->fp_status); |
1327 | dd016883 | bellard | DEBUG_FPU_STATE(); |
1328 | dd016883 | bellard | RETURN(); |
1329 | dd016883 | bellard | } |
1330 | 6ea83fed | bellard | FLOAT_OP(cvtd, w) |
1331 | 6ea83fed | bellard | { |
1332 | 6ea83fed | bellard | FDT2 = int32_to_float64(WT0, &env->fp_status); |
1333 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
1334 | 6ea83fed | bellard | RETURN(); |
1335 | 6ea83fed | bellard | } |
1336 | dd016883 | bellard | FLOAT_OP(cvts, d) |
1337 | dd016883 | bellard | { |
1338 | 417f38f0 | pbrook | FST2 = float64_to_float32(FDT0, &env->fp_status); |
1339 | dd016883 | bellard | DEBUG_FPU_STATE(); |
1340 | dd016883 | bellard | RETURN(); |
1341 | dd016883 | bellard | } |
1342 | 6ea83fed | bellard | FLOAT_OP(cvts, w) |
1343 | 6ea83fed | bellard | { |
1344 | 6ea83fed | bellard | FST2 = int32_to_float32(WT0, &env->fp_status); |
1345 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
1346 | 6ea83fed | bellard | RETURN(); |
1347 | 6ea83fed | bellard | } |
1348 | 6ea83fed | bellard | FLOAT_OP(cvtw, s) |
1349 | 6ea83fed | bellard | { |
1350 | 6ea83fed | bellard | WT2 = float32_to_int32(FST0, &env->fp_status); |
1351 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
1352 | 6ea83fed | bellard | RETURN(); |
1353 | 6ea83fed | bellard | } |
1354 | 6ea83fed | bellard | FLOAT_OP(cvtw, d) |
1355 | 6ea83fed | bellard | { |
1356 | 6ea83fed | bellard | WT2 = float64_to_int32(FDT0, &env->fp_status); |
1357 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
1358 | 6ea83fed | bellard | RETURN(); |
1359 | 6ea83fed | bellard | } |
1360 | 6ea83fed | bellard | |
1361 | 6ea83fed | bellard | FLOAT_OP(roundw, d) |
1362 | 6ea83fed | bellard | { |
1363 | 6ea83fed | bellard | set_float_rounding_mode(float_round_nearest_even, &env->fp_status); |
1364 | 6ea83fed | bellard | WT2 = float64_round_to_int(FDT0, &env->fp_status); |
1365 | 6ea83fed | bellard | RESTORE_ROUNDING_MODE; |
1366 | 6ea83fed | bellard | |
1367 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
1368 | 6ea83fed | bellard | RETURN(); |
1369 | 6ea83fed | bellard | } |
1370 | 6ea83fed | bellard | FLOAT_OP(roundw, s) |
1371 | 6ea83fed | bellard | { |
1372 | 6ea83fed | bellard | set_float_rounding_mode(float_round_nearest_even, &env->fp_status); |
1373 | 6ea83fed | bellard | WT2 = float32_round_to_int(FST0, &env->fp_status); |
1374 | 6ea83fed | bellard | RESTORE_ROUNDING_MODE; |
1375 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
1376 | 6ea83fed | bellard | RETURN(); |
1377 | 6ea83fed | bellard | } |
1378 | 6ea83fed | bellard | |
1379 | 6ea83fed | bellard | FLOAT_OP(truncw, d) |
1380 | 6ea83fed | bellard | { |
1381 | 6ea83fed | bellard | WT2 = float64_to_int32_round_to_zero(FDT0, &env->fp_status); |
1382 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
1383 | 6ea83fed | bellard | RETURN(); |
1384 | 6ea83fed | bellard | } |
1385 | 6ea83fed | bellard | FLOAT_OP(truncw, s) |
1386 | 6ea83fed | bellard | { |
1387 | 6ea83fed | bellard | WT2 = float32_to_int32_round_to_zero(FST0, &env->fp_status); |
1388 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
1389 | 6ea83fed | bellard | RETURN(); |
1390 | 6ea83fed | bellard | } |
1391 | 6ea83fed | bellard | |
1392 | 6ea83fed | bellard | FLOAT_OP(ceilw, d) |
1393 | 6ea83fed | bellard | { |
1394 | 6ea83fed | bellard | set_float_rounding_mode(float_round_up, &env->fp_status); |
1395 | 6ea83fed | bellard | WT2 = float64_round_to_int(FDT0, &env->fp_status); |
1396 | 6ea83fed | bellard | RESTORE_ROUNDING_MODE; |
1397 | 6ea83fed | bellard | |
1398 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
1399 | 6ea83fed | bellard | RETURN(); |
1400 | 6ea83fed | bellard | } |
1401 | 6ea83fed | bellard | FLOAT_OP(ceilw, s) |
1402 | 6ea83fed | bellard | { |
1403 | 6ea83fed | bellard | set_float_rounding_mode(float_round_up, &env->fp_status); |
1404 | 6ea83fed | bellard | WT2 = float32_round_to_int(FST0, &env->fp_status); |
1405 | 6ea83fed | bellard | RESTORE_ROUNDING_MODE; |
1406 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
1407 | 6ea83fed | bellard | RETURN(); |
1408 | 6ea83fed | bellard | } |
1409 | 6ea83fed | bellard | |
1410 | 6ea83fed | bellard | FLOAT_OP(floorw, d) |
1411 | 6ea83fed | bellard | { |
1412 | 6ea83fed | bellard | set_float_rounding_mode(float_round_down, &env->fp_status); |
1413 | 6ea83fed | bellard | WT2 = float64_round_to_int(FDT0, &env->fp_status); |
1414 | 6ea83fed | bellard | RESTORE_ROUNDING_MODE; |
1415 | 6ea83fed | bellard | |
1416 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
1417 | 6ea83fed | bellard | RETURN(); |
1418 | 6ea83fed | bellard | } |
1419 | 6ea83fed | bellard | FLOAT_OP(floorw, s) |
1420 | 6ea83fed | bellard | { |
1421 | 6ea83fed | bellard | set_float_rounding_mode(float_round_down, &env->fp_status); |
1422 | 6ea83fed | bellard | WT2 = float32_round_to_int(FST0, &env->fp_status); |
1423 | 6ea83fed | bellard | RESTORE_ROUNDING_MODE; |
1424 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
1425 | 6ea83fed | bellard | RETURN(); |
1426 | 6ea83fed | bellard | } |
1427 | 6ea83fed | bellard | |
1428 | 6ea83fed | bellard | /* binary operations */
|
1429 | 6ea83fed | bellard | #define FLOAT_BINOP(name) \
|
1430 | 6ea83fed | bellard | FLOAT_OP(name, d) \ |
1431 | 6ea83fed | bellard | { \ |
1432 | 6ea83fed | bellard | FDT2 = float64_ ## name (FDT0, FDT1, &env->fp_status); \ |
1433 | 6ea83fed | bellard | DEBUG_FPU_STATE(); \ |
1434 | 6ea83fed | bellard | } \ |
1435 | 6ea83fed | bellard | FLOAT_OP(name, s) \ |
1436 | 6ea83fed | bellard | { \ |
1437 | 6ea83fed | bellard | FST2 = float32_ ## name (FST0, FST1, &env->fp_status); \ |
1438 | 6ea83fed | bellard | DEBUG_FPU_STATE(); \ |
1439 | 6ea83fed | bellard | } |
1440 | 6ea83fed | bellard | FLOAT_BINOP(add) |
1441 | 6ea83fed | bellard | FLOAT_BINOP(sub) |
1442 | 6ea83fed | bellard | FLOAT_BINOP(mul) |
1443 | 6ea83fed | bellard | FLOAT_BINOP(div) |
1444 | 6ea83fed | bellard | #undef FLOAT_BINOP
|
1445 | 6ea83fed | bellard | |
1446 | 6ea83fed | bellard | /* unary operations, modifying fp status */
|
1447 | 6ea83fed | bellard | #define FLOAT_UNOP(name) \
|
1448 | 6ea83fed | bellard | FLOAT_OP(name, d) \ |
1449 | 6ea83fed | bellard | { \ |
1450 | 6ea83fed | bellard | FDT2 = float64_ ## name(FDT0, &env->fp_status); \ |
1451 | 6ea83fed | bellard | DEBUG_FPU_STATE(); \ |
1452 | 6ea83fed | bellard | } \ |
1453 | 6ea83fed | bellard | FLOAT_OP(name, s) \ |
1454 | 6ea83fed | bellard | { \ |
1455 | 6ea83fed | bellard | FST2 = float32_ ## name(FST0, &env->fp_status); \ |
1456 | 6ea83fed | bellard | DEBUG_FPU_STATE(); \ |
1457 | 6ea83fed | bellard | } |
1458 | 6ea83fed | bellard | FLOAT_UNOP(sqrt) |
1459 | 6ea83fed | bellard | #undef FLOAT_UNOP
|
1460 | 6ea83fed | bellard | |
1461 | 6ea83fed | bellard | /* unary operations, not modifying fp status */
|
1462 | 6ea83fed | bellard | #define FLOAT_UNOP(name) \
|
1463 | 6ea83fed | bellard | FLOAT_OP(name, d) \ |
1464 | 6ea83fed | bellard | { \ |
1465 | 6ea83fed | bellard | FDT2 = float64_ ## name(FDT0); \ |
1466 | 6ea83fed | bellard | DEBUG_FPU_STATE(); \ |
1467 | 6ea83fed | bellard | } \ |
1468 | 6ea83fed | bellard | FLOAT_OP(name, s) \ |
1469 | 6ea83fed | bellard | { \ |
1470 | 6ea83fed | bellard | FST2 = float32_ ## name(FST0); \ |
1471 | 6ea83fed | bellard | DEBUG_FPU_STATE(); \ |
1472 | 6ea83fed | bellard | } |
1473 | 6ea83fed | bellard | FLOAT_UNOP(abs) |
1474 | 6ea83fed | bellard | FLOAT_UNOP(chs) |
1475 | 6ea83fed | bellard | #undef FLOAT_UNOP
|
1476 | 6ea83fed | bellard | |
1477 | 6ea83fed | bellard | FLOAT_OP(mov, d) |
1478 | 6ea83fed | bellard | { |
1479 | 6ea83fed | bellard | FDT2 = FDT0; |
1480 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
1481 | 6ea83fed | bellard | RETURN(); |
1482 | 6ea83fed | bellard | } |
1483 | 6ea83fed | bellard | FLOAT_OP(mov, s) |
1484 | 6ea83fed | bellard | { |
1485 | 6ea83fed | bellard | FST2 = FST0; |
1486 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
1487 | 6ea83fed | bellard | RETURN(); |
1488 | 6ea83fed | bellard | } |
1489 | 6ea83fed | bellard | |
1490 | 6ea83fed | bellard | #ifdef CONFIG_SOFTFLOAT
|
1491 | 6ea83fed | bellard | #define clear_invalid() do { \ |
1492 | 6ea83fed | bellard | int flags = get_float_exception_flags(&env->fp_status); \
|
1493 | 6ea83fed | bellard | flags &= ~float_flag_invalid; \ |
1494 | 6ea83fed | bellard | set_float_exception_flags(flags, &env->fp_status); \ |
1495 | 6ea83fed | bellard | } while(0) |
1496 | 6ea83fed | bellard | #else
|
1497 | 6ea83fed | bellard | #define clear_invalid() do { } while(0) |
1498 | 6ea83fed | bellard | #endif
|
1499 | 6ea83fed | bellard | |
1500 | 6ea83fed | bellard | extern void dump_fpu_s(CPUState *env); |
1501 | 6ea83fed | bellard | |
1502 | 6ea83fed | bellard | #define FOP_COND(fmt, op, sig, cond) \
|
1503 | 6ea83fed | bellard | void op_cmp_ ## fmt ## _ ## op (void) \ |
1504 | 6ea83fed | bellard | { \ |
1505 | 6ea83fed | bellard | if (cond) \
|
1506 | 6ea83fed | bellard | SET_FP_COND(env->fcr31); \ |
1507 | 6ea83fed | bellard | else \
|
1508 | 6ea83fed | bellard | CLEAR_FP_COND(env->fcr31); \ |
1509 | 6ea83fed | bellard | if (!sig) \
|
1510 | 6ea83fed | bellard | clear_invalid(); \ |
1511 | 6ea83fed | bellard | /*CALL_FROM_TB1(dump_fpu_s, env);*/ \
|
1512 | 6ea83fed | bellard | DEBUG_FPU_STATE(); \ |
1513 | 6ea83fed | bellard | RETURN(); \ |
1514 | 6ea83fed | bellard | } |
1515 | 6ea83fed | bellard | |
1516 | 569f5d66 | bellard | int float64_is_unordered(float64 a, float64 b STATUS_PARAM)
|
1517 | 6ea83fed | bellard | { |
1518 | 6ea83fed | bellard | if (float64_is_nan(a) || float64_is_nan(b)) {
|
1519 | 6ea83fed | bellard | float_raise(float_flag_invalid, status); |
1520 | 6ea83fed | bellard | return 1; |
1521 | 6ea83fed | bellard | } |
1522 | 6ea83fed | bellard | else {
|
1523 | 6ea83fed | bellard | return 0; |
1524 | 6ea83fed | bellard | } |
1525 | 6ea83fed | bellard | } |
1526 | 6ea83fed | bellard | |
1527 | 6ea83fed | bellard | FOP_COND(d, f, 0, 0) |
1528 | 6ea83fed | bellard | FOP_COND(d, un, 0, float64_is_unordered(FDT1, FDT0, &env->fp_status))
|
1529 | 6ea83fed | bellard | FOP_COND(d, eq, 0, float64_eq(FDT0, FDT1, &env->fp_status))
|
1530 | 6ea83fed | bellard | FOP_COND(d, ueq, 0, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_eq(FDT0, FDT1, &env->fp_status))
|
1531 | 6ea83fed | bellard | FOP_COND(d, olt, 0, float64_lt(FDT0, FDT1, &env->fp_status))
|
1532 | 6ea83fed | bellard | FOP_COND(d, ult, 0, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_lt(FDT0, FDT1, &env->fp_status))
|
1533 | 6ea83fed | bellard | FOP_COND(d, ole, 0, float64_le(FDT0, FDT1, &env->fp_status))
|
1534 | 6ea83fed | bellard | FOP_COND(d, ule, 0, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_le(FDT0, FDT1, &env->fp_status))
|
1535 | 6ea83fed | bellard | /* NOTE: the comma operator will make "cond" to eval to false,
|
1536 | 6ea83fed | bellard | * but float*_is_unordered() is still called
|
1537 | 6ea83fed | bellard | */
|
1538 | 6ea83fed | bellard | FOP_COND(d, sf, 1, (float64_is_unordered(FDT0, FDT1, &env->fp_status), 0)) |
1539 | 6ea83fed | bellard | FOP_COND(d, ngle,1, float64_is_unordered(FDT1, FDT0, &env->fp_status))
|
1540 | 6ea83fed | bellard | FOP_COND(d, seq, 1, float64_eq(FDT0, FDT1, &env->fp_status))
|
1541 | 6ea83fed | bellard | FOP_COND(d, ngl, 1, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_eq(FDT0, FDT1, &env->fp_status))
|
1542 | 6ea83fed | bellard | FOP_COND(d, lt, 1, float64_lt(FDT0, FDT1, &env->fp_status))
|
1543 | 6ea83fed | bellard | FOP_COND(d, nge, 1, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_lt(FDT0, FDT1, &env->fp_status))
|
1544 | 6ea83fed | bellard | FOP_COND(d, le, 1, float64_le(FDT0, FDT1, &env->fp_status))
|
1545 | 6ea83fed | bellard | FOP_COND(d, ngt, 1, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_le(FDT0, FDT1, &env->fp_status))
|
1546 | 6ea83fed | bellard | |
1547 | 6ea83fed | bellard | flag float32_is_unordered(float32 a, float32 b STATUS_PARAM) |
1548 | 6ea83fed | bellard | { |
1549 | 6ea83fed | bellard | extern flag float32_is_nan( float32 a );
|
1550 | 6ea83fed | bellard | if (float32_is_nan(a) || float32_is_nan(b)) {
|
1551 | 6ea83fed | bellard | float_raise(float_flag_invalid, status); |
1552 | 6ea83fed | bellard | return 1; |
1553 | 6ea83fed | bellard | } |
1554 | 6ea83fed | bellard | else {
|
1555 | 6ea83fed | bellard | return 0; |
1556 | 6ea83fed | bellard | } |
1557 | 6ea83fed | bellard | } |
1558 | 6ea83fed | bellard | |
1559 | 6ea83fed | bellard | /* NOTE: the comma operator will make "cond" to eval to false,
|
1560 | 6ea83fed | bellard | * but float*_is_unordered() is still called
|
1561 | 6ea83fed | bellard | */
|
1562 | 6ea83fed | bellard | FOP_COND(s, f, 0, 0) |
1563 | 6ea83fed | bellard | FOP_COND(s, un, 0, float32_is_unordered(FST1, FST0, &env->fp_status))
|
1564 | 6ea83fed | bellard | FOP_COND(s, eq, 0, float32_eq(FST0, FST1, &env->fp_status))
|
1565 | 6ea83fed | bellard | FOP_COND(s, ueq, 0, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_eq(FST0, FST1, &env->fp_status))
|
1566 | 6ea83fed | bellard | FOP_COND(s, olt, 0, float32_lt(FST0, FST1, &env->fp_status))
|
1567 | 6ea83fed | bellard | FOP_COND(s, ult, 0, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_lt(FST0, FST1, &env->fp_status))
|
1568 | 6ea83fed | bellard | FOP_COND(s, ole, 0, float32_le(FST0, FST1, &env->fp_status))
|
1569 | 6ea83fed | bellard | FOP_COND(s, ule, 0, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_le(FST0, FST1, &env->fp_status))
|
1570 | 6ea83fed | bellard | /* NOTE: the comma operator will make "cond" to eval to false,
|
1571 | 6ea83fed | bellard | * but float*_is_unordered() is still called
|
1572 | 6ea83fed | bellard | */
|
1573 | 6ea83fed | bellard | FOP_COND(s, sf, 1, (float32_is_unordered(FST0, FST1, &env->fp_status), 0)) |
1574 | 6ea83fed | bellard | FOP_COND(s, ngle,1, float32_is_unordered(FST1, FST0, &env->fp_status))
|
1575 | 6ea83fed | bellard | FOP_COND(s, seq, 1, float32_eq(FST0, FST1, &env->fp_status))
|
1576 | 6ea83fed | bellard | FOP_COND(s, ngl, 1, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_eq(FST0, FST1, &env->fp_status))
|
1577 | 6ea83fed | bellard | FOP_COND(s, lt, 1, float32_lt(FST0, FST1, &env->fp_status))
|
1578 | 6ea83fed | bellard | FOP_COND(s, nge, 1, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_lt(FST0, FST1, &env->fp_status))
|
1579 | 6ea83fed | bellard | FOP_COND(s, le, 1, float32_le(FST0, FST1, &env->fp_status))
|
1580 | 6ea83fed | bellard | FOP_COND(s, ngt, 1, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_le(FST0, FST1, &env->fp_status))
|
1581 | 6ea83fed | bellard | |
1582 | 6ea83fed | bellard | void op_bc1f (void) |
1583 | 6ea83fed | bellard | { |
1584 | 6ea83fed | bellard | T0 = ! IS_FP_COND_SET(env->fcr31); |
1585 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
1586 | 6ea83fed | bellard | RETURN(); |
1587 | 6ea83fed | bellard | } |
1588 | 6ea83fed | bellard | |
1589 | 6ea83fed | bellard | void op_bc1t (void) |
1590 | 6ea83fed | bellard | { |
1591 | 6ea83fed | bellard | T0 = IS_FP_COND_SET(env->fcr31); |
1592 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
1593 | 6ea83fed | bellard | RETURN(); |
1594 | 6ea83fed | bellard | } |
1595 | 6ea83fed | bellard | #endif /* MIPS_USES_FPU */ |
1596 | 6ea83fed | bellard | |
1597 | 6af0bf9c | bellard | #if defined(MIPS_USES_R4K_TLB)
|
1598 | 6af0bf9c | bellard | void op_tlbwi (void) |
1599 | 6af0bf9c | bellard | { |
1600 | 6af0bf9c | bellard | CALL_FROM_TB0(do_tlbwi); |
1601 | 6af0bf9c | bellard | RETURN(); |
1602 | 6af0bf9c | bellard | } |
1603 | 6af0bf9c | bellard | |
1604 | 6af0bf9c | bellard | void op_tlbwr (void) |
1605 | 6af0bf9c | bellard | { |
1606 | 6af0bf9c | bellard | CALL_FROM_TB0(do_tlbwr); |
1607 | 6af0bf9c | bellard | RETURN(); |
1608 | 6af0bf9c | bellard | } |
1609 | 6af0bf9c | bellard | |
1610 | 6af0bf9c | bellard | void op_tlbp (void) |
1611 | 6af0bf9c | bellard | { |
1612 | 6af0bf9c | bellard | CALL_FROM_TB0(do_tlbp); |
1613 | 6af0bf9c | bellard | RETURN(); |
1614 | 6af0bf9c | bellard | } |
1615 | 6af0bf9c | bellard | |
1616 | 6af0bf9c | bellard | void op_tlbr (void) |
1617 | 6af0bf9c | bellard | { |
1618 | 6af0bf9c | bellard | CALL_FROM_TB0(do_tlbr); |
1619 | 6af0bf9c | bellard | RETURN(); |
1620 | 6af0bf9c | bellard | } |
1621 | 6af0bf9c | bellard | #endif
|
1622 | 6af0bf9c | bellard | |
1623 | 6af0bf9c | bellard | /* Specials */
|
1624 | 6af0bf9c | bellard | void op_pmon (void) |
1625 | 6af0bf9c | bellard | { |
1626 | 6af0bf9c | bellard | CALL_FROM_TB1(do_pmon, PARAM1); |
1627 | 7a387fff | ths | RETURN(); |
1628 | 7a387fff | ths | } |
1629 | 7a387fff | ths | |
1630 | 7a387fff | ths | void op_di (void) |
1631 | 7a387fff | ths | { |
1632 | 7a387fff | ths | uint32_t val; |
1633 | 7a387fff | ths | |
1634 | 7a387fff | ths | T0 = env->CP0_Status; |
1635 | 7a387fff | ths | val = T0 & ~(1 << CP0St_IE);
|
1636 | 7a387fff | ths | if (val != T0) {
|
1637 | 7a387fff | ths | env->interrupt_request &= ~CPU_INTERRUPT_HARD; |
1638 | 7a387fff | ths | env->CP0_Status = val; |
1639 | 7a387fff | ths | } |
1640 | 7a387fff | ths | RETURN(); |
1641 | 7a387fff | ths | } |
1642 | 7a387fff | ths | |
1643 | 7a387fff | ths | void op_ei (void) |
1644 | 7a387fff | ths | { |
1645 | 7a387fff | ths | uint32_t val; |
1646 | 7a387fff | ths | |
1647 | 7a387fff | ths | T0 = env->CP0_Status; |
1648 | 7a387fff | ths | val = T0 | (1 << CP0St_IE);
|
1649 | 7a387fff | ths | if (val != T0) {
|
1650 | 7a387fff | ths | const uint32_t mask = 0x0000FF00; |
1651 | 7a387fff | ths | |
1652 | 7a387fff | ths | env->CP0_Status = val; |
1653 | 7a387fff | ths | if (!(env->hflags & MIPS_HFLAG_EXL) &&
|
1654 | 7a387fff | ths | !(env->hflags & MIPS_HFLAG_ERL) && |
1655 | 7a387fff | ths | !(env->hflags & MIPS_HFLAG_DM) && |
1656 | 7a387fff | ths | (env->CP0_Status & env->CP0_Cause & mask)) { |
1657 | 7a387fff | ths | env->interrupt_request |= CPU_INTERRUPT_HARD; |
1658 | 7a387fff | ths | if (logfile)
|
1659 | 7a387fff | ths | CALL_FROM_TB0(do_mtc0_status_irqraise_debug); |
1660 | 7a387fff | ths | } |
1661 | 7a387fff | ths | } |
1662 | 7a387fff | ths | RETURN(); |
1663 | 6af0bf9c | bellard | } |
1664 | 6af0bf9c | bellard | |
1665 | 6af0bf9c | bellard | void op_trap (void) |
1666 | 6af0bf9c | bellard | { |
1667 | 6af0bf9c | bellard | if (T0) {
|
1668 | 4ad40f36 | bellard | CALL_FROM_TB1(do_raise_exception_direct, EXCP_TRAP); |
1669 | 6af0bf9c | bellard | } |
1670 | 6af0bf9c | bellard | RETURN(); |
1671 | 6af0bf9c | bellard | } |
1672 | 6af0bf9c | bellard | |
1673 | 4ad40f36 | bellard | void op_debug (void) |
1674 | 4ad40f36 | bellard | { |
1675 | 7a387fff | ths | CALL_FROM_TB1(do_raise_exception, EXCP_DEBUG); |
1676 | 7a387fff | ths | RETURN(); |
1677 | 4ad40f36 | bellard | } |
1678 | 4ad40f36 | bellard | |
1679 | 6af0bf9c | bellard | void op_set_lladdr (void) |
1680 | 6af0bf9c | bellard | { |
1681 | 6af0bf9c | bellard | env->CP0_LLAddr = T2; |
1682 | 7a387fff | ths | RETURN(); |
1683 | 6af0bf9c | bellard | } |
1684 | 6af0bf9c | bellard | |
1685 | 6af0bf9c | bellard | void debug_eret (void); |
1686 | 6af0bf9c | bellard | void op_eret (void) |
1687 | 6af0bf9c | bellard | { |
1688 | 6af0bf9c | bellard | CALL_FROM_TB0(debug_eret); |
1689 | 51e11d9e | bellard | if (env->hflags & MIPS_HFLAG_ERL) {
|
1690 | 6af0bf9c | bellard | env->PC = env->CP0_ErrorEPC; |
1691 | 51e11d9e | bellard | env->hflags &= ~MIPS_HFLAG_ERL; |
1692 | 3e382bc8 | bellard | env->CP0_Status &= ~(1 << CP0St_ERL);
|
1693 | 51e11d9e | bellard | } else {
|
1694 | 6af0bf9c | bellard | env->PC = env->CP0_EPC; |
1695 | 51e11d9e | bellard | env->hflags &= ~MIPS_HFLAG_EXL; |
1696 | 3e382bc8 | bellard | env->CP0_Status &= ~(1 << CP0St_EXL);
|
1697 | 51e11d9e | bellard | } |
1698 | 6af0bf9c | bellard | env->CP0_LLAddr = 1;
|
1699 | 7a387fff | ths | RETURN(); |
1700 | 6af0bf9c | bellard | } |
1701 | 6af0bf9c | bellard | |
1702 | 6af0bf9c | bellard | void op_deret (void) |
1703 | 6af0bf9c | bellard | { |
1704 | 6af0bf9c | bellard | CALL_FROM_TB0(debug_eret); |
1705 | 6af0bf9c | bellard | env->PC = env->CP0_DEPC; |
1706 | 7a387fff | ths | RETURN(); |
1707 | 7a387fff | ths | } |
1708 | 7a387fff | ths | |
1709 | 7a387fff | ths | void op_rdhwr_cpunum(void) |
1710 | 7a387fff | ths | { |
1711 | 7a387fff | ths | if (env->CP0_HWREna & (1 << 0)) |
1712 | 7a387fff | ths | T0 = env->CP0_EBase & 0x2ff;
|
1713 | 7a387fff | ths | else
|
1714 | 7a387fff | ths | CALL_FROM_TB1(do_raise_exception_direct, EXCP_RI); |
1715 | 7a387fff | ths | RETURN(); |
1716 | 7a387fff | ths | } |
1717 | 7a387fff | ths | |
1718 | 7a387fff | ths | void op_rdhwr_synci_step(void) |
1719 | 7a387fff | ths | { |
1720 | 7a387fff | ths | if (env->CP0_HWREna & (1 << 1)) |
1721 | 7a387fff | ths | T0 = env->SYNCI_Step; |
1722 | 7a387fff | ths | else
|
1723 | 7a387fff | ths | CALL_FROM_TB1(do_raise_exception_direct, EXCP_RI); |
1724 | 7a387fff | ths | RETURN(); |
1725 | 7a387fff | ths | } |
1726 | 7a387fff | ths | |
1727 | 7a387fff | ths | void op_rdhwr_cc(void) |
1728 | 7a387fff | ths | { |
1729 | 7a387fff | ths | if (env->CP0_HWREna & (1 << 2)) |
1730 | 7a387fff | ths | T0 = env->CP0_Count; |
1731 | 7a387fff | ths | else
|
1732 | 7a387fff | ths | CALL_FROM_TB1(do_raise_exception_direct, EXCP_RI); |
1733 | 7a387fff | ths | RETURN(); |
1734 | 7a387fff | ths | } |
1735 | 7a387fff | ths | |
1736 | 7a387fff | ths | void op_rdhwr_ccres(void) |
1737 | 7a387fff | ths | { |
1738 | 7a387fff | ths | if (env->CP0_HWREna & (1 << 3)) |
1739 | 7a387fff | ths | T0 = env->CCRes; |
1740 | 7a387fff | ths | else
|
1741 | 7a387fff | ths | CALL_FROM_TB1(do_raise_exception_direct, EXCP_RI); |
1742 | 7a387fff | ths | RETURN(); |
1743 | 6af0bf9c | bellard | } |
1744 | 6af0bf9c | bellard | |
1745 | 6af0bf9c | bellard | void op_save_state (void) |
1746 | 6af0bf9c | bellard | { |
1747 | 6af0bf9c | bellard | env->hflags = PARAM1; |
1748 | 6af0bf9c | bellard | RETURN(); |
1749 | 6af0bf9c | bellard | } |
1750 | 6af0bf9c | bellard | |
1751 | 6af0bf9c | bellard | void op_save_pc (void) |
1752 | 6af0bf9c | bellard | { |
1753 | 6af0bf9c | bellard | env->PC = PARAM1; |
1754 | 6af0bf9c | bellard | RETURN(); |
1755 | 6af0bf9c | bellard | } |
1756 | 6af0bf9c | bellard | |
1757 | 6af0bf9c | bellard | void op_raise_exception (void) |
1758 | 6af0bf9c | bellard | { |
1759 | 6af0bf9c | bellard | CALL_FROM_TB1(do_raise_exception, PARAM1); |
1760 | 6af0bf9c | bellard | RETURN(); |
1761 | 6af0bf9c | bellard | } |
1762 | 6af0bf9c | bellard | |
1763 | 6af0bf9c | bellard | void op_raise_exception_err (void) |
1764 | 6af0bf9c | bellard | { |
1765 | 6af0bf9c | bellard | CALL_FROM_TB2(do_raise_exception_err, PARAM1, PARAM2); |
1766 | 6af0bf9c | bellard | RETURN(); |
1767 | 6af0bf9c | bellard | } |
1768 | 6af0bf9c | bellard | |
1769 | 6af0bf9c | bellard | void op_exit_tb (void) |
1770 | 6af0bf9c | bellard | { |
1771 | 6af0bf9c | bellard | EXIT_TB(); |
1772 | 7a387fff | ths | RETURN(); |
1773 | 6af0bf9c | bellard | } |
1774 | 6af0bf9c | bellard | |
1775 | 4ad40f36 | bellard | void op_wait (void) |
1776 | 4ad40f36 | bellard | { |
1777 | 4ad40f36 | bellard | env->halted = 1;
|
1778 | 4ad40f36 | bellard | CALL_FROM_TB1(do_raise_exception, EXCP_HLT); |
1779 | 7a387fff | ths | RETURN(); |
1780 | 7a387fff | ths | } |
1781 | 7a387fff | ths | |
1782 | 7a387fff | ths | /* Bitfield operations. */
|
1783 | 7a387fff | ths | void op_ext(void) |
1784 | 7a387fff | ths | { |
1785 | 7a387fff | ths | unsigned int pos = PARAM1; |
1786 | 7a387fff | ths | unsigned int size = PARAM2; |
1787 | 7a387fff | ths | |
1788 | 7a387fff | ths | T0 = (T1 >> pos) & ((1 << size) - 1); |
1789 | 7a387fff | ths | RETURN(); |
1790 | 7a387fff | ths | } |
1791 | 7a387fff | ths | |
1792 | 7a387fff | ths | void op_ins(void) |
1793 | 7a387fff | ths | { |
1794 | 7a387fff | ths | unsigned int pos = PARAM1; |
1795 | 7a387fff | ths | unsigned int size = PARAM2; |
1796 | 7a387fff | ths | target_ulong mask = ((1 << size) - 1) << pos; |
1797 | 7a387fff | ths | |
1798 | 7a387fff | ths | T0 = (T2 & ~mask) | ((T1 << pos) & mask); |
1799 | 7a387fff | ths | RETURN(); |
1800 | 7a387fff | ths | } |
1801 | 7a387fff | ths | |
1802 | 7a387fff | ths | void op_wsbh(void) |
1803 | 7a387fff | ths | { |
1804 | 7a387fff | ths | T0 = ((T1 << 8) & ~0x00FF00FF) | ((T1 >> 8) & 0x00FF00FF); |
1805 | 7a387fff | ths | RETURN(); |
1806 | 7a387fff | ths | } |
1807 | 7a387fff | ths | |
1808 | 7a387fff | ths | void op_dsbh(void) |
1809 | 7a387fff | ths | { |
1810 | 7a387fff | ths | T0 = ((T1 << 8) & ~0x00FF00FF00FF00FFULL) | ((T1 >> 8) & 0x00FF00FF00FF00FFULL); |
1811 | 7a387fff | ths | RETURN(); |
1812 | 7a387fff | ths | } |
1813 | 7a387fff | ths | |
1814 | 7a387fff | ths | void op_dshd(void) |
1815 | 7a387fff | ths | { |
1816 | 7a387fff | ths | T0 = ((T1 << 16) & ~0x0000FFFF0000FFFFULL) | ((T1 >> 16) & 0x0000FFFF0000FFFFULL); |
1817 | 7a387fff | ths | RETURN(); |
1818 | 7a387fff | ths | } |
1819 | 7a387fff | ths | |
1820 | 7a387fff | ths | void op_seb(void) |
1821 | 7a387fff | ths | { |
1822 | 7a387fff | ths | T0 = ((T1 & 0xFF) ^ 0x80) - 0x80; |
1823 | 7a387fff | ths | RETURN(); |
1824 | 7a387fff | ths | } |
1825 | 7a387fff | ths | |
1826 | 7a387fff | ths | void op_seh(void) |
1827 | 7a387fff | ths | { |
1828 | 7a387fff | ths | T0 = ((T1 & 0xFFFF) ^ 0x8000) - 0x8000; |
1829 | 7a387fff | ths | RETURN(); |
1830 | 4ad40f36 | bellard | } |