Revision 7a387fff target-mips/mips-defs.h

b/target-mips/mips-defs.h
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 * Define a major version 1, minor version 0.
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 */
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#define MIPS_FCR0 ((0 << 16) | (1 << 8) | (1 << 4) | 0)
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/* Have config1, uses TLB */
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#define MIPS_CONFIG0_1                                          \
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((1 << CP0C0_M) | (0 << CP0C0_K23) | (0 << CP0C0_KU) |          \
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 (1 << CP0C0_MT) | (2 << CP0C0_K0))
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  /* Have config1, is MIPS32R1, uses TLB, no virtual icache,
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     uncached coherency */
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#define MIPS_CONFIG0_1                                            \
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  ((1 << CP0C0_M) | (0x0 << CP0C0_K23) | (0x0 << CP0C0_KU) |      \
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   (0x0 << CP0C0_AT) | (0x0 << CP0C0_AR) | (0x1 << CP0C0_MT) |    \
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   (0x2 << CP0C0_K0))
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#ifdef TARGET_WORDS_BIGENDIAN
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#define MIPS_CONFIG0 (MIPS_CONFIG0_1 | (1 << CP0C0_BE))
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#else
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#define MIPS_CONFIG0 MIPS_CONFIG0_1
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#endif
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/* 16 TLBs, 64 sets Icache, 16 bytes Icache line, 2-way Icache,
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 * 64 sets Dcache, 16 bytes Dcache line, 2-way Dcache,
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 * no performance counters, watch registers present, no code compression,
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 * EJTAG present, FPU enable bit depending on MIPS_USES_FPU
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 */
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#define MIPS_CONFIG1                                            \
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((15 << CP0C1_MMU) |                                            \
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 (0x000 << CP0C1_IS) | (0x3 << CP0C1_IL) | (0x01 << CP0C1_IA) | \
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 (0x000 << CP0C1_DS) | (0x3 << CP0C1_DL) | (0x01 << CP0C1_DA) | \
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 (0 << CP0C1_PC) | (1 << CP0C1_WR) | (0 << CP0C1_CA) |          \
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 (1 << CP0C1_EP) | (MIPS_USES_FPU << CP0C1_FP))
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/* Have config2, 16 TLB entries, 64 sets Icache, 16 bytes Icache line,
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   2-way Icache, 64 sets Dcache, 16 bytes Dcache line, 2-way Dcache,
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   no coprocessor2 attached, no MDMX support attached,
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   no performance counters, watch registers present,
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   no code compression, EJTAG present, FPU enable bit depending on
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   MIPS_USES_FPU */
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#define MIPS_CONFIG1_1                                            \
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((1 << CP0C1_M) | ((MIPS_TLB_NB - 1) << CP0C1_MMU) |              \
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 (0x0 << CP0C1_IS) | (0x3 << CP0C1_IL) | (0x1 << CP0C1_IA) |      \
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 (0x0 << CP0C1_DS) | (0x3 << CP0C1_DL) | (0x1 << CP0C1_DA) |      \
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 (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) |            \
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 (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP))
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#ifdef MIPS_USES_FPU
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#define MIPS_CONFIG1  (MIPS_CONFIG1_1 | (1 << CP0C1_FP))
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#else
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#define MIPS_CONFIG1  (MIPS_CONFIG1_1 | (0 << CP0C1_FP))
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#endif
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/* Have config3, no tertiary/secondary caches implemented */
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#define MIPS_CONFIG2                                              \
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((1 << CP0C2_M))
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/* No config4, no DSP ASE, no large physaddr,
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   no external interrupt controller, no vectored interupts,
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   no 1kb pages, no MT ASE, no SmartMIPS ASE, no trace logic */
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#define MIPS_CONFIG3                                              \
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((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) |          \
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 (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) |        \
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 (0 << CP0C3_MT) | (0 << CP0C3_SM) | (0 << CP0C3_TL))
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#elif (MIPS_CPU == MIPS_R4Kp)
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/* 32 bits target */
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#define TARGET_LONG_BITS 32
......
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#define MIPS_USES_R4K_FPM
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#else
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#error "MIPS CPU not defined"
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/* Remainder for other flags */
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/* Reminder for other flags */
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//#define TARGET_MIPS64
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//#define MIPS_USES_FPU
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#endif

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