Revision 7a962d30
| b/target-mips/helper.c | ||
|---|---|---|
| 33 | 33 |
ret = -2; |
| 34 | 34 |
tag = (address & 0xFFFFE000); |
| 35 | 35 |
ASID = env->CP0_EntryHi & 0x000000FF; |
| 36 |
for (i = 0; i < 16; i++) {
|
|
| 36 |
for (i = 0; i < MIPS_TLB_NB; i++) {
|
|
| 37 | 37 |
tlb = &env->tlb[i]; |
| 38 | 38 |
/* Check ASID, virtual page number & size */ |
| 39 | 39 |
if ((tlb->G == 1 || tlb->ASID == ASID) && |
| b/target-mips/op_helper.c | ||
|---|---|---|
| 531 | 531 |
|
| 532 | 532 |
void do_tlbwi (void) |
| 533 | 533 |
{
|
| 534 |
invalidate_tb(env->CP0_index & 0xF); |
|
| 535 |
fill_tb(env->CP0_index & 0xF); |
|
| 534 |
/* Wildly undefined effects for CP0_index containing a too high value and |
|
| 535 |
MIPS_TLB_NB not being a power of two. But so does real silicon. */ |
|
| 536 |
invalidate_tb(env->CP0_index & (MIPS_TLB_NB - 1)); |
|
| 537 |
fill_tb(env->CP0_index & (MIPS_TLB_NB - 1)); |
|
| 536 | 538 |
} |
| 537 | 539 |
|
| 538 | 540 |
void do_tlbwr (void) |
| ... | ... | |
| 552 | 554 |
|
| 553 | 555 |
tag = (env->CP0_EntryHi & 0xFFFFE000); |
| 554 | 556 |
ASID = env->CP0_EntryHi & 0x000000FF; |
| 555 |
for (i = 0; i < 16; i++) {
|
|
| 557 |
for (i = 0; i < MIPS_TLB_NB; i++) {
|
|
| 556 | 558 |
tlb = &env->tlb[i]; |
| 557 | 559 |
/* Check ASID, virtual page number & size */ |
| 558 | 560 |
if ((tlb->G == 1 || tlb->ASID == ASID) && tlb->VPN == tag) {
|
| ... | ... | |
| 561 | 563 |
break; |
| 562 | 564 |
} |
| 563 | 565 |
} |
| 564 |
if (i == 16) {
|
|
| 566 |
if (i == MIPS_TLB_NB) {
|
|
| 565 | 567 |
env->CP0_index |= 0x80000000; |
| 566 | 568 |
} |
| 567 | 569 |
} |
| ... | ... | |
| 571 | 573 |
tlb_t *tlb; |
| 572 | 574 |
int size; |
| 573 | 575 |
|
| 574 |
tlb = &env->tlb[env->CP0_index & 0xF];
|
|
| 576 |
tlb = &env->tlb[env->CP0_index & (MIPS_TLB_NB - 1)];
|
|
| 575 | 577 |
env->CP0_EntryHi = tlb->VPN | tlb->ASID; |
| 576 | 578 |
size = (tlb->end - tlb->VPN) >> 12; |
| 577 | 579 |
env->CP0_PageMask = (size - 1) << 13; |
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