Revision 7a962d30 target-mips/op_helper.c
b/target-mips/op_helper.c | ||
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531 | 531 |
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void do_tlbwi (void) |
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{ |
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invalidate_tb(env->CP0_index & 0xF); |
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fill_tb(env->CP0_index & 0xF); |
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/* Wildly undefined effects for CP0_index containing a too high value and |
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MIPS_TLB_NB not being a power of two. But so does real silicon. */ |
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invalidate_tb(env->CP0_index & (MIPS_TLB_NB - 1)); |
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fill_tb(env->CP0_index & (MIPS_TLB_NB - 1)); |
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} |
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void do_tlbwr (void) |
... | ... | |
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tag = (env->CP0_EntryHi & 0xFFFFE000); |
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ASID = env->CP0_EntryHi & 0x000000FF; |
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for (i = 0; i < 16; i++) {
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for (i = 0; i < MIPS_TLB_NB; i++) {
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tlb = &env->tlb[i]; |
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/* Check ASID, virtual page number & size */ |
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if ((tlb->G == 1 || tlb->ASID == ASID) && tlb->VPN == tag) { |
... | ... | |
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break; |
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} |
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} |
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if (i == 16) {
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if (i == MIPS_TLB_NB) {
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env->CP0_index |= 0x80000000; |
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} |
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} |
... | ... | |
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tlb_t *tlb; |
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int size; |
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tlb = &env->tlb[env->CP0_index & 0xF];
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tlb = &env->tlb[env->CP0_index & (MIPS_TLB_NB - 1)];
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env->CP0_EntryHi = tlb->VPN | tlb->ASID; |
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size = (tlb->end - tlb->VPN) >> 12; |
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env->CP0_PageMask = (size - 1) << 13; |
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