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1 | 80cabfad | bellard | /*
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2 | 80cabfad | bellard | * QEMU 8253/8254 interval timer emulation
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3 | 5fafdf24 | ths | *
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4 | 80cabfad | bellard | * Copyright (c) 2003-2004 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 80cabfad | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 80cabfad | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 80cabfad | bellard | * in the Software without restriction, including without limitation the rights
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9 | 80cabfad | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 80cabfad | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 80cabfad | bellard | * furnished to do so, subject to the following conditions:
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12 | 80cabfad | bellard | *
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13 | 80cabfad | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 80cabfad | bellard | * all copies or substantial portions of the Software.
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15 | 80cabfad | bellard | *
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16 | 80cabfad | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 80cabfad | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 80cabfad | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 80cabfad | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 80cabfad | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 80cabfad | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 80cabfad | bellard | * THE SOFTWARE.
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23 | 80cabfad | bellard | */
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24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "pc.h" |
26 | 87ecb68b | pbrook | #include "isa.h" |
27 | 87ecb68b | pbrook | #include "qemu-timer.h" |
28 | 80cabfad | bellard | |
29 | b0a21b53 | bellard | //#define DEBUG_PIT
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30 | b0a21b53 | bellard | |
31 | ec844b96 | bellard | #define RW_STATE_LSB 1 |
32 | ec844b96 | bellard | #define RW_STATE_MSB 2 |
33 | ec844b96 | bellard | #define RW_STATE_WORD0 3 |
34 | ec844b96 | bellard | #define RW_STATE_WORD1 4 |
35 | 80cabfad | bellard | |
36 | ec844b96 | bellard | typedef struct PITChannelState { |
37 | ec844b96 | bellard | int count; /* can be 65536 */ |
38 | ec844b96 | bellard | uint16_t latched_count; |
39 | ec844b96 | bellard | uint8_t count_latched; |
40 | ec844b96 | bellard | uint8_t status_latched; |
41 | ec844b96 | bellard | uint8_t status; |
42 | ec844b96 | bellard | uint8_t read_state; |
43 | ec844b96 | bellard | uint8_t write_state; |
44 | ec844b96 | bellard | uint8_t write_latch; |
45 | ec844b96 | bellard | uint8_t rw_mode; |
46 | ec844b96 | bellard | uint8_t mode; |
47 | ec844b96 | bellard | uint8_t bcd; /* not supported */
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48 | ec844b96 | bellard | uint8_t gate; /* timer start */
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49 | ec844b96 | bellard | int64_t count_load_time; |
50 | ec844b96 | bellard | /* irq handling */
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51 | ec844b96 | bellard | int64_t next_transition_time; |
52 | ec844b96 | bellard | QEMUTimer *irq_timer; |
53 | d537cf6c | pbrook | qemu_irq irq; |
54 | ec844b96 | bellard | } PITChannelState; |
55 | ec844b96 | bellard | |
56 | 64d7e9a4 | Blue Swirl | typedef struct PITState { |
57 | 64d7e9a4 | Blue Swirl | ISADevice dev; |
58 | 64d7e9a4 | Blue Swirl | uint32_t irq; |
59 | 64d7e9a4 | Blue Swirl | uint32_t iobase; |
60 | ec844b96 | bellard | PITChannelState channels[3];
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61 | 64d7e9a4 | Blue Swirl | } PITState; |
62 | ec844b96 | bellard | |
63 | ec844b96 | bellard | static PITState pit_state;
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64 | 80cabfad | bellard | |
65 | b0a21b53 | bellard | static void pit_irq_timer_update(PITChannelState *s, int64_t current_time); |
66 | b0a21b53 | bellard | |
67 | 80cabfad | bellard | static int pit_get_count(PITChannelState *s) |
68 | 80cabfad | bellard | { |
69 | 80cabfad | bellard | uint64_t d; |
70 | 80cabfad | bellard | int counter;
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71 | 80cabfad | bellard | |
72 | 74475455 | Paolo Bonzini | d = muldiv64(qemu_get_clock_ns(vm_clock) - s->count_load_time, PIT_FREQ, |
73 | 6ee093c9 | Juan Quintela | get_ticks_per_sec()); |
74 | 80cabfad | bellard | switch(s->mode) {
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75 | 80cabfad | bellard | case 0: |
76 | 80cabfad | bellard | case 1: |
77 | 80cabfad | bellard | case 4: |
78 | 80cabfad | bellard | case 5: |
79 | 80cabfad | bellard | counter = (s->count - d) & 0xffff;
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80 | 80cabfad | bellard | break;
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81 | 80cabfad | bellard | case 3: |
82 | 80cabfad | bellard | /* XXX: may be incorrect for odd counts */
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83 | 80cabfad | bellard | counter = s->count - ((2 * d) % s->count);
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84 | 80cabfad | bellard | break;
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85 | 80cabfad | bellard | default:
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86 | 80cabfad | bellard | counter = s->count - (d % s->count); |
87 | 80cabfad | bellard | break;
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88 | 80cabfad | bellard | } |
89 | 80cabfad | bellard | return counter;
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90 | 80cabfad | bellard | } |
91 | 80cabfad | bellard | |
92 | 80cabfad | bellard | /* get pit output bit */
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93 | ec844b96 | bellard | static int pit_get_out1(PITChannelState *s, int64_t current_time) |
94 | 80cabfad | bellard | { |
95 | 80cabfad | bellard | uint64_t d; |
96 | 80cabfad | bellard | int out;
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97 | 80cabfad | bellard | |
98 | 6ee093c9 | Juan Quintela | d = muldiv64(current_time - s->count_load_time, PIT_FREQ, |
99 | 6ee093c9 | Juan Quintela | get_ticks_per_sec()); |
100 | 80cabfad | bellard | switch(s->mode) {
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101 | 80cabfad | bellard | default:
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102 | 80cabfad | bellard | case 0: |
103 | 80cabfad | bellard | out = (d >= s->count); |
104 | 80cabfad | bellard | break;
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105 | 80cabfad | bellard | case 1: |
106 | 80cabfad | bellard | out = (d < s->count); |
107 | 80cabfad | bellard | break;
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108 | 80cabfad | bellard | case 2: |
109 | 80cabfad | bellard | if ((d % s->count) == 0 && d != 0) |
110 | 80cabfad | bellard | out = 1;
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111 | 80cabfad | bellard | else
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112 | 80cabfad | bellard | out = 0;
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113 | 80cabfad | bellard | break;
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114 | 80cabfad | bellard | case 3: |
115 | 80cabfad | bellard | out = (d % s->count) < ((s->count + 1) >> 1); |
116 | 80cabfad | bellard | break;
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117 | 80cabfad | bellard | case 4: |
118 | 80cabfad | bellard | case 5: |
119 | 80cabfad | bellard | out = (d == s->count); |
120 | 80cabfad | bellard | break;
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121 | 80cabfad | bellard | } |
122 | 80cabfad | bellard | return out;
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123 | 80cabfad | bellard | } |
124 | 80cabfad | bellard | |
125 | 64d7e9a4 | Blue Swirl | int pit_get_out(ISADevice *dev, int channel, int64_t current_time) |
126 | ec844b96 | bellard | { |
127 | 64d7e9a4 | Blue Swirl | PITState *pit = DO_UPCAST(PITState, dev, dev); |
128 | ec844b96 | bellard | PITChannelState *s = &pit->channels[channel]; |
129 | ec844b96 | bellard | return pit_get_out1(s, current_time);
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130 | ec844b96 | bellard | } |
131 | ec844b96 | bellard | |
132 | b0a21b53 | bellard | /* return -1 if no transition will occur. */
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133 | 5fafdf24 | ths | static int64_t pit_get_next_transition_time(PITChannelState *s,
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134 | b0a21b53 | bellard | int64_t current_time) |
135 | 80cabfad | bellard | { |
136 | b0a21b53 | bellard | uint64_t d, next_time, base; |
137 | b0a21b53 | bellard | int period2;
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138 | 80cabfad | bellard | |
139 | 6ee093c9 | Juan Quintela | d = muldiv64(current_time - s->count_load_time, PIT_FREQ, |
140 | 6ee093c9 | Juan Quintela | get_ticks_per_sec()); |
141 | 80cabfad | bellard | switch(s->mode) {
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142 | 80cabfad | bellard | default:
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143 | 80cabfad | bellard | case 0: |
144 | 80cabfad | bellard | case 1: |
145 | b0a21b53 | bellard | if (d < s->count)
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146 | b0a21b53 | bellard | next_time = s->count; |
147 | b0a21b53 | bellard | else
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148 | b0a21b53 | bellard | return -1; |
149 | 80cabfad | bellard | break;
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150 | 80cabfad | bellard | case 2: |
151 | b0a21b53 | bellard | base = (d / s->count) * s->count; |
152 | b0a21b53 | bellard | if ((d - base) == 0 && d != 0) |
153 | b0a21b53 | bellard | next_time = base + s->count; |
154 | b0a21b53 | bellard | else
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155 | b0a21b53 | bellard | next_time = base + s->count + 1;
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156 | 80cabfad | bellard | break;
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157 | 80cabfad | bellard | case 3: |
158 | b0a21b53 | bellard | base = (d / s->count) * s->count; |
159 | b0a21b53 | bellard | period2 = ((s->count + 1) >> 1); |
160 | 5fafdf24 | ths | if ((d - base) < period2)
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161 | b0a21b53 | bellard | next_time = base + period2; |
162 | b0a21b53 | bellard | else
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163 | b0a21b53 | bellard | next_time = base + s->count; |
164 | 80cabfad | bellard | break;
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165 | 80cabfad | bellard | case 4: |
166 | 80cabfad | bellard | case 5: |
167 | b0a21b53 | bellard | if (d < s->count)
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168 | b0a21b53 | bellard | next_time = s->count; |
169 | b0a21b53 | bellard | else if (d == s->count) |
170 | b0a21b53 | bellard | next_time = s->count + 1;
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171 | 80cabfad | bellard | else
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172 | b0a21b53 | bellard | return -1; |
173 | 80cabfad | bellard | break;
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174 | 80cabfad | bellard | } |
175 | b0a21b53 | bellard | /* convert to timer units */
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176 | 6ee093c9 | Juan Quintela | next_time = s->count_load_time + muldiv64(next_time, get_ticks_per_sec(), |
177 | 6ee093c9 | Juan Quintela | PIT_FREQ); |
178 | 1154e441 | bellard | /* fix potential rounding problems */
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179 | 1154e441 | bellard | /* XXX: better solution: use a clock at PIT_FREQ Hz */
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180 | 1154e441 | bellard | if (next_time <= current_time)
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181 | 1154e441 | bellard | next_time = current_time + 1;
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182 | b0a21b53 | bellard | return next_time;
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183 | 80cabfad | bellard | } |
184 | 80cabfad | bellard | |
185 | 80cabfad | bellard | /* val must be 0 or 1 */
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186 | 64d7e9a4 | Blue Swirl | void pit_set_gate(ISADevice *dev, int channel, int val) |
187 | 80cabfad | bellard | { |
188 | 64d7e9a4 | Blue Swirl | PITState *pit = DO_UPCAST(PITState, dev, dev); |
189 | ec844b96 | bellard | PITChannelState *s = &pit->channels[channel]; |
190 | ec844b96 | bellard | |
191 | 80cabfad | bellard | switch(s->mode) {
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192 | 80cabfad | bellard | default:
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193 | 80cabfad | bellard | case 0: |
194 | 80cabfad | bellard | case 4: |
195 | 80cabfad | bellard | /* XXX: just disable/enable counting */
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196 | 80cabfad | bellard | break;
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197 | 80cabfad | bellard | case 1: |
198 | 80cabfad | bellard | case 5: |
199 | 80cabfad | bellard | if (s->gate < val) {
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200 | 80cabfad | bellard | /* restart counting on rising edge */
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201 | 74475455 | Paolo Bonzini | s->count_load_time = qemu_get_clock_ns(vm_clock); |
202 | b0a21b53 | bellard | pit_irq_timer_update(s, s->count_load_time); |
203 | 80cabfad | bellard | } |
204 | 80cabfad | bellard | break;
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205 | 80cabfad | bellard | case 2: |
206 | 80cabfad | bellard | case 3: |
207 | 80cabfad | bellard | if (s->gate < val) {
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208 | 80cabfad | bellard | /* restart counting on rising edge */
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209 | 74475455 | Paolo Bonzini | s->count_load_time = qemu_get_clock_ns(vm_clock); |
210 | b0a21b53 | bellard | pit_irq_timer_update(s, s->count_load_time); |
211 | 80cabfad | bellard | } |
212 | 80cabfad | bellard | /* XXX: disable/enable counting */
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213 | 80cabfad | bellard | break;
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214 | 80cabfad | bellard | } |
215 | 80cabfad | bellard | s->gate = val; |
216 | 80cabfad | bellard | } |
217 | 80cabfad | bellard | |
218 | 64d7e9a4 | Blue Swirl | int pit_get_gate(ISADevice *dev, int channel) |
219 | ec844b96 | bellard | { |
220 | 64d7e9a4 | Blue Swirl | PITState *pit = DO_UPCAST(PITState, dev, dev); |
221 | ec844b96 | bellard | PITChannelState *s = &pit->channels[channel]; |
222 | ec844b96 | bellard | return s->gate;
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223 | ec844b96 | bellard | } |
224 | ec844b96 | bellard | |
225 | 64d7e9a4 | Blue Swirl | int pit_get_initial_count(ISADevice *dev, int channel) |
226 | fd06c375 | bellard | { |
227 | 64d7e9a4 | Blue Swirl | PITState *pit = DO_UPCAST(PITState, dev, dev); |
228 | fd06c375 | bellard | PITChannelState *s = &pit->channels[channel]; |
229 | fd06c375 | bellard | return s->count;
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230 | fd06c375 | bellard | } |
231 | fd06c375 | bellard | |
232 | 64d7e9a4 | Blue Swirl | int pit_get_mode(ISADevice *dev, int channel) |
233 | fd06c375 | bellard | { |
234 | 64d7e9a4 | Blue Swirl | PITState *pit = DO_UPCAST(PITState, dev, dev); |
235 | fd06c375 | bellard | PITChannelState *s = &pit->channels[channel]; |
236 | fd06c375 | bellard | return s->mode;
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237 | fd06c375 | bellard | } |
238 | fd06c375 | bellard | |
239 | 80cabfad | bellard | static inline void pit_load_count(PITChannelState *s, int val) |
240 | 80cabfad | bellard | { |
241 | 80cabfad | bellard | if (val == 0) |
242 | 80cabfad | bellard | val = 0x10000;
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243 | 74475455 | Paolo Bonzini | s->count_load_time = qemu_get_clock_ns(vm_clock); |
244 | 80cabfad | bellard | s->count = val; |
245 | b0a21b53 | bellard | pit_irq_timer_update(s, s->count_load_time); |
246 | 80cabfad | bellard | } |
247 | 80cabfad | bellard | |
248 | ec844b96 | bellard | /* if already latched, do not latch again */
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249 | ec844b96 | bellard | static void pit_latch_count(PITChannelState *s) |
250 | ec844b96 | bellard | { |
251 | ec844b96 | bellard | if (!s->count_latched) {
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252 | ec844b96 | bellard | s->latched_count = pit_get_count(s); |
253 | ec844b96 | bellard | s->count_latched = s->rw_mode; |
254 | ec844b96 | bellard | } |
255 | ec844b96 | bellard | } |
256 | ec844b96 | bellard | |
257 | b41a2cd1 | bellard | static void pit_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
258 | 80cabfad | bellard | { |
259 | ec844b96 | bellard | PITState *pit = opaque; |
260 | 80cabfad | bellard | int channel, access;
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261 | 80cabfad | bellard | PITChannelState *s; |
262 | 80cabfad | bellard | |
263 | 80cabfad | bellard | addr &= 3;
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264 | 80cabfad | bellard | if (addr == 3) { |
265 | 80cabfad | bellard | channel = val >> 6;
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266 | ec844b96 | bellard | if (channel == 3) { |
267 | ec844b96 | bellard | /* read back command */
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268 | ec844b96 | bellard | for(channel = 0; channel < 3; channel++) { |
269 | ec844b96 | bellard | s = &pit->channels[channel]; |
270 | ec844b96 | bellard | if (val & (2 << channel)) { |
271 | ec844b96 | bellard | if (!(val & 0x20)) { |
272 | ec844b96 | bellard | pit_latch_count(s); |
273 | ec844b96 | bellard | } |
274 | ec844b96 | bellard | if (!(val & 0x10) && !s->status_latched) { |
275 | ec844b96 | bellard | /* status latch */
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276 | ec844b96 | bellard | /* XXX: add BCD and null count */
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277 | 74475455 | Paolo Bonzini | s->status = (pit_get_out1(s, qemu_get_clock_ns(vm_clock)) << 7) |
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278 | ec844b96 | bellard | (s->rw_mode << 4) |
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279 | ec844b96 | bellard | (s->mode << 1) |
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280 | ec844b96 | bellard | s->bcd; |
281 | ec844b96 | bellard | s->status_latched = 1;
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282 | ec844b96 | bellard | } |
283 | ec844b96 | bellard | } |
284 | ec844b96 | bellard | } |
285 | ec844b96 | bellard | } else {
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286 | ec844b96 | bellard | s = &pit->channels[channel]; |
287 | ec844b96 | bellard | access = (val >> 4) & 3; |
288 | ec844b96 | bellard | if (access == 0) { |
289 | ec844b96 | bellard | pit_latch_count(s); |
290 | ec844b96 | bellard | } else {
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291 | ec844b96 | bellard | s->rw_mode = access; |
292 | ec844b96 | bellard | s->read_state = access; |
293 | ec844b96 | bellard | s->write_state = access; |
294 | ec844b96 | bellard | |
295 | ec844b96 | bellard | s->mode = (val >> 1) & 7; |
296 | ec844b96 | bellard | s->bcd = val & 1;
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297 | ec844b96 | bellard | /* XXX: update irq timer ? */
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298 | ec844b96 | bellard | } |
299 | 80cabfad | bellard | } |
300 | 80cabfad | bellard | } else {
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301 | ec844b96 | bellard | s = &pit->channels[addr]; |
302 | ec844b96 | bellard | switch(s->write_state) {
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303 | ec844b96 | bellard | default:
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304 | 80cabfad | bellard | case RW_STATE_LSB:
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305 | 80cabfad | bellard | pit_load_count(s, val); |
306 | 80cabfad | bellard | break;
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307 | 80cabfad | bellard | case RW_STATE_MSB:
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308 | 80cabfad | bellard | pit_load_count(s, val << 8);
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309 | 80cabfad | bellard | break;
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310 | 80cabfad | bellard | case RW_STATE_WORD0:
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311 | ec844b96 | bellard | s->write_latch = val; |
312 | ec844b96 | bellard | s->write_state = RW_STATE_WORD1; |
313 | ec844b96 | bellard | break;
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314 | 80cabfad | bellard | case RW_STATE_WORD1:
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315 | ec844b96 | bellard | pit_load_count(s, s->write_latch | (val << 8));
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316 | ec844b96 | bellard | s->write_state = RW_STATE_WORD0; |
317 | 80cabfad | bellard | break;
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318 | 80cabfad | bellard | } |
319 | 80cabfad | bellard | } |
320 | 80cabfad | bellard | } |
321 | 80cabfad | bellard | |
322 | b41a2cd1 | bellard | static uint32_t pit_ioport_read(void *opaque, uint32_t addr) |
323 | 80cabfad | bellard | { |
324 | ec844b96 | bellard | PITState *pit = opaque; |
325 | 80cabfad | bellard | int ret, count;
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326 | 80cabfad | bellard | PITChannelState *s; |
327 | 3b46e624 | ths | |
328 | 80cabfad | bellard | addr &= 3;
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329 | ec844b96 | bellard | s = &pit->channels[addr]; |
330 | ec844b96 | bellard | if (s->status_latched) {
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331 | ec844b96 | bellard | s->status_latched = 0;
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332 | ec844b96 | bellard | ret = s->status; |
333 | ec844b96 | bellard | } else if (s->count_latched) { |
334 | ec844b96 | bellard | switch(s->count_latched) {
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335 | ec844b96 | bellard | default:
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336 | ec844b96 | bellard | case RW_STATE_LSB:
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337 | ec844b96 | bellard | ret = s->latched_count & 0xff;
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338 | ec844b96 | bellard | s->count_latched = 0;
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339 | ec844b96 | bellard | break;
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340 | ec844b96 | bellard | case RW_STATE_MSB:
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341 | 80cabfad | bellard | ret = s->latched_count >> 8;
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342 | ec844b96 | bellard | s->count_latched = 0;
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343 | ec844b96 | bellard | break;
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344 | ec844b96 | bellard | case RW_STATE_WORD0:
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345 | 80cabfad | bellard | ret = s->latched_count & 0xff;
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346 | ec844b96 | bellard | s->count_latched = RW_STATE_MSB; |
347 | ec844b96 | bellard | break;
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348 | ec844b96 | bellard | } |
349 | ec844b96 | bellard | } else {
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350 | ec844b96 | bellard | switch(s->read_state) {
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351 | ec844b96 | bellard | default:
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352 | ec844b96 | bellard | case RW_STATE_LSB:
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353 | ec844b96 | bellard | count = pit_get_count(s); |
354 | ec844b96 | bellard | ret = count & 0xff;
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355 | ec844b96 | bellard | break;
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356 | ec844b96 | bellard | case RW_STATE_MSB:
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357 | ec844b96 | bellard | count = pit_get_count(s); |
358 | ec844b96 | bellard | ret = (count >> 8) & 0xff; |
359 | ec844b96 | bellard | break;
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360 | ec844b96 | bellard | case RW_STATE_WORD0:
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361 | ec844b96 | bellard | count = pit_get_count(s); |
362 | ec844b96 | bellard | ret = count & 0xff;
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363 | ec844b96 | bellard | s->read_state = RW_STATE_WORD1; |
364 | ec844b96 | bellard | break;
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365 | ec844b96 | bellard | case RW_STATE_WORD1:
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366 | ec844b96 | bellard | count = pit_get_count(s); |
367 | ec844b96 | bellard | ret = (count >> 8) & 0xff; |
368 | ec844b96 | bellard | s->read_state = RW_STATE_WORD0; |
369 | ec844b96 | bellard | break;
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370 | ec844b96 | bellard | } |
371 | 80cabfad | bellard | } |
372 | 80cabfad | bellard | return ret;
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373 | 80cabfad | bellard | } |
374 | 80cabfad | bellard | |
375 | b0a21b53 | bellard | static void pit_irq_timer_update(PITChannelState *s, int64_t current_time) |
376 | b0a21b53 | bellard | { |
377 | b0a21b53 | bellard | int64_t expire_time; |
378 | b0a21b53 | bellard | int irq_level;
|
379 | b0a21b53 | bellard | |
380 | b0a21b53 | bellard | if (!s->irq_timer)
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381 | b0a21b53 | bellard | return;
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382 | b0a21b53 | bellard | expire_time = pit_get_next_transition_time(s, current_time); |
383 | ec844b96 | bellard | irq_level = pit_get_out1(s, current_time); |
384 | d537cf6c | pbrook | qemu_set_irq(s->irq, irq_level); |
385 | b0a21b53 | bellard | #ifdef DEBUG_PIT
|
386 | b0a21b53 | bellard | printf("irq_level=%d next_delay=%f\n",
|
387 | 5fafdf24 | ths | irq_level, |
388 | 6ee093c9 | Juan Quintela | (double)(expire_time - current_time) / get_ticks_per_sec());
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389 | b0a21b53 | bellard | #endif
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390 | b0a21b53 | bellard | s->next_transition_time = expire_time; |
391 | b0a21b53 | bellard | if (expire_time != -1) |
392 | b0a21b53 | bellard | qemu_mod_timer(s->irq_timer, expire_time); |
393 | b0a21b53 | bellard | else
|
394 | b0a21b53 | bellard | qemu_del_timer(s->irq_timer); |
395 | b0a21b53 | bellard | } |
396 | b0a21b53 | bellard | |
397 | b0a21b53 | bellard | static void pit_irq_timer(void *opaque) |
398 | b0a21b53 | bellard | { |
399 | b0a21b53 | bellard | PITChannelState *s = opaque; |
400 | b0a21b53 | bellard | |
401 | b0a21b53 | bellard | pit_irq_timer_update(s, s->next_transition_time); |
402 | b0a21b53 | bellard | } |
403 | b0a21b53 | bellard | |
404 | 5122b431 | Juan Quintela | static const VMStateDescription vmstate_pit_channel = { |
405 | 5122b431 | Juan Quintela | .name = "pit channel",
|
406 | 5122b431 | Juan Quintela | .version_id = 2,
|
407 | 5122b431 | Juan Quintela | .minimum_version_id = 2,
|
408 | 5122b431 | Juan Quintela | .minimum_version_id_old = 2,
|
409 | 5122b431 | Juan Quintela | .fields = (VMStateField []) { |
410 | 5122b431 | Juan Quintela | VMSTATE_INT32(count, PITChannelState), |
411 | 5122b431 | Juan Quintela | VMSTATE_UINT16(latched_count, PITChannelState), |
412 | 5122b431 | Juan Quintela | VMSTATE_UINT8(count_latched, PITChannelState), |
413 | 5122b431 | Juan Quintela | VMSTATE_UINT8(status_latched, PITChannelState), |
414 | 5122b431 | Juan Quintela | VMSTATE_UINT8(status, PITChannelState), |
415 | 5122b431 | Juan Quintela | VMSTATE_UINT8(read_state, PITChannelState), |
416 | 5122b431 | Juan Quintela | VMSTATE_UINT8(write_state, PITChannelState), |
417 | 5122b431 | Juan Quintela | VMSTATE_UINT8(write_latch, PITChannelState), |
418 | 5122b431 | Juan Quintela | VMSTATE_UINT8(rw_mode, PITChannelState), |
419 | 5122b431 | Juan Quintela | VMSTATE_UINT8(mode, PITChannelState), |
420 | 5122b431 | Juan Quintela | VMSTATE_UINT8(bcd, PITChannelState), |
421 | 5122b431 | Juan Quintela | VMSTATE_UINT8(gate, PITChannelState), |
422 | 5122b431 | Juan Quintela | VMSTATE_INT64(count_load_time, PITChannelState), |
423 | 5122b431 | Juan Quintela | VMSTATE_INT64(next_transition_time, PITChannelState), |
424 | 5122b431 | Juan Quintela | VMSTATE_END_OF_LIST() |
425 | b0a21b53 | bellard | } |
426 | 5122b431 | Juan Quintela | }; |
427 | b0a21b53 | bellard | |
428 | 5122b431 | Juan Quintela | static int pit_load_old(QEMUFile *f, void *opaque, int version_id) |
429 | b0a21b53 | bellard | { |
430 | ec844b96 | bellard | PITState *pit = opaque; |
431 | b0a21b53 | bellard | PITChannelState *s; |
432 | b0a21b53 | bellard | int i;
|
433 | 3b46e624 | ths | |
434 | b0a21b53 | bellard | if (version_id != 1) |
435 | b0a21b53 | bellard | return -EINVAL;
|
436 | b0a21b53 | bellard | |
437 | b0a21b53 | bellard | for(i = 0; i < 3; i++) { |
438 | ec844b96 | bellard | s = &pit->channels[i]; |
439 | bee8d684 | ths | s->count=qemu_get_be32(f); |
440 | b0a21b53 | bellard | qemu_get_be16s(f, &s->latched_count); |
441 | ec844b96 | bellard | qemu_get_8s(f, &s->count_latched); |
442 | ec844b96 | bellard | qemu_get_8s(f, &s->status_latched); |
443 | ec844b96 | bellard | qemu_get_8s(f, &s->status); |
444 | ec844b96 | bellard | qemu_get_8s(f, &s->read_state); |
445 | ec844b96 | bellard | qemu_get_8s(f, &s->write_state); |
446 | ec844b96 | bellard | qemu_get_8s(f, &s->write_latch); |
447 | ec844b96 | bellard | qemu_get_8s(f, &s->rw_mode); |
448 | b0a21b53 | bellard | qemu_get_8s(f, &s->mode); |
449 | b0a21b53 | bellard | qemu_get_8s(f, &s->bcd); |
450 | b0a21b53 | bellard | qemu_get_8s(f, &s->gate); |
451 | bee8d684 | ths | s->count_load_time=qemu_get_be64(f); |
452 | b0a21b53 | bellard | if (s->irq_timer) {
|
453 | bee8d684 | ths | s->next_transition_time=qemu_get_be64(f); |
454 | b0a21b53 | bellard | qemu_get_timer(f, s->irq_timer); |
455 | b0a21b53 | bellard | } |
456 | b0a21b53 | bellard | } |
457 | b0a21b53 | bellard | return 0; |
458 | b0a21b53 | bellard | } |
459 | b0a21b53 | bellard | |
460 | 5122b431 | Juan Quintela | static const VMStateDescription vmstate_pit = { |
461 | 5122b431 | Juan Quintela | .name = "i8254",
|
462 | 5122b431 | Juan Quintela | .version_id = 2,
|
463 | 5122b431 | Juan Quintela | .minimum_version_id = 2,
|
464 | 5122b431 | Juan Quintela | .minimum_version_id_old = 1,
|
465 | 5122b431 | Juan Quintela | .load_state_old = pit_load_old, |
466 | 5122b431 | Juan Quintela | .fields = (VMStateField []) { |
467 | 5122b431 | Juan Quintela | VMSTATE_STRUCT_ARRAY(channels, PITState, 3, 2, vmstate_pit_channel, PITChannelState), |
468 | 5122b431 | Juan Quintela | VMSTATE_TIMER(channels[0].irq_timer, PITState),
|
469 | 5122b431 | Juan Quintela | VMSTATE_END_OF_LIST() |
470 | 5122b431 | Juan Quintela | } |
471 | 5122b431 | Juan Quintela | }; |
472 | 5122b431 | Juan Quintela | |
473 | 64d7e9a4 | Blue Swirl | static void pit_reset(DeviceState *dev) |
474 | 80cabfad | bellard | { |
475 | 64d7e9a4 | Blue Swirl | PITState *pit = container_of(dev, PITState, dev.qdev); |
476 | 80cabfad | bellard | PITChannelState *s; |
477 | 80cabfad | bellard | int i;
|
478 | 80cabfad | bellard | |
479 | 80cabfad | bellard | for(i = 0;i < 3; i++) { |
480 | ec844b96 | bellard | s = &pit->channels[i]; |
481 | 80cabfad | bellard | s->mode = 3;
|
482 | 80cabfad | bellard | s->gate = (i != 2);
|
483 | 80cabfad | bellard | pit_load_count(s, 0);
|
484 | 80cabfad | bellard | } |
485 | d7d02e3c | bellard | } |
486 | d7d02e3c | bellard | |
487 | 16b29ae1 | aliguori | /* When HPET is operating in legacy mode, i8254 timer0 is disabled */
|
488 | 16b29ae1 | aliguori | void hpet_pit_disable(void) { |
489 | 16b29ae1 | aliguori | PITChannelState *s; |
490 | 16b29ae1 | aliguori | s = &pit_state.channels[0];
|
491 | e0dd114c | aliguori | if (s->irq_timer)
|
492 | e0dd114c | aliguori | qemu_del_timer(s->irq_timer); |
493 | 16b29ae1 | aliguori | } |
494 | 16b29ae1 | aliguori | |
495 | c50c2d68 | aurel32 | /* When HPET is reset or leaving legacy mode, it must reenable i8254
|
496 | 16b29ae1 | aliguori | * timer 0
|
497 | 16b29ae1 | aliguori | */
|
498 | 16b29ae1 | aliguori | |
499 | 16b29ae1 | aliguori | void hpet_pit_enable(void) |
500 | 16b29ae1 | aliguori | { |
501 | 16b29ae1 | aliguori | PITState *pit = &pit_state; |
502 | 16b29ae1 | aliguori | PITChannelState *s; |
503 | 16b29ae1 | aliguori | s = &pit->channels[0];
|
504 | 16b29ae1 | aliguori | s->mode = 3;
|
505 | 16b29ae1 | aliguori | s->gate = 1;
|
506 | 16b29ae1 | aliguori | pit_load_count(s, 0);
|
507 | 16b29ae1 | aliguori | } |
508 | 16b29ae1 | aliguori | |
509 | 64d7e9a4 | Blue Swirl | static int pit_initfn(ISADevice *dev) |
510 | d7d02e3c | bellard | { |
511 | 64d7e9a4 | Blue Swirl | PITState *pit = DO_UPCAST(PITState, dev, dev); |
512 | d7d02e3c | bellard | PITChannelState *s; |
513 | d7d02e3c | bellard | |
514 | d7d02e3c | bellard | s = &pit->channels[0];
|
515 | d7d02e3c | bellard | /* the timer 0 is connected to an IRQ */
|
516 | 74475455 | Paolo Bonzini | s->irq_timer = qemu_new_timer_ns(vm_clock, pit_irq_timer, s); |
517 | ee951a37 | Jan Kiszka | s->irq = isa_get_irq(pit->irq); |
518 | 80cabfad | bellard | |
519 | 64d7e9a4 | Blue Swirl | register_ioport_write(pit->iobase, 4, 1, pit_ioport_write, pit); |
520 | 64d7e9a4 | Blue Swirl | register_ioport_read(pit->iobase, 3, 1, pit_ioport_read, pit); |
521 | 64d7e9a4 | Blue Swirl | isa_init_ioport(dev, pit->iobase); |
522 | d7d02e3c | bellard | |
523 | ca22a3a3 | Jan Kiszka | qdev_set_legacy_instance_id(&dev->qdev, pit->iobase, 2);
|
524 | ca22a3a3 | Jan Kiszka | |
525 | 64d7e9a4 | Blue Swirl | return 0; |
526 | 64d7e9a4 | Blue Swirl | } |
527 | 64d7e9a4 | Blue Swirl | |
528 | 64d7e9a4 | Blue Swirl | static ISADeviceInfo pit_info = {
|
529 | 64d7e9a4 | Blue Swirl | .qdev.name = "isa-pit",
|
530 | 64d7e9a4 | Blue Swirl | .qdev.size = sizeof(PITState),
|
531 | 64d7e9a4 | Blue Swirl | .qdev.vmsd = &vmstate_pit, |
532 | 64d7e9a4 | Blue Swirl | .qdev.reset = pit_reset, |
533 | 64d7e9a4 | Blue Swirl | .qdev.no_user = 1,
|
534 | 64d7e9a4 | Blue Swirl | .init = pit_initfn, |
535 | 64d7e9a4 | Blue Swirl | .qdev.props = (Property[]) { |
536 | 64d7e9a4 | Blue Swirl | DEFINE_PROP_UINT32("irq", PITState, irq, -1), |
537 | 64d7e9a4 | Blue Swirl | DEFINE_PROP_HEX32("iobase", PITState, iobase, -1), |
538 | 64d7e9a4 | Blue Swirl | DEFINE_PROP_END_OF_LIST(), |
539 | 64d7e9a4 | Blue Swirl | }, |
540 | 64d7e9a4 | Blue Swirl | }; |
541 | 64d7e9a4 | Blue Swirl | |
542 | 64d7e9a4 | Blue Swirl | static void pit_register(void) |
543 | 64d7e9a4 | Blue Swirl | { |
544 | 64d7e9a4 | Blue Swirl | isa_qdev_register(&pit_info); |
545 | 80cabfad | bellard | } |
546 | 64d7e9a4 | Blue Swirl | device_init(pit_register) |