Revision 7b169687 hw/iommu.c
| b/hw/iommu.c | ||
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| 78 | 78 |
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| 79 | 79 |
#define IOMMU_AFAR (0x1004 >> 2) |
| 80 | 80 |
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#define IOMMU_AER (0x1008 >> 2) /* Arbiter Enable Register */ |
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#define IOMMU_AER_EN_P0_ARB 0x00000001 /* MBus master 0x8 (Always 1) */ |
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#define IOMMU_AER_EN_P1_ARB 0x00000002 /* MBus master 0x9 */ |
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#define IOMMU_AER_EN_P2_ARB 0x00000004 /* MBus master 0xa */ |
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#define IOMMU_AER_EN_P3_ARB 0x00000008 /* MBus master 0xb */ |
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#define IOMMU_AER_EN_0 0x00010000 /* SBus slot 0 */ |
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#define IOMMU_AER_EN_1 0x00020000 /* SBus slot 1 */ |
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#define IOMMU_AER_EN_2 0x00040000 /* SBus slot 2 */ |
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#define IOMMU_AER_EN_3 0x00080000 /* SBus slot 3 */ |
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#define IOMMU_AER_EN_F 0x00100000 /* SBus on-board */ |
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#define IOMMU_AER_SBW 0x80000000 /* S-to-M asynchronous writes */ |
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#define IOMMU_AER_MASK 0x801f000f |
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#define IOMMU_SBCFG0 (0x1010 >> 2) /* SBUS configration per-slot */ |
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#define IOMMU_SBCFG1 (0x1014 >> 2) /* SBUS configration per-slot */ |
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#define IOMMU_SBCFG2 (0x1018 >> 2) /* SBUS configration per-slot */ |
| ... | ... | |
| 196 | 209 |
s->regs[saddr] = val; |
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qemu_irq_lower(s->irq); |
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break; |
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case IOMMU_AER: |
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s->regs[saddr] = (val & IOMMU_AER_MASK) | IOMMU_AER_EN_P0_ARB; |
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break; |
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case IOMMU_AFSR: |
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s->regs[saddr] = (val & IOMMU_AFSR_MASK) | IOMMU_AFSR_RESV; |
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qemu_irq_lower(s->irq); |
| ... | ... | |
| 344 | 360 |
s->regs[IOMMU_CTRL] = s->version; |
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s->regs[IOMMU_ARBEN] = IOMMU_MID; |
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s->regs[IOMMU_AFSR] = IOMMU_AFSR_RESV; |
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s->regs[IOMMU_AER] = IOMMU_AER_EN_P0_ARB | IOMMU_AER_EN_P1_ARB; |
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| 347 | 364 |
s->regs[IOMMU_MASK_ID] = IOMMU_TS_MASK; |
| 348 | 365 |
qemu_irq_lower(s->irq); |
| 349 | 366 |
} |
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