root / hw / vga_int.h @ 7b17d41e
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1 | 798b0c25 | bellard | /*
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2 | 798b0c25 | bellard | * QEMU internal VGA defines.
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3 | 798b0c25 | bellard | *
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4 | 798b0c25 | bellard | * Copyright (c) 2003-2004 Fabrice Bellard
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5 | 798b0c25 | bellard | *
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6 | 798b0c25 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 798b0c25 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 798b0c25 | bellard | * in the Software without restriction, including without limitation the rights
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9 | 798b0c25 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 798b0c25 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 798b0c25 | bellard | * furnished to do so, subject to the following conditions:
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12 | 798b0c25 | bellard | *
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13 | 798b0c25 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 798b0c25 | bellard | * all copies or substantial portions of the Software.
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15 | 798b0c25 | bellard | *
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16 | 798b0c25 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 798b0c25 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 798b0c25 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 798b0c25 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 798b0c25 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 798b0c25 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 798b0c25 | bellard | * THE SOFTWARE.
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23 | 798b0c25 | bellard | */
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24 | 798b0c25 | bellard | #define MSR_COLOR_EMULATION 0x01 |
25 | 798b0c25 | bellard | #define MSR_PAGE_SELECT 0x20 |
26 | 798b0c25 | bellard | |
27 | 798b0c25 | bellard | #define ST01_V_RETRACE 0x08 |
28 | 798b0c25 | bellard | #define ST01_DISP_ENABLE 0x01 |
29 | 798b0c25 | bellard | |
30 | 798b0c25 | bellard | /* bochs VBE support */
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31 | 798b0c25 | bellard | #define CONFIG_BOCHS_VBE
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32 | 798b0c25 | bellard | |
33 | 798b0c25 | bellard | #define VBE_DISPI_MAX_XRES 1024 |
34 | 798b0c25 | bellard | #define VBE_DISPI_MAX_YRES 768 |
35 | 798b0c25 | bellard | |
36 | 798b0c25 | bellard | #define VBE_DISPI_INDEX_ID 0x0 |
37 | 798b0c25 | bellard | #define VBE_DISPI_INDEX_XRES 0x1 |
38 | 798b0c25 | bellard | #define VBE_DISPI_INDEX_YRES 0x2 |
39 | 798b0c25 | bellard | #define VBE_DISPI_INDEX_BPP 0x3 |
40 | 798b0c25 | bellard | #define VBE_DISPI_INDEX_ENABLE 0x4 |
41 | 798b0c25 | bellard | #define VBE_DISPI_INDEX_BANK 0x5 |
42 | 798b0c25 | bellard | #define VBE_DISPI_INDEX_VIRT_WIDTH 0x6 |
43 | 798b0c25 | bellard | #define VBE_DISPI_INDEX_VIRT_HEIGHT 0x7 |
44 | 798b0c25 | bellard | #define VBE_DISPI_INDEX_X_OFFSET 0x8 |
45 | 798b0c25 | bellard | #define VBE_DISPI_INDEX_Y_OFFSET 0x9 |
46 | 798b0c25 | bellard | #define VBE_DISPI_INDEX_NB 0xa |
47 | 798b0c25 | bellard | |
48 | 798b0c25 | bellard | #define VBE_DISPI_ID0 0xB0C0 |
49 | 798b0c25 | bellard | #define VBE_DISPI_ID1 0xB0C1 |
50 | 798b0c25 | bellard | #define VBE_DISPI_ID2 0xB0C2 |
51 | 798b0c25 | bellard | |
52 | 798b0c25 | bellard | #define VBE_DISPI_DISABLED 0x00 |
53 | 798b0c25 | bellard | #define VBE_DISPI_ENABLED 0x01 |
54 | 798b0c25 | bellard | #define VBE_DISPI_LFB_ENABLED 0x40 |
55 | 798b0c25 | bellard | #define VBE_DISPI_NOCLEARMEM 0x80 |
56 | 798b0c25 | bellard | |
57 | 798b0c25 | bellard | #define VBE_DISPI_LFB_PHYSICAL_ADDRESS 0xE0000000 |
58 | 798b0c25 | bellard | |
59 | 798b0c25 | bellard | typedef struct VGAState { |
60 | 798b0c25 | bellard | uint8_t *vram_ptr; |
61 | 798b0c25 | bellard | unsigned long vram_offset; |
62 | 798b0c25 | bellard | unsigned int vram_size; |
63 | 798b0c25 | bellard | uint32_t latch; |
64 | 798b0c25 | bellard | uint8_t sr_index; |
65 | 798b0c25 | bellard | uint8_t sr[256];
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66 | 798b0c25 | bellard | uint8_t gr_index; |
67 | 798b0c25 | bellard | uint8_t gr[256];
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68 | 798b0c25 | bellard | uint8_t ar_index; |
69 | 798b0c25 | bellard | uint8_t ar[21];
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70 | 798b0c25 | bellard | int ar_flip_flop;
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71 | 798b0c25 | bellard | uint8_t cr_index; |
72 | 798b0c25 | bellard | uint8_t cr[256]; /* CRT registers */ |
73 | 798b0c25 | bellard | uint8_t msr; /* Misc Output Register */
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74 | 798b0c25 | bellard | uint8_t fcr; /* Feature Control Register */
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75 | 798b0c25 | bellard | uint8_t st00; /* status 0 */
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76 | 798b0c25 | bellard | uint8_t st01; /* status 1 */
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77 | 798b0c25 | bellard | uint8_t dac_state; |
78 | 798b0c25 | bellard | uint8_t dac_sub_index; |
79 | 798b0c25 | bellard | uint8_t dac_read_index; |
80 | 798b0c25 | bellard | uint8_t dac_write_index; |
81 | 798b0c25 | bellard | uint8_t dac_cache[3]; /* used when writing */ |
82 | 798b0c25 | bellard | uint8_t palette[768];
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83 | 798b0c25 | bellard | int32_t bank_offset; |
84 | 798b0c25 | bellard | int (*get_bpp)(struct VGAState *s); |
85 | 798b0c25 | bellard | void (*get_offsets)(struct VGAState *s, |
86 | 798b0c25 | bellard | uint32_t *pline_offset, |
87 | 798b0c25 | bellard | uint32_t *pstart_addr); |
88 | 798b0c25 | bellard | #ifdef CONFIG_BOCHS_VBE
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89 | 798b0c25 | bellard | uint16_t vbe_index; |
90 | 798b0c25 | bellard | uint16_t vbe_regs[VBE_DISPI_INDEX_NB]; |
91 | 798b0c25 | bellard | uint32_t vbe_start_addr; |
92 | 798b0c25 | bellard | uint32_t vbe_line_offset; |
93 | 798b0c25 | bellard | uint32_t vbe_bank_mask; |
94 | 798b0c25 | bellard | #endif
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95 | 798b0c25 | bellard | /* display refresh support */
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96 | 798b0c25 | bellard | DisplayState *ds; |
97 | 798b0c25 | bellard | uint32_t font_offsets[2];
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98 | 798b0c25 | bellard | int graphic_mode;
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99 | 798b0c25 | bellard | uint8_t shift_control; |
100 | 798b0c25 | bellard | uint8_t double_scan; |
101 | 798b0c25 | bellard | uint32_t line_offset; |
102 | 798b0c25 | bellard | uint32_t line_compare; |
103 | 798b0c25 | bellard | uint32_t start_addr; |
104 | 798b0c25 | bellard | uint8_t last_cw, last_ch; |
105 | 798b0c25 | bellard | uint32_t last_width, last_height; /* in chars or pixels */
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106 | 798b0c25 | bellard | uint32_t last_scr_width, last_scr_height; /* in pixels */
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107 | 798b0c25 | bellard | uint8_t cursor_start, cursor_end; |
108 | 798b0c25 | bellard | uint32_t cursor_offset; |
109 | 798b0c25 | bellard | unsigned int (*rgb_to_pixel)(unsigned int r, unsigned int g, unsigned b); |
110 | 798b0c25 | bellard | /* tell for each page if it has been updated since the last time */
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111 | 798b0c25 | bellard | uint32_t last_palette[256];
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112 | 798b0c25 | bellard | #define CH_ATTR_SIZE (160 * 100) |
113 | 798b0c25 | bellard | uint32_t last_ch_attr[CH_ATTR_SIZE]; /* XXX: make it dynamic */
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114 | 798b0c25 | bellard | } VGAState; |
115 | 798b0c25 | bellard | |
116 | 798b0c25 | bellard | void vga_common_init(VGAState *s, DisplayState *ds, uint8_t *vga_ram_base,
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117 | 798b0c25 | bellard | unsigned long vga_ram_offset, int vga_ram_size); |
118 | 798b0c25 | bellard | uint32_t vga_mem_readb(void *opaque, target_phys_addr_t addr);
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119 | 798b0c25 | bellard | void vga_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val); |
120 | 798b0c25 | bellard | |
121 | 798b0c25 | bellard | extern const uint8_t sr_mask[8]; |
122 | 798b0c25 | bellard | extern const uint8_t gr_mask[16]; |