root / cache-utils.c @ 7b239bec
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1 | 902b3d5c | malc | #include "cache-utils.h" |
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2 | 902b3d5c | malc | |
3 | 902b3d5c | malc | #ifdef __powerpc__
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4 | 902b3d5c | malc | struct qemu_cache_conf qemu_cache_conf = {
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5 | 902b3d5c | malc | .dcache_bsize = 16,
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6 | 902b3d5c | malc | .icache_bsize = 16
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7 | 902b3d5c | malc | }; |
8 | 902b3d5c | malc | |
9 | 902b3d5c | malc | #if defined _AIX
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10 | 902b3d5c | malc | #include <sys/systemcfg.h> |
11 | 902b3d5c | malc | |
12 | 902b3d5c | malc | static void ppc_init_cacheline_sizes(void) |
13 | 902b3d5c | malc | { |
14 | 902b3d5c | malc | qemu_cache_conf.icache_bsize = _system_configuration.icache_line; |
15 | 902b3d5c | malc | qemu_cache_conf.dcache_bsize = _system_configuration.dcache_line; |
16 | 902b3d5c | malc | } |
17 | 902b3d5c | malc | |
18 | 902b3d5c | malc | #elif defined __linux__
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19 | 4710036a | malc | |
20 | 4710036a | malc | #define QEMU_AT_NULL 0 |
21 | 4710036a | malc | #define QEMU_AT_DCACHEBSIZE 19 |
22 | 4710036a | malc | #define QEMU_AT_ICACHEBSIZE 20 |
23 | 902b3d5c | malc | |
24 | 902b3d5c | malc | static void ppc_init_cacheline_sizes(char **envp) |
25 | 902b3d5c | malc | { |
26 | 902b3d5c | malc | unsigned long *auxv; |
27 | 902b3d5c | malc | |
28 | 902b3d5c | malc | while (*envp++);
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29 | 902b3d5c | malc | |
30 | 4710036a | malc | for (auxv = (unsigned long *) envp; *auxv != QEMU_AT_NULL; auxv += 2) { |
31 | 902b3d5c | malc | switch (*auxv) {
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32 | 807d5170 | malc | case QEMU_AT_DCACHEBSIZE: qemu_cache_conf.dcache_bsize = auxv[1]; break; |
33 | 807d5170 | malc | case QEMU_AT_ICACHEBSIZE: qemu_cache_conf.icache_bsize = auxv[1]; break; |
34 | 902b3d5c | malc | default: break; |
35 | 902b3d5c | malc | } |
36 | 902b3d5c | malc | } |
37 | 902b3d5c | malc | } |
38 | 902b3d5c | malc | |
39 | 902b3d5c | malc | #elif defined __APPLE__
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40 | 902b3d5c | malc | #include <sys/types.h> |
41 | 902b3d5c | malc | #include <sys/sysctl.h> |
42 | 902b3d5c | malc | |
43 | 902b3d5c | malc | static void ppc_init_cacheline_sizes(void) |
44 | 902b3d5c | malc | { |
45 | 902b3d5c | malc | size_t len; |
46 | 902b3d5c | malc | unsigned cacheline;
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47 | 902b3d5c | malc | int name[2] = { CTL_HW, HW_CACHELINE }; |
48 | 902b3d5c | malc | |
49 | 902b3d5c | malc | if (sysctl(name, 2, &cacheline, &len, NULL, 0)) { |
50 | 902b3d5c | malc | perror("sysctl CTL_HW HW_CACHELINE failed");
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51 | 902b3d5c | malc | } else {
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52 | 902b3d5c | malc | qemu_cache_conf.dcache_bsize = cacheline; |
53 | 902b3d5c | malc | qemu_cache_conf.icache_bsize = cacheline; |
54 | 902b3d5c | malc | } |
55 | 902b3d5c | malc | } |
56 | 902b3d5c | malc | #endif
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57 | 902b3d5c | malc | |
58 | 902b3d5c | malc | #ifdef __linux__
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59 | 902b3d5c | malc | void qemu_cache_utils_init(char **envp) |
60 | 902b3d5c | malc | { |
61 | 902b3d5c | malc | ppc_init_cacheline_sizes(envp); |
62 | 902b3d5c | malc | } |
63 | 902b3d5c | malc | #else
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64 | 902b3d5c | malc | void qemu_cache_utils_init(char **envp) |
65 | 902b3d5c | malc | { |
66 | 902b3d5c | malc | (void) envp;
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67 | 902b3d5c | malc | ppc_init_cacheline_sizes(); |
68 | 902b3d5c | malc | } |
69 | 902b3d5c | malc | #endif
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70 | 902b3d5c | malc | |
71 | 902b3d5c | malc | #endif /* __powerpc__ */ |