Revision 7b270ef2
| b/target-mips/translate.c | ||
|---|---|---|
| 463 | 463 |
struct TranslationBlock *tb; |
| 464 | 464 |
target_ulong pc, saved_pc; |
| 465 | 465 |
uint32_t opcode; |
| 466 |
int singlestep_enabled; |
|
| 466 | 467 |
/* Routine used to access memory */ |
| 467 | 468 |
int mem_idx; |
| 468 | 469 |
uint32_t hflags, saved_hflags; |
| ... | ... | |
| 2459 | 2460 |
{
|
| 2460 | 2461 |
TranslationBlock *tb; |
| 2461 | 2462 |
tb = ctx->tb; |
| 2462 |
if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
|
|
| 2463 |
if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) && |
|
| 2464 |
likely(!ctx->singlestep_enabled)) {
|
|
| 2463 | 2465 |
tcg_gen_goto_tb(n); |
| 2464 | 2466 |
gen_save_pc(dest); |
| 2465 | 2467 |
tcg_gen_exit_tb((long)tb + n); |
| 2466 | 2468 |
} else {
|
| 2467 | 2469 |
gen_save_pc(dest); |
| 2470 |
if (ctx->singlestep_enabled) {
|
|
| 2471 |
save_cpu_state(ctx, 0); |
|
| 2472 |
gen_helper_0i(raise_exception, EXCP_DEBUG); |
|
| 2473 |
} |
|
| 2468 | 2474 |
tcg_gen_exit_tb(0); |
| 2469 | 2475 |
} |
| 2470 | 2476 |
} |
| ... | ... | |
| 8263 | 8269 |
/* unconditional branch to register */ |
| 8264 | 8270 |
MIPS_DEBUG("branch to register");
|
| 8265 | 8271 |
tcg_gen_mov_tl(cpu_PC, btarget); |
| 8272 |
if (ctx->singlestep_enabled) {
|
|
| 8273 |
save_cpu_state(ctx, 0); |
|
| 8274 |
gen_helper_0i(raise_exception, EXCP_DEBUG); |
|
| 8275 |
} |
|
| 8266 | 8276 |
tcg_gen_exit_tb(0); |
| 8267 | 8277 |
break; |
| 8268 | 8278 |
default: |
| ... | ... | |
| 8292 | 8302 |
gen_opc_end = gen_opc_buf + OPC_MAX_SIZE - 16; |
| 8293 | 8303 |
ctx.pc = pc_start; |
| 8294 | 8304 |
ctx.saved_pc = -1; |
| 8305 |
ctx.singlestep_enabled = env->singlestep_enabled; |
|
| 8295 | 8306 |
ctx.tb = tb; |
| 8296 | 8307 |
ctx.bstate = BS_NONE; |
| 8297 | 8308 |
/* Restore delay slot state from the tb context. */ |
| ... | ... | |
| 8347 | 8358 |
ctx.pc += 4; |
| 8348 | 8359 |
num_insns++; |
| 8349 | 8360 |
|
| 8350 |
if (env->singlestep_enabled) |
|
| 8361 |
/* Execute a branch and its delay slot as a single instruction. |
|
| 8362 |
This is what GDB expects and is consistent with what the |
|
| 8363 |
hardware does (e.g. if a delay slot instruction faults, the |
|
| 8364 |
reported PC is the PC of the branch). */ |
|
| 8365 |
if (env->singlestep_enabled && (ctx.hflags & MIPS_HFLAG_BMASK) == 0) |
|
| 8351 | 8366 |
break; |
| 8352 | 8367 |
|
| 8353 | 8368 |
if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0) |
| ... | ... | |
| 8364 | 8379 |
} |
| 8365 | 8380 |
if (tb->cflags & CF_LAST_IO) |
| 8366 | 8381 |
gen_io_end(); |
| 8367 |
if (env->singlestep_enabled) {
|
|
| 8382 |
if (env->singlestep_enabled && ctx.bstate != BS_BRANCH) {
|
|
| 8368 | 8383 |
save_cpu_state(&ctx, ctx.bstate == BS_NONE); |
| 8369 | 8384 |
gen_helper_0i(raise_exception, EXCP_DEBUG); |
| 8370 | 8385 |
} else {
|
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