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/*
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* Texas Instruments OMAP processors.
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*
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* Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 or
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* (at your option) version 3 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef hw_omap_h
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# define hw_omap_h "omap.h" |
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# define OMAP_EMIFS_BASE 0x00000000 |
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# define OMAP2_Q0_BASE 0x00000000 |
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# define OMAP_CS0_BASE 0x00000000 |
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# define OMAP_CS1_BASE 0x04000000 |
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# define OMAP_CS2_BASE 0x08000000 |
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# define OMAP_CS3_BASE 0x0c000000 |
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# define OMAP_EMIFF_BASE 0x10000000 |
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# define OMAP_IMIF_BASE 0x20000000 |
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# define OMAP_LOCALBUS_BASE 0x30000000 |
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# define OMAP2_Q1_BASE 0x40000000 |
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# define OMAP2_L4_BASE 0x48000000 |
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# define OMAP2_SRAM_BASE 0x40200000 |
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# define OMAP2_L3_BASE 0x68000000 |
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# define OMAP2_Q2_BASE 0x80000000 |
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# define OMAP2_Q3_BASE 0xc0000000 |
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# define OMAP_MPUI_BASE 0xe1000000 |
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# define OMAP730_SRAM_SIZE 0x00032000 |
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# define OMAP15XX_SRAM_SIZE 0x00030000 |
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# define OMAP16XX_SRAM_SIZE 0x00004000 |
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# define OMAP1611_SRAM_SIZE 0x0003e800 |
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# define OMAP242X_SRAM_SIZE 0x000a0000 |
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# define OMAP243X_SRAM_SIZE 0x00010000 |
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# define OMAP_CS0_SIZE 0x04000000 |
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# define OMAP_CS1_SIZE 0x04000000 |
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# define OMAP_CS2_SIZE 0x04000000 |
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# define OMAP_CS3_SIZE 0x04000000 |
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/* omap_clk.c */
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struct omap_mpu_state_s;
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typedef struct clk *omap_clk; |
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omap_clk omap_findclk(struct omap_mpu_state_s *mpu, const char *name); |
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void omap_clk_init(struct omap_mpu_state_s *mpu); |
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void omap_clk_adduser(struct clk *clk, qemu_irq user); |
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void omap_clk_get(omap_clk clk);
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void omap_clk_put(omap_clk clk);
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void omap_clk_onoff(omap_clk clk, int on); |
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void omap_clk_canidle(omap_clk clk, int can); |
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void omap_clk_setrate(omap_clk clk, int divide, int multiply); |
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int64_t omap_clk_getrate(omap_clk clk); |
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void omap_clk_reparent(omap_clk clk, omap_clk parent);
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/* omap[123].c */
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struct omap_l4_s;
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struct omap_l4_s *omap_l4_init(target_phys_addr_t base, int ta_num); |
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struct omap_target_agent_s;
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struct omap_target_agent_s *omap_l4ta_get(struct omap_l4_s *bus, int cs); |
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target_phys_addr_t omap_l4_attach(struct omap_target_agent_s *ta, int region, |
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int iotype);
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# define l4_register_io_memory cpu_register_io_memory
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struct omap_intr_handler_s;
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struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base,
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unsigned long size, unsigned char nbanks, qemu_irq **pins, |
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qemu_irq parent_irq, qemu_irq parent_fiq, omap_clk clk); |
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struct omap_intr_handler_s *omap2_inth_init(target_phys_addr_t base,
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int size, int nbanks, qemu_irq **pins, |
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qemu_irq parent_irq, qemu_irq parent_fiq, |
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omap_clk fclk, omap_clk iclk); |
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void omap_inth_reset(struct omap_intr_handler_s *s); |
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struct omap_prcm_s;
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struct omap_prcm_s *omap_prcm_init(struct omap_target_agent_s *ta, |
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qemu_irq mpu_int, qemu_irq dsp_int, qemu_irq iva_int, |
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struct omap_mpu_state_s *mpu);
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struct omap_sysctl_s;
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struct omap_sysctl_s *omap_sysctl_init(struct omap_target_agent_s *ta, |
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omap_clk iclk, struct omap_mpu_state_s *mpu);
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struct omap_sdrc_s;
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struct omap_sdrc_s *omap_sdrc_init(target_phys_addr_t base);
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struct omap_gpmc_s;
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struct omap_gpmc_s *omap_gpmc_init(target_phys_addr_t base, qemu_irq irq);
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void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, int iomemtype, |
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void (*base_upd)(void *opaque, target_phys_addr_t new), |
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void (*unmap)(void *opaque), void *opaque); |
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/*
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* Common IRQ numbers for level 1 interrupt handler
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* See /usr/include/asm-arm/arch-omap/irqs.h in Linux.
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*/
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# define OMAP_INT_CAMERA 1 |
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# define OMAP_INT_FIQ 3 |
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# define OMAP_INT_RTDX 6 |
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# define OMAP_INT_DSP_MMU_ABORT 7 |
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# define OMAP_INT_HOST 8 |
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# define OMAP_INT_ABORT 9 |
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# define OMAP_INT_BRIDGE_PRIV 13 |
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# define OMAP_INT_GPIO_BANK1 14 |
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# define OMAP_INT_UART3 15 |
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# define OMAP_INT_TIMER3 16 |
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# define OMAP_INT_DMA_CH0_6 19 |
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# define OMAP_INT_DMA_CH1_7 20 |
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# define OMAP_INT_DMA_CH2_8 21 |
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# define OMAP_INT_DMA_CH3 22 |
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# define OMAP_INT_DMA_CH4 23 |
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# define OMAP_INT_DMA_CH5 24 |
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# define OMAP_INT_DMA_LCD 25 |
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# define OMAP_INT_TIMER1 26 |
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# define OMAP_INT_WD_TIMER 27 |
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# define OMAP_INT_BRIDGE_PUB 28 |
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# define OMAP_INT_TIMER2 30 |
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# define OMAP_INT_LCD_CTRL 31 |
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/*
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* Common OMAP-15xx IRQ numbers for level 1 interrupt handler
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*/
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# define OMAP_INT_15XX_IH2_IRQ 0 |
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# define OMAP_INT_15XX_LB_MMU 17 |
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# define OMAP_INT_15XX_LOCAL_BUS 29 |
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/*
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* OMAP-1510 specific IRQ numbers for level 1 interrupt handler
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*/
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# define OMAP_INT_1510_SPI_TX 4 |
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# define OMAP_INT_1510_SPI_RX 5 |
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# define OMAP_INT_1510_DSP_MAILBOX1 10 |
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# define OMAP_INT_1510_DSP_MAILBOX2 11 |
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/*
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* OMAP-310 specific IRQ numbers for level 1 interrupt handler
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*/
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# define OMAP_INT_310_McBSP2_TX 4 |
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# define OMAP_INT_310_McBSP2_RX 5 |
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# define OMAP_INT_310_HSB_MAILBOX1 12 |
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# define OMAP_INT_310_HSAB_MMU 18 |
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/*
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* OMAP-1610 specific IRQ numbers for level 1 interrupt handler
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*/
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# define OMAP_INT_1610_IH2_IRQ 0 |
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# define OMAP_INT_1610_IH2_FIQ 2 |
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# define OMAP_INT_1610_McBSP2_TX 4 |
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# define OMAP_INT_1610_McBSP2_RX 5 |
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# define OMAP_INT_1610_DSP_MAILBOX1 10 |
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# define OMAP_INT_1610_DSP_MAILBOX2 11 |
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# define OMAP_INT_1610_LCD_LINE 12 |
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# define OMAP_INT_1610_GPTIMER1 17 |
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# define OMAP_INT_1610_GPTIMER2 18 |
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# define OMAP_INT_1610_SSR_FIFO_0 29 |
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/*
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* OMAP-730 specific IRQ numbers for level 1 interrupt handler
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*/
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# define OMAP_INT_730_IH2_FIQ 0 |
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# define OMAP_INT_730_IH2_IRQ 1 |
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# define OMAP_INT_730_USB_NON_ISO 2 |
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# define OMAP_INT_730_USB_ISO 3 |
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# define OMAP_INT_730_ICR 4 |
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# define OMAP_INT_730_EAC 5 |
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# define OMAP_INT_730_GPIO_BANK1 6 |
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# define OMAP_INT_730_GPIO_BANK2 7 |
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# define OMAP_INT_730_GPIO_BANK3 8 |
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# define OMAP_INT_730_McBSP2TX 10 |
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# define OMAP_INT_730_McBSP2RX 11 |
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# define OMAP_INT_730_McBSP2RX_OVF 12 |
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# define OMAP_INT_730_LCD_LINE 14 |
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# define OMAP_INT_730_GSM_PROTECT 15 |
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# define OMAP_INT_730_TIMER3 16 |
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# define OMAP_INT_730_GPIO_BANK5 17 |
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# define OMAP_INT_730_GPIO_BANK6 18 |
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# define OMAP_INT_730_SPGIO_WR 29 |
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/*
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* Common IRQ numbers for level 2 interrupt handler
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*/
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# define OMAP_INT_KEYBOARD 1 |
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# define OMAP_INT_uWireTX 2 |
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# define OMAP_INT_uWireRX 3 |
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# define OMAP_INT_I2C 4 |
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# define OMAP_INT_MPUIO 5 |
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# define OMAP_INT_USB_HHC_1 6 |
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# define OMAP_INT_McBSP3TX 10 |
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# define OMAP_INT_McBSP3RX 11 |
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# define OMAP_INT_McBSP1TX 12 |
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# define OMAP_INT_McBSP1RX 13 |
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# define OMAP_INT_UART1 14 |
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# define OMAP_INT_UART2 15 |
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# define OMAP_INT_USB_W2FC 20 |
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# define OMAP_INT_1WIRE 21 |
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# define OMAP_INT_OS_TIMER 22 |
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# define OMAP_INT_OQN 23 |
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# define OMAP_INT_GAUGE_32K 24 |
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# define OMAP_INT_RTC_TIMER 25 |
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# define OMAP_INT_RTC_ALARM 26 |
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# define OMAP_INT_DSP_MMU 28 |
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/*
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* OMAP-1510 specific IRQ numbers for level 2 interrupt handler
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*/
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# define OMAP_INT_1510_BT_MCSI1TX 16 |
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# define OMAP_INT_1510_BT_MCSI1RX 17 |
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# define OMAP_INT_1510_SoSSI_MATCH 19 |
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# define OMAP_INT_1510_MEM_STICK 27 |
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# define OMAP_INT_1510_COM_SPI_RO 31 |
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/*
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* OMAP-310 specific IRQ numbers for level 2 interrupt handler
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*/
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# define OMAP_INT_310_FAC 0 |
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# define OMAP_INT_310_USB_HHC_2 7 |
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# define OMAP_INT_310_MCSI1_FE 16 |
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# define OMAP_INT_310_MCSI2_FE 17 |
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# define OMAP_INT_310_USB_W2FC_ISO 29 |
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# define OMAP_INT_310_USB_W2FC_NON_ISO 30 |
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# define OMAP_INT_310_McBSP2RX_OF 31 |
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/*
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* OMAP-1610 specific IRQ numbers for level 2 interrupt handler
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*/
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# define OMAP_INT_1610_FAC 0 |
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# define OMAP_INT_1610_USB_HHC_2 7 |
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# define OMAP_INT_1610_USB_OTG 8 |
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# define OMAP_INT_1610_SoSSI 9 |
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# define OMAP_INT_1610_BT_MCSI1TX 16 |
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# define OMAP_INT_1610_BT_MCSI1RX 17 |
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# define OMAP_INT_1610_SoSSI_MATCH 19 |
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# define OMAP_INT_1610_MEM_STICK 27 |
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# define OMAP_INT_1610_McBSP2RX_OF 31 |
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# define OMAP_INT_1610_STI 32 |
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# define OMAP_INT_1610_STI_WAKEUP 33 |
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# define OMAP_INT_1610_GPTIMER3 34 |
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# define OMAP_INT_1610_GPTIMER4 35 |
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# define OMAP_INT_1610_GPTIMER5 36 |
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# define OMAP_INT_1610_GPTIMER6 37 |
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# define OMAP_INT_1610_GPTIMER7 38 |
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# define OMAP_INT_1610_GPTIMER8 39 |
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# define OMAP_INT_1610_GPIO_BANK2 40 |
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# define OMAP_INT_1610_GPIO_BANK3 41 |
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# define OMAP_INT_1610_MMC2 42 |
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# define OMAP_INT_1610_CF 43 |
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# define OMAP_INT_1610_WAKE_UP_REQ 46 |
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# define OMAP_INT_1610_GPIO_BANK4 48 |
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# define OMAP_INT_1610_SPI 49 |
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# define OMAP_INT_1610_DMA_CH6 53 |
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# define OMAP_INT_1610_DMA_CH7 54 |
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# define OMAP_INT_1610_DMA_CH8 55 |
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# define OMAP_INT_1610_DMA_CH9 56 |
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# define OMAP_INT_1610_DMA_CH10 57 |
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# define OMAP_INT_1610_DMA_CH11 58 |
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# define OMAP_INT_1610_DMA_CH12 59 |
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# define OMAP_INT_1610_DMA_CH13 60 |
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# define OMAP_INT_1610_DMA_CH14 61 |
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# define OMAP_INT_1610_DMA_CH15 62 |
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# define OMAP_INT_1610_NAND 63 |
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/*
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* OMAP-730 specific IRQ numbers for level 2 interrupt handler
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*/
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# define OMAP_INT_730_HW_ERRORS 0 |
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# define OMAP_INT_730_NFIQ_PWR_FAIL 1 |
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# define OMAP_INT_730_CFCD 2 |
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# define OMAP_INT_730_CFIREQ 3 |
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# define OMAP_INT_730_I2C 4 |
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# define OMAP_INT_730_PCC 5 |
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# define OMAP_INT_730_MPU_EXT_NIRQ 6 |
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# define OMAP_INT_730_SPI_100K_1 7 |
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# define OMAP_INT_730_SYREN_SPI 8 |
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# define OMAP_INT_730_VLYNQ 9 |
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# define OMAP_INT_730_GPIO_BANK4 10 |
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# define OMAP_INT_730_McBSP1TX 11 |
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# define OMAP_INT_730_McBSP1RX 12 |
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# define OMAP_INT_730_McBSP1RX_OF 13 |
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# define OMAP_INT_730_UART_MODEM_IRDA_2 14 |
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# define OMAP_INT_730_UART_MODEM_1 15 |
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# define OMAP_INT_730_MCSI 16 |
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# define OMAP_INT_730_uWireTX 17 |
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# define OMAP_INT_730_uWireRX 18 |
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# define OMAP_INT_730_SMC_CD 19 |
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# define OMAP_INT_730_SMC_IREQ 20 |
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# define OMAP_INT_730_HDQ_1WIRE 21 |
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# define OMAP_INT_730_TIMER32K 22 |
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# define OMAP_INT_730_MMC_SDIO 23 |
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# define OMAP_INT_730_UPLD 24 |
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# define OMAP_INT_730_USB_HHC_1 27 |
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# define OMAP_INT_730_USB_HHC_2 28 |
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# define OMAP_INT_730_USB_GENI 29 |
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# define OMAP_INT_730_USB_OTG 30 |
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# define OMAP_INT_730_CAMERA_IF 31 |
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# define OMAP_INT_730_RNG 32 |
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# define OMAP_INT_730_DUAL_MODE_TIMER 33 |
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# define OMAP_INT_730_DBB_RF_EN 34 |
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# define OMAP_INT_730_MPUIO_KEYPAD 35 |
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# define OMAP_INT_730_SHA1_MD5 36 |
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# define OMAP_INT_730_SPI_100K_2 37 |
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# define OMAP_INT_730_RNG_IDLE 38 |
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# define OMAP_INT_730_MPUIO 39 |
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# define OMAP_INT_730_LLPC_LCD_CTRL_OFF 40 |
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# define OMAP_INT_730_LLPC_OE_FALLING 41 |
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# define OMAP_INT_730_LLPC_OE_RISING 42 |
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# define OMAP_INT_730_LLPC_VSYNC 43 |
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# define OMAP_INT_730_WAKE_UP_REQ 46 |
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# define OMAP_INT_730_DMA_CH6 53 |
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# define OMAP_INT_730_DMA_CH7 54 |
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# define OMAP_INT_730_DMA_CH8 55 |
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# define OMAP_INT_730_DMA_CH9 56 |
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# define OMAP_INT_730_DMA_CH10 57 |
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# define OMAP_INT_730_DMA_CH11 58 |
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# define OMAP_INT_730_DMA_CH12 59 |
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# define OMAP_INT_730_DMA_CH13 60 |
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# define OMAP_INT_730_DMA_CH14 61 |
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# define OMAP_INT_730_DMA_CH15 62 |
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# define OMAP_INT_730_NAND 63 |
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|
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/*
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* OMAP-24xx common IRQ numbers
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*/
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# define OMAP_INT_24XX_STI 4 |
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# define OMAP_INT_24XX_SYS_NIRQ 7 |
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# define OMAP_INT_24XX_L3_IRQ 10 |
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# define OMAP_INT_24XX_PRCM_MPU_IRQ 11 |
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# define OMAP_INT_24XX_SDMA_IRQ0 12 |
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# define OMAP_INT_24XX_SDMA_IRQ1 13 |
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# define OMAP_INT_24XX_SDMA_IRQ2 14 |
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# define OMAP_INT_24XX_SDMA_IRQ3 15 |
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# define OMAP_INT_243X_MCBSP2_IRQ 16 |
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# define OMAP_INT_243X_MCBSP3_IRQ 17 |
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# define OMAP_INT_243X_MCBSP4_IRQ 18 |
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# define OMAP_INT_243X_MCBSP5_IRQ 19 |
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# define OMAP_INT_24XX_GPMC_IRQ 20 |
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# define OMAP_INT_24XX_GUFFAW_IRQ 21 |
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# define OMAP_INT_24XX_IVA_IRQ 22 |
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# define OMAP_INT_24XX_EAC_IRQ 23 |
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# define OMAP_INT_24XX_CAM_IRQ 24 |
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# define OMAP_INT_24XX_DSS_IRQ 25 |
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# define OMAP_INT_24XX_MAIL_U0_MPU 26 |
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# define OMAP_INT_24XX_DSP_UMA 27 |
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# define OMAP_INT_24XX_DSP_MMU 28 |
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# define OMAP_INT_24XX_GPIO_BANK1 29 |
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# define OMAP_INT_24XX_GPIO_BANK2 30 |
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# define OMAP_INT_24XX_GPIO_BANK3 31 |
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# define OMAP_INT_24XX_GPIO_BANK4 32 |
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# define OMAP_INT_243X_GPIO_BANK5 33 |
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# define OMAP_INT_24XX_MAIL_U3_MPU 34 |
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# define OMAP_INT_24XX_WDT3 35 |
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# define OMAP_INT_24XX_WDT4 36 |
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# define OMAP_INT_24XX_GPTIMER1 37 |
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# define OMAP_INT_24XX_GPTIMER2 38 |
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# define OMAP_INT_24XX_GPTIMER3 39 |
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# define OMAP_INT_24XX_GPTIMER4 40 |
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# define OMAP_INT_24XX_GPTIMER5 41 |
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# define OMAP_INT_24XX_GPTIMER6 42 |
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# define OMAP_INT_24XX_GPTIMER7 43 |
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# define OMAP_INT_24XX_GPTIMER8 44 |
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# define OMAP_INT_24XX_GPTIMER9 45 |
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# define OMAP_INT_24XX_GPTIMER10 46 |
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# define OMAP_INT_24XX_GPTIMER11 47 |
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# define OMAP_INT_24XX_GPTIMER12 48 |
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# define OMAP_INT_24XX_PKA_IRQ 50 |
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# define OMAP_INT_24XX_SHA1MD5_IRQ 51 |
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# define OMAP_INT_24XX_RNG_IRQ 52 |
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# define OMAP_INT_24XX_MG_IRQ 53 |
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# define OMAP_INT_24XX_I2C1_IRQ 56 |
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# define OMAP_INT_24XX_I2C2_IRQ 57 |
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# define OMAP_INT_24XX_MCBSP1_IRQ_TX 59 |
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# define OMAP_INT_24XX_MCBSP1_IRQ_RX 60 |
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# define OMAP_INT_24XX_MCBSP2_IRQ_TX 62 |
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# define OMAP_INT_24XX_MCBSP2_IRQ_RX 63 |
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# define OMAP_INT_243X_MCBSP1_IRQ 64 |
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# define OMAP_INT_24XX_MCSPI1_IRQ 65 |
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# define OMAP_INT_24XX_MCSPI2_IRQ 66 |
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# define OMAP_INT_24XX_SSI1_IRQ0 67 |
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# define OMAP_INT_24XX_SSI1_IRQ1 68 |
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# define OMAP_INT_24XX_SSI2_IRQ0 69 |
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# define OMAP_INT_24XX_SSI2_IRQ1 70 |
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# define OMAP_INT_24XX_SSI_GDD_IRQ 71 |
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# define OMAP_INT_24XX_UART1_IRQ 72 |
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# define OMAP_INT_24XX_UART2_IRQ 73 |
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# define OMAP_INT_24XX_UART3_IRQ 74 |
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# define OMAP_INT_24XX_USB_IRQ_GEN 75 |
395 |
# define OMAP_INT_24XX_USB_IRQ_NISO 76 |
396 |
# define OMAP_INT_24XX_USB_IRQ_ISO 77 |
397 |
# define OMAP_INT_24XX_USB_IRQ_HGEN 78 |
398 |
# define OMAP_INT_24XX_USB_IRQ_HSOF 79 |
399 |
# define OMAP_INT_24XX_USB_IRQ_OTG 80 |
400 |
# define OMAP_INT_24XX_VLYNQ_IRQ 81 |
401 |
# define OMAP_INT_24XX_MMC_IRQ 83 |
402 |
# define OMAP_INT_24XX_MS_IRQ 84 |
403 |
# define OMAP_INT_24XX_FAC_IRQ 85 |
404 |
# define OMAP_INT_24XX_MCSPI3_IRQ 91 |
405 |
# define OMAP_INT_243X_HS_USB_MC 92 |
406 |
# define OMAP_INT_243X_HS_USB_DMA 93 |
407 |
# define OMAP_INT_243X_CARKIT 94 |
408 |
# define OMAP_INT_34XX_GPTIMER12 95 |
409 |
|
410 |
/* omap_dma.c */
|
411 |
enum omap_dma_model {
|
412 |
omap_dma_3_0, |
413 |
omap_dma_3_1, |
414 |
omap_dma_3_2, |
415 |
omap_dma_4, |
416 |
}; |
417 |
|
418 |
struct soc_dma_s;
|
419 |
struct soc_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs,
|
420 |
qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk,
|
421 |
enum omap_dma_model model);
|
422 |
struct soc_dma_s *omap_dma4_init(target_phys_addr_t base, qemu_irq *irqs,
|
423 |
struct omap_mpu_state_s *mpu, int fifo, |
424 |
int chans, omap_clk iclk, omap_clk fclk);
|
425 |
void omap_dma_reset(struct soc_dma_s *s); |
426 |
|
427 |
struct dma_irq_map {
|
428 |
int ih;
|
429 |
int intr;
|
430 |
}; |
431 |
|
432 |
/* Only used in OMAP DMA 3.x gigacells */
|
433 |
enum omap_dma_port {
|
434 |
emiff = 0,
|
435 |
emifs, |
436 |
imif, /* omap16xx: ocp_t1 */
|
437 |
tipb, |
438 |
local, /* omap16xx: ocp_t2 */
|
439 |
tipb_mpui, |
440 |
__omap_dma_port_last, |
441 |
}; |
442 |
|
443 |
typedef enum { |
444 |
constant = 0,
|
445 |
post_incremented, |
446 |
single_index, |
447 |
double_index, |
448 |
} omap_dma_addressing_t; |
449 |
|
450 |
/* Only used in OMAP DMA 3.x gigacells */
|
451 |
struct omap_dma_lcd_channel_s {
|
452 |
enum omap_dma_port src;
|
453 |
target_phys_addr_t src_f1_top; |
454 |
target_phys_addr_t src_f1_bottom; |
455 |
target_phys_addr_t src_f2_top; |
456 |
target_phys_addr_t src_f2_bottom; |
457 |
|
458 |
/* Used in OMAP DMA 3.2 gigacell */
|
459 |
unsigned char brust_f1; |
460 |
unsigned char pack_f1; |
461 |
unsigned char data_type_f1; |
462 |
unsigned char brust_f2; |
463 |
unsigned char pack_f2; |
464 |
unsigned char data_type_f2; |
465 |
unsigned char end_prog; |
466 |
unsigned char repeat; |
467 |
unsigned char auto_init; |
468 |
unsigned char priority; |
469 |
unsigned char fs; |
470 |
unsigned char running; |
471 |
unsigned char bs; |
472 |
unsigned char omap_3_1_compatible_disable; |
473 |
unsigned char dst; |
474 |
unsigned char lch_type; |
475 |
int16_t element_index_f1; |
476 |
int16_t element_index_f2; |
477 |
int32_t frame_index_f1; |
478 |
int32_t frame_index_f2; |
479 |
uint16_t elements_f1; |
480 |
uint16_t frames_f1; |
481 |
uint16_t elements_f2; |
482 |
uint16_t frames_f2; |
483 |
omap_dma_addressing_t mode_f1; |
484 |
omap_dma_addressing_t mode_f2; |
485 |
|
486 |
/* Destination port is fixed. */
|
487 |
int interrupts;
|
488 |
int condition;
|
489 |
int dual;
|
490 |
|
491 |
int current_frame;
|
492 |
target_phys_addr_t phys_framebuffer[2];
|
493 |
qemu_irq irq; |
494 |
struct omap_mpu_state_s *mpu;
|
495 |
} *omap_dma_get_lcdch(struct soc_dma_s *s);
|
496 |
|
497 |
/*
|
498 |
* DMA request numbers for OMAP1
|
499 |
* See /usr/include/asm-arm/arch-omap/dma.h in Linux.
|
500 |
*/
|
501 |
# define OMAP_DMA_NO_DEVICE 0 |
502 |
# define OMAP_DMA_MCSI1_TX 1 |
503 |
# define OMAP_DMA_MCSI1_RX 2 |
504 |
# define OMAP_DMA_I2C_RX 3 |
505 |
# define OMAP_DMA_I2C_TX 4 |
506 |
# define OMAP_DMA_EXT_NDMA_REQ0 5 |
507 |
# define OMAP_DMA_EXT_NDMA_REQ1 6 |
508 |
# define OMAP_DMA_UWIRE_TX 7 |
509 |
# define OMAP_DMA_MCBSP1_TX 8 |
510 |
# define OMAP_DMA_MCBSP1_RX 9 |
511 |
# define OMAP_DMA_MCBSP3_TX 10 |
512 |
# define OMAP_DMA_MCBSP3_RX 11 |
513 |
# define OMAP_DMA_UART1_TX 12 |
514 |
# define OMAP_DMA_UART1_RX 13 |
515 |
# define OMAP_DMA_UART2_TX 14 |
516 |
# define OMAP_DMA_UART2_RX 15 |
517 |
# define OMAP_DMA_MCBSP2_TX 16 |
518 |
# define OMAP_DMA_MCBSP2_RX 17 |
519 |
# define OMAP_DMA_UART3_TX 18 |
520 |
# define OMAP_DMA_UART3_RX 19 |
521 |
# define OMAP_DMA_CAMERA_IF_RX 20 |
522 |
# define OMAP_DMA_MMC_TX 21 |
523 |
# define OMAP_DMA_MMC_RX 22 |
524 |
# define OMAP_DMA_NAND 23 /* Not in OMAP310 */ |
525 |
# define OMAP_DMA_IRQ_LCD_LINE 24 /* Not in OMAP310 */ |
526 |
# define OMAP_DMA_MEMORY_STICK 25 /* Not in OMAP310 */ |
527 |
# define OMAP_DMA_USB_W2FC_RX0 26 |
528 |
# define OMAP_DMA_USB_W2FC_RX1 27 |
529 |
# define OMAP_DMA_USB_W2FC_RX2 28 |
530 |
# define OMAP_DMA_USB_W2FC_TX0 29 |
531 |
# define OMAP_DMA_USB_W2FC_TX1 30 |
532 |
# define OMAP_DMA_USB_W2FC_TX2 31 |
533 |
|
534 |
/* These are only for 1610 */
|
535 |
# define OMAP_DMA_CRYPTO_DES_IN 32 |
536 |
# define OMAP_DMA_SPI_TX 33 |
537 |
# define OMAP_DMA_SPI_RX 34 |
538 |
# define OMAP_DMA_CRYPTO_HASH 35 |
539 |
# define OMAP_DMA_CCP_ATTN 36 |
540 |
# define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37 |
541 |
# define OMAP_DMA_CMT_APE_TX_CHAN_0 38 |
542 |
# define OMAP_DMA_CMT_APE_RV_CHAN_0 39 |
543 |
# define OMAP_DMA_CMT_APE_TX_CHAN_1 40 |
544 |
# define OMAP_DMA_CMT_APE_RV_CHAN_1 41 |
545 |
# define OMAP_DMA_CMT_APE_TX_CHAN_2 42 |
546 |
# define OMAP_DMA_CMT_APE_RV_CHAN_2 43 |
547 |
# define OMAP_DMA_CMT_APE_TX_CHAN_3 44 |
548 |
# define OMAP_DMA_CMT_APE_RV_CHAN_3 45 |
549 |
# define OMAP_DMA_CMT_APE_TX_CHAN_4 46 |
550 |
# define OMAP_DMA_CMT_APE_RV_CHAN_4 47 |
551 |
# define OMAP_DMA_CMT_APE_TX_CHAN_5 48 |
552 |
# define OMAP_DMA_CMT_APE_RV_CHAN_5 49 |
553 |
# define OMAP_DMA_CMT_APE_TX_CHAN_6 50 |
554 |
# define OMAP_DMA_CMT_APE_RV_CHAN_6 51 |
555 |
# define OMAP_DMA_CMT_APE_TX_CHAN_7 52 |
556 |
# define OMAP_DMA_CMT_APE_RV_CHAN_7 53 |
557 |
# define OMAP_DMA_MMC2_TX 54 |
558 |
# define OMAP_DMA_MMC2_RX 55 |
559 |
# define OMAP_DMA_CRYPTO_DES_OUT 56 |
560 |
|
561 |
/*
|
562 |
* DMA request numbers for the OMAP2
|
563 |
*/
|
564 |
# define OMAP24XX_DMA_NO_DEVICE 0 |
565 |
# define OMAP24XX_DMA_XTI_DMA 1 /* Not in OMAP2420 */ |
566 |
# define OMAP24XX_DMA_EXT_DMAREQ0 2 |
567 |
# define OMAP24XX_DMA_EXT_DMAREQ1 3 |
568 |
# define OMAP24XX_DMA_GPMC 4 |
569 |
# define OMAP24XX_DMA_GFX 5 /* Not in OMAP2420 */ |
570 |
# define OMAP24XX_DMA_DSS 6 |
571 |
# define OMAP24XX_DMA_VLYNQ_TX 7 /* Not in OMAP2420 */ |
572 |
# define OMAP24XX_DMA_CWT 8 /* Not in OMAP2420 */ |
573 |
# define OMAP24XX_DMA_AES_TX 9 /* Not in OMAP2420 */ |
574 |
# define OMAP24XX_DMA_AES_RX 10 /* Not in OMAP2420 */ |
575 |
# define OMAP24XX_DMA_DES_TX 11 /* Not in OMAP2420 */ |
576 |
# define OMAP24XX_DMA_DES_RX 12 /* Not in OMAP2420 */ |
577 |
# define OMAP24XX_DMA_SHA1MD5_RX 13 /* Not in OMAP2420 */ |
578 |
# define OMAP24XX_DMA_EXT_DMAREQ2 14 |
579 |
# define OMAP24XX_DMA_EXT_DMAREQ3 15 |
580 |
# define OMAP24XX_DMA_EXT_DMAREQ4 16 |
581 |
# define OMAP24XX_DMA_EAC_AC_RD 17 |
582 |
# define OMAP24XX_DMA_EAC_AC_WR 18 |
583 |
# define OMAP24XX_DMA_EAC_MD_UL_RD 19 |
584 |
# define OMAP24XX_DMA_EAC_MD_UL_WR 20 |
585 |
# define OMAP24XX_DMA_EAC_MD_DL_RD 21 |
586 |
# define OMAP24XX_DMA_EAC_MD_DL_WR 22 |
587 |
# define OMAP24XX_DMA_EAC_BT_UL_RD 23 |
588 |
# define OMAP24XX_DMA_EAC_BT_UL_WR 24 |
589 |
# define OMAP24XX_DMA_EAC_BT_DL_RD 25 |
590 |
# define OMAP24XX_DMA_EAC_BT_DL_WR 26 |
591 |
# define OMAP24XX_DMA_I2C1_TX 27 |
592 |
# define OMAP24XX_DMA_I2C1_RX 28 |
593 |
# define OMAP24XX_DMA_I2C2_TX 29 |
594 |
# define OMAP24XX_DMA_I2C2_RX 30 |
595 |
# define OMAP24XX_DMA_MCBSP1_TX 31 |
596 |
# define OMAP24XX_DMA_MCBSP1_RX 32 |
597 |
# define OMAP24XX_DMA_MCBSP2_TX 33 |
598 |
# define OMAP24XX_DMA_MCBSP2_RX 34 |
599 |
# define OMAP24XX_DMA_SPI1_TX0 35 |
600 |
# define OMAP24XX_DMA_SPI1_RX0 36 |
601 |
# define OMAP24XX_DMA_SPI1_TX1 37 |
602 |
# define OMAP24XX_DMA_SPI1_RX1 38 |
603 |
# define OMAP24XX_DMA_SPI1_TX2 39 |
604 |
# define OMAP24XX_DMA_SPI1_RX2 40 |
605 |
# define OMAP24XX_DMA_SPI1_TX3 41 |
606 |
# define OMAP24XX_DMA_SPI1_RX3 42 |
607 |
# define OMAP24XX_DMA_SPI2_TX0 43 |
608 |
# define OMAP24XX_DMA_SPI2_RX0 44 |
609 |
# define OMAP24XX_DMA_SPI2_TX1 45 |
610 |
# define OMAP24XX_DMA_SPI2_RX1 46 |
611 |
|
612 |
# define OMAP24XX_DMA_UART1_TX 49 |
613 |
# define OMAP24XX_DMA_UART1_RX 50 |
614 |
# define OMAP24XX_DMA_UART2_TX 51 |
615 |
# define OMAP24XX_DMA_UART2_RX 52 |
616 |
# define OMAP24XX_DMA_UART3_TX 53 |
617 |
# define OMAP24XX_DMA_UART3_RX 54 |
618 |
# define OMAP24XX_DMA_USB_W2FC_TX0 55 |
619 |
# define OMAP24XX_DMA_USB_W2FC_RX0 56 |
620 |
# define OMAP24XX_DMA_USB_W2FC_TX1 57 |
621 |
# define OMAP24XX_DMA_USB_W2FC_RX1 58 |
622 |
# define OMAP24XX_DMA_USB_W2FC_TX2 59 |
623 |
# define OMAP24XX_DMA_USB_W2FC_RX2 60 |
624 |
# define OMAP24XX_DMA_MMC1_TX 61 |
625 |
# define OMAP24XX_DMA_MMC1_RX 62 |
626 |
# define OMAP24XX_DMA_MS 63 /* Not in OMAP2420 */ |
627 |
# define OMAP24XX_DMA_EXT_DMAREQ5 64 |
628 |
|
629 |
/* omap[123].c */
|
630 |
struct omap_mpu_timer_s;
|
631 |
struct omap_mpu_timer_s *omap_mpu_timer_init(target_phys_addr_t base,
|
632 |
qemu_irq irq, omap_clk clk); |
633 |
|
634 |
struct omap_gp_timer_s;
|
635 |
struct omap_gp_timer_s *omap_gp_timer_init(struct omap_target_agent_s *ta, |
636 |
qemu_irq irq, omap_clk fclk, omap_clk iclk); |
637 |
|
638 |
struct omap_watchdog_timer_s;
|
639 |
struct omap_watchdog_timer_s *omap_wd_timer_init(target_phys_addr_t base,
|
640 |
qemu_irq irq, omap_clk clk); |
641 |
|
642 |
struct omap_32khz_timer_s;
|
643 |
struct omap_32khz_timer_s *omap_os_timer_init(target_phys_addr_t base,
|
644 |
qemu_irq irq, omap_clk clk); |
645 |
|
646 |
void omap_synctimer_init(struct omap_target_agent_s *ta, |
647 |
struct omap_mpu_state_s *mpu, omap_clk fclk, omap_clk iclk);
|
648 |
|
649 |
struct omap_tipb_bridge_s;
|
650 |
struct omap_tipb_bridge_s *omap_tipb_bridge_init(target_phys_addr_t base,
|
651 |
qemu_irq abort_irq, omap_clk clk); |
652 |
|
653 |
struct omap_uart_s;
|
654 |
struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
|
655 |
qemu_irq irq, omap_clk fclk, omap_clk iclk, |
656 |
qemu_irq txdma, qemu_irq rxdma, CharDriverState *chr); |
657 |
struct omap_uart_s *omap2_uart_init(struct omap_target_agent_s *ta, |
658 |
qemu_irq irq, omap_clk fclk, omap_clk iclk, |
659 |
qemu_irq txdma, qemu_irq rxdma, CharDriverState *chr); |
660 |
void omap_uart_reset(struct omap_uart_s *s); |
661 |
void omap_uart_attach(struct omap_uart_s *s, CharDriverState *chr); |
662 |
|
663 |
struct omap_mpuio_s;
|
664 |
struct omap_mpuio_s *omap_mpuio_init(target_phys_addr_t base,
|
665 |
qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup, |
666 |
omap_clk clk); |
667 |
qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s);
|
668 |
void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler); |
669 |
void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down); |
670 |
|
671 |
struct omap_gpio_s;
|
672 |
struct omap_gpio_s *omap_gpio_init(target_phys_addr_t base,
|
673 |
qemu_irq irq, omap_clk clk); |
674 |
qemu_irq *omap_gpio_in_get(struct omap_gpio_s *s);
|
675 |
void omap_gpio_out_set(struct omap_gpio_s *s, int line, qemu_irq handler); |
676 |
|
677 |
struct omap_gpif_s;
|
678 |
struct omap_gpif_s *omap2_gpio_init(struct omap_target_agent_s *ta, |
679 |
qemu_irq *irq, omap_clk *fclk, omap_clk iclk, int modules);
|
680 |
qemu_irq *omap2_gpio_in_get(struct omap_gpif_s *s, int start); |
681 |
void omap2_gpio_out_set(struct omap_gpif_s *s, int line, qemu_irq handler); |
682 |
|
683 |
struct uWireSlave {
|
684 |
uint16_t (*receive)(void *opaque);
|
685 |
void (*send)(void *opaque, uint16_t data); |
686 |
void *opaque;
|
687 |
}; |
688 |
struct omap_uwire_s;
|
689 |
struct omap_uwire_s *omap_uwire_init(target_phys_addr_t base,
|
690 |
qemu_irq *irq, qemu_irq dma, omap_clk clk); |
691 |
void omap_uwire_attach(struct omap_uwire_s *s, |
692 |
uWireSlave *slave, int chipselect);
|
693 |
|
694 |
struct omap_mcspi_s;
|
695 |
struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum, |
696 |
qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk); |
697 |
void omap_mcspi_attach(struct omap_mcspi_s *s, |
698 |
uint32_t (*txrx)(void *opaque, uint32_t, int), void *opaque, |
699 |
int chipselect);
|
700 |
|
701 |
struct omap_rtc_s;
|
702 |
struct omap_rtc_s *omap_rtc_init(target_phys_addr_t base,
|
703 |
qemu_irq *irq, omap_clk clk); |
704 |
|
705 |
struct I2SCodec {
|
706 |
void *opaque;
|
707 |
|
708 |
/* The CPU can call this if it is generating the clock signal on the
|
709 |
* i2s port. The CODEC can ignore it if it is set up as a clock
|
710 |
* master and generates its own clock. */
|
711 |
void (*set_rate)(void *opaque, int in, int out); |
712 |
|
713 |
void (*tx_swallow)(void *opaque); |
714 |
qemu_irq rx_swallow; |
715 |
qemu_irq tx_start; |
716 |
|
717 |
int tx_rate;
|
718 |
int cts;
|
719 |
int rx_rate;
|
720 |
int rts;
|
721 |
|
722 |
struct i2s_fifo_s {
|
723 |
uint8_t *fifo; |
724 |
int len;
|
725 |
int start;
|
726 |
int size;
|
727 |
} in, out; |
728 |
}; |
729 |
struct omap_mcbsp_s;
|
730 |
struct omap_mcbsp_s *omap_mcbsp_init(target_phys_addr_t base,
|
731 |
qemu_irq *irq, qemu_irq *dma, omap_clk clk); |
732 |
void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, I2SCodec *slave); |
733 |
|
734 |
struct omap_lpg_s;
|
735 |
struct omap_lpg_s *omap_lpg_init(target_phys_addr_t base, omap_clk clk);
|
736 |
|
737 |
void omap_tap_init(struct omap_target_agent_s *ta, |
738 |
struct omap_mpu_state_s *mpu);
|
739 |
|
740 |
struct omap_eac_s;
|
741 |
struct omap_eac_s *omap_eac_init(struct omap_target_agent_s *ta, |
742 |
qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk); |
743 |
|
744 |
/* omap_lcdc.c */
|
745 |
struct omap_lcd_panel_s;
|
746 |
void omap_lcdc_reset(struct omap_lcd_panel_s *s); |
747 |
struct omap_lcd_panel_s *omap_lcdc_init(target_phys_addr_t base, qemu_irq irq,
|
748 |
struct omap_dma_lcd_channel_s *dma,
|
749 |
ram_addr_t imif_base, ram_addr_t emiff_base, omap_clk clk); |
750 |
|
751 |
/* omap_dss.c */
|
752 |
struct rfbi_chip_s {
|
753 |
void *opaque;
|
754 |
void (*write)(void *opaque, int dc, uint16_t value); |
755 |
void (*block)(void *opaque, int dc, void *buf, size_t len, int pitch); |
756 |
uint16_t (*read)(void *opaque, int dc); |
757 |
}; |
758 |
struct omap_dss_s;
|
759 |
void omap_dss_reset(struct omap_dss_s *s); |
760 |
struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta, |
761 |
target_phys_addr_t l3_base, |
762 |
qemu_irq irq, qemu_irq drq, |
763 |
omap_clk fck1, omap_clk fck2, omap_clk ck54m, |
764 |
omap_clk ick1, omap_clk ick2); |
765 |
void omap_rfbi_attach(struct omap_dss_s *s, int cs, struct rfbi_chip_s *chip); |
766 |
|
767 |
/* omap_mmc.c */
|
768 |
struct omap_mmc_s;
|
769 |
struct omap_mmc_s *omap_mmc_init(target_phys_addr_t base,
|
770 |
BlockDriverState *bd, |
771 |
qemu_irq irq, qemu_irq dma[], omap_clk clk); |
772 |
struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta, |
773 |
BlockDriverState *bd, qemu_irq irq, qemu_irq dma[], |
774 |
omap_clk fclk, omap_clk iclk); |
775 |
void omap_mmc_reset(struct omap_mmc_s *s); |
776 |
void omap_mmc_handlers(struct omap_mmc_s *s, qemu_irq ro, qemu_irq cover); |
777 |
void omap_mmc_enable(struct omap_mmc_s *s, int enable); |
778 |
|
779 |
/* omap_i2c.c */
|
780 |
struct omap_i2c_s;
|
781 |
struct omap_i2c_s *omap_i2c_init(target_phys_addr_t base,
|
782 |
qemu_irq irq, qemu_irq *dma, omap_clk clk); |
783 |
struct omap_i2c_s *omap2_i2c_init(struct omap_target_agent_s *ta, |
784 |
qemu_irq irq, qemu_irq *dma, omap_clk fclk, omap_clk iclk); |
785 |
void omap_i2c_reset(struct omap_i2c_s *s); |
786 |
i2c_bus *omap_i2c_bus(struct omap_i2c_s *s);
|
787 |
|
788 |
# define cpu_is_omap310(cpu) (cpu->mpu_model == omap310)
|
789 |
# define cpu_is_omap1510(cpu) (cpu->mpu_model == omap1510)
|
790 |
# define cpu_is_omap1610(cpu) (cpu->mpu_model == omap1610)
|
791 |
# define cpu_is_omap1710(cpu) (cpu->mpu_model == omap1710)
|
792 |
# define cpu_is_omap2410(cpu) (cpu->mpu_model == omap2410)
|
793 |
# define cpu_is_omap2420(cpu) (cpu->mpu_model == omap2420)
|
794 |
# define cpu_is_omap2430(cpu) (cpu->mpu_model == omap2430)
|
795 |
# define cpu_is_omap3430(cpu) (cpu->mpu_model == omap3430)
|
796 |
|
797 |
# define cpu_is_omap15xx(cpu) \
|
798 |
(cpu_is_omap310(cpu) || cpu_is_omap1510(cpu)) |
799 |
# define cpu_is_omap16xx(cpu) \
|
800 |
(cpu_is_omap1610(cpu) || cpu_is_omap1710(cpu)) |
801 |
# define cpu_is_omap24xx(cpu) \
|
802 |
(cpu_is_omap2410(cpu) || cpu_is_omap2420(cpu) || cpu_is_omap2430(cpu)) |
803 |
|
804 |
# define cpu_class_omap1(cpu) \
|
805 |
(cpu_is_omap15xx(cpu) || cpu_is_omap16xx(cpu)) |
806 |
# define cpu_class_omap2(cpu) cpu_is_omap24xx(cpu)
|
807 |
# define cpu_class_omap3(cpu) cpu_is_omap3430(cpu)
|
808 |
|
809 |
struct omap_mpu_state_s {
|
810 |
enum omap_mpu_model {
|
811 |
omap310, |
812 |
omap1510, |
813 |
omap1610, |
814 |
omap1710, |
815 |
omap2410, |
816 |
omap2420, |
817 |
omap2422, |
818 |
omap2423, |
819 |
omap2430, |
820 |
omap3430, |
821 |
} mpu_model; |
822 |
|
823 |
CPUState *env; |
824 |
|
825 |
qemu_irq *irq[2];
|
826 |
qemu_irq *drq; |
827 |
|
828 |
qemu_irq wakeup; |
829 |
|
830 |
struct omap_dma_port_if_s {
|
831 |
uint32_t (*read[3])(struct omap_mpu_state_s *s, |
832 |
target_phys_addr_t offset); |
833 |
void (*write[3])(struct omap_mpu_state_s *s, |
834 |
target_phys_addr_t offset, uint32_t value); |
835 |
int (*addr_valid)(struct omap_mpu_state_s *s, |
836 |
target_phys_addr_t addr); |
837 |
} port[__omap_dma_port_last]; |
838 |
|
839 |
unsigned long sdram_size; |
840 |
unsigned long sram_size; |
841 |
|
842 |
/* MPUI-TIPB peripherals */
|
843 |
struct omap_uart_s *uart[3]; |
844 |
|
845 |
struct omap_gpio_s *gpio;
|
846 |
|
847 |
struct omap_mcbsp_s *mcbsp1;
|
848 |
struct omap_mcbsp_s *mcbsp3;
|
849 |
|
850 |
/* MPU public TIPB peripherals */
|
851 |
struct omap_32khz_timer_s *os_timer;
|
852 |
|
853 |
struct omap_mmc_s *mmc;
|
854 |
|
855 |
struct omap_mpuio_s *mpuio;
|
856 |
|
857 |
struct omap_uwire_s *microwire;
|
858 |
|
859 |
struct {
|
860 |
uint8_t output; |
861 |
uint8_t level; |
862 |
uint8_t enable; |
863 |
int clk;
|
864 |
} pwl; |
865 |
|
866 |
struct {
|
867 |
uint8_t frc; |
868 |
uint8_t vrc; |
869 |
uint8_t gcr; |
870 |
omap_clk clk; |
871 |
} pwt; |
872 |
|
873 |
struct omap_i2c_s *i2c[2]; |
874 |
|
875 |
struct omap_rtc_s *rtc;
|
876 |
|
877 |
struct omap_mcbsp_s *mcbsp2;
|
878 |
|
879 |
struct omap_lpg_s *led[2]; |
880 |
|
881 |
/* MPU private TIPB peripherals */
|
882 |
struct omap_intr_handler_s *ih[2]; |
883 |
|
884 |
struct soc_dma_s *dma;
|
885 |
|
886 |
struct omap_mpu_timer_s *timer[3]; |
887 |
struct omap_watchdog_timer_s *wdt;
|
888 |
|
889 |
struct omap_lcd_panel_s *lcd;
|
890 |
|
891 |
uint32_t ulpd_pm_regs[21];
|
892 |
int64_t ulpd_gauge_start; |
893 |
|
894 |
uint32_t func_mux_ctrl[14];
|
895 |
uint32_t comp_mode_ctrl[1];
|
896 |
uint32_t pull_dwn_ctrl[4];
|
897 |
uint32_t gate_inh_ctrl[1];
|
898 |
uint32_t voltage_ctrl[1];
|
899 |
uint32_t test_dbg_ctrl[1];
|
900 |
uint32_t mod_conf_ctrl[1];
|
901 |
int compat1509;
|
902 |
|
903 |
uint32_t mpui_ctrl; |
904 |
|
905 |
struct omap_tipb_bridge_s *private_tipb;
|
906 |
struct omap_tipb_bridge_s *public_tipb;
|
907 |
|
908 |
uint32_t tcmi_regs[17];
|
909 |
|
910 |
struct dpll_ctl_s {
|
911 |
uint16_t mode; |
912 |
omap_clk dpll; |
913 |
} dpll[3];
|
914 |
|
915 |
omap_clk clks; |
916 |
struct {
|
917 |
int cold_start;
|
918 |
int clocking_scheme;
|
919 |
uint16_t arm_ckctl; |
920 |
uint16_t arm_idlect1; |
921 |
uint16_t arm_idlect2; |
922 |
uint16_t arm_ewupct; |
923 |
uint16_t arm_rstct1; |
924 |
uint16_t arm_rstct2; |
925 |
uint16_t arm_ckout1; |
926 |
int dpll1_mode;
|
927 |
uint16_t dsp_idlect1; |
928 |
uint16_t dsp_idlect2; |
929 |
uint16_t dsp_rstct2; |
930 |
} clkm; |
931 |
|
932 |
/* OMAP2-only peripherals */
|
933 |
struct omap_l4_s *l4;
|
934 |
|
935 |
struct omap_gp_timer_s *gptimer[12]; |
936 |
|
937 |
struct omap_synctimer_s {
|
938 |
uint32_t val; |
939 |
uint16_t readh; |
940 |
} synctimer; |
941 |
|
942 |
struct omap_prcm_s *prcm;
|
943 |
struct omap_sdrc_s *sdrc;
|
944 |
struct omap_gpmc_s *gpmc;
|
945 |
struct omap_sysctl_s *sysc;
|
946 |
|
947 |
struct omap_gpif_s *gpif;
|
948 |
|
949 |
struct omap_mcspi_s *mcspi[2]; |
950 |
|
951 |
struct omap_dss_s *dss;
|
952 |
|
953 |
struct omap_eac_s *eac;
|
954 |
}; |
955 |
|
956 |
/* omap1.c */
|
957 |
struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size, |
958 |
const char *core); |
959 |
|
960 |
/* omap2.c */
|
961 |
struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size, |
962 |
const char *core); |
963 |
|
964 |
# if TARGET_PHYS_ADDR_BITS == 32 |
965 |
# define OMAP_FMT_plx "%#08x" |
966 |
# elif TARGET_PHYS_ADDR_BITS == 64 |
967 |
# define OMAP_FMT_plx "%#08" PRIx64 |
968 |
# else
|
969 |
# error TARGET_PHYS_ADDR_BITS undefined
|
970 |
# endif
|
971 |
|
972 |
uint32_t omap_badwidth_read8(void *opaque, target_phys_addr_t addr);
|
973 |
void omap_badwidth_write8(void *opaque, target_phys_addr_t addr, |
974 |
uint32_t value); |
975 |
uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr);
|
976 |
void omap_badwidth_write16(void *opaque, target_phys_addr_t addr, |
977 |
uint32_t value); |
978 |
uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr);
|
979 |
void omap_badwidth_write32(void *opaque, target_phys_addr_t addr, |
980 |
uint32_t value); |
981 |
|
982 |
void omap_mpu_wakeup(void *opaque, int irq, int req); |
983 |
|
984 |
# define OMAP_BAD_REG(paddr) \
|
985 |
fprintf(stderr, "%s: Bad register " OMAP_FMT_plx "\n", \ |
986 |
__FUNCTION__, paddr) |
987 |
# define OMAP_RO_REG(paddr) \
|
988 |
fprintf(stderr, "%s: Read-only register " OMAP_FMT_plx "\n", \ |
989 |
__FUNCTION__, paddr) |
990 |
|
991 |
/* OMAP-specific Linux bootloader tags for the ATAG_BOARD area
|
992 |
(Board-specifc tags are not here) */
|
993 |
#define OMAP_TAG_CLOCK 0x4f01 |
994 |
#define OMAP_TAG_MMC 0x4f02 |
995 |
#define OMAP_TAG_SERIAL_CONSOLE 0x4f03 |
996 |
#define OMAP_TAG_USB 0x4f04 |
997 |
#define OMAP_TAG_LCD 0x4f05 |
998 |
#define OMAP_TAG_GPIO_SWITCH 0x4f06 |
999 |
#define OMAP_TAG_UART 0x4f07 |
1000 |
#define OMAP_TAG_FBMEM 0x4f08 |
1001 |
#define OMAP_TAG_STI_CONSOLE 0x4f09 |
1002 |
#define OMAP_TAG_CAMERA_SENSOR 0x4f0a |
1003 |
#define OMAP_TAG_PARTITION 0x4f0b |
1004 |
#define OMAP_TAG_TEA5761 0x4f10 |
1005 |
#define OMAP_TAG_TMP105 0x4f11 |
1006 |
#define OMAP_TAG_BOOT_REASON 0x4f80 |
1007 |
#define OMAP_TAG_FLASH_PART_STR 0x4f81 |
1008 |
#define OMAP_TAG_VERSION_STR 0x4f82 |
1009 |
|
1010 |
enum {
|
1011 |
OMAP_GPIOSW_TYPE_COVER = 0 << 4, |
1012 |
OMAP_GPIOSW_TYPE_CONNECTION = 1 << 4, |
1013 |
OMAP_GPIOSW_TYPE_ACTIVITY = 2 << 4, |
1014 |
}; |
1015 |
|
1016 |
#define OMAP_GPIOSW_INVERTED 0x0001 |
1017 |
#define OMAP_GPIOSW_OUTPUT 0x0002 |
1018 |
|
1019 |
# define TCMI_VERBOSE 1 |
1020 |
//# define MEM_VERBOSE 1
|
1021 |
|
1022 |
# ifdef TCMI_VERBOSE
|
1023 |
# define OMAP_8B_REG(paddr) \
|
1024 |
fprintf(stderr, "%s: 8-bit register " OMAP_FMT_plx "\n", \ |
1025 |
__FUNCTION__, paddr) |
1026 |
# define OMAP_16B_REG(paddr) \
|
1027 |
fprintf(stderr, "%s: 16-bit register " OMAP_FMT_plx "\n", \ |
1028 |
__FUNCTION__, paddr) |
1029 |
# define OMAP_32B_REG(paddr) \
|
1030 |
fprintf(stderr, "%s: 32-bit register " OMAP_FMT_plx "\n", \ |
1031 |
__FUNCTION__, paddr) |
1032 |
# else
|
1033 |
# define OMAP_8B_REG(paddr)
|
1034 |
# define OMAP_16B_REG(paddr)
|
1035 |
# define OMAP_32B_REG(paddr)
|
1036 |
# endif
|
1037 |
|
1038 |
# define OMAP_MPUI_REG_MASK 0x000007ff |
1039 |
|
1040 |
# ifdef MEM_VERBOSE
|
1041 |
struct io_fn {
|
1042 |
CPUReadMemoryFunc **mem_read; |
1043 |
CPUWriteMemoryFunc **mem_write; |
1044 |
void *opaque;
|
1045 |
int in;
|
1046 |
}; |
1047 |
|
1048 |
static uint32_t io_readb(void *opaque, target_phys_addr_t addr) |
1049 |
{ |
1050 |
struct io_fn *s = opaque;
|
1051 |
uint32_t ret; |
1052 |
|
1053 |
s->in ++; |
1054 |
ret = s->mem_read[0](s->opaque, addr);
|
1055 |
s->in --; |
1056 |
if (!s->in)
|
1057 |
fprintf(stderr, "%08x ---> %02x\n", (uint32_t) addr, ret);
|
1058 |
return ret;
|
1059 |
} |
1060 |
static uint32_t io_readh(void *opaque, target_phys_addr_t addr) |
1061 |
{ |
1062 |
struct io_fn *s = opaque;
|
1063 |
uint32_t ret; |
1064 |
|
1065 |
s->in ++; |
1066 |
ret = s->mem_read[1](s->opaque, addr);
|
1067 |
s->in --; |
1068 |
if (!s->in)
|
1069 |
fprintf(stderr, "%08x ---> %04x\n", (uint32_t) addr, ret);
|
1070 |
return ret;
|
1071 |
} |
1072 |
static uint32_t io_readw(void *opaque, target_phys_addr_t addr) |
1073 |
{ |
1074 |
struct io_fn *s = opaque;
|
1075 |
uint32_t ret; |
1076 |
|
1077 |
s->in ++; |
1078 |
ret = s->mem_read[2](s->opaque, addr);
|
1079 |
s->in --; |
1080 |
if (!s->in)
|
1081 |
fprintf(stderr, "%08x ---> %08x\n", (uint32_t) addr, ret);
|
1082 |
return ret;
|
1083 |
} |
1084 |
static void io_writeb(void *opaque, target_phys_addr_t addr, uint32_t value) |
1085 |
{ |
1086 |
struct io_fn *s = opaque;
|
1087 |
|
1088 |
if (!s->in)
|
1089 |
fprintf(stderr, "%08x <--- %02x\n", (uint32_t) addr, value);
|
1090 |
s->in ++; |
1091 |
s->mem_write[0](s->opaque, addr, value);
|
1092 |
s->in --; |
1093 |
} |
1094 |
static void io_writeh(void *opaque, target_phys_addr_t addr, uint32_t value) |
1095 |
{ |
1096 |
struct io_fn *s = opaque;
|
1097 |
|
1098 |
if (!s->in)
|
1099 |
fprintf(stderr, "%08x <--- %04x\n", (uint32_t) addr, value);
|
1100 |
s->in ++; |
1101 |
s->mem_write[1](s->opaque, addr, value);
|
1102 |
s->in --; |
1103 |
} |
1104 |
static void io_writew(void *opaque, target_phys_addr_t addr, uint32_t value) |
1105 |
{ |
1106 |
struct io_fn *s = opaque;
|
1107 |
|
1108 |
if (!s->in)
|
1109 |
fprintf(stderr, "%08x <--- %08x\n", (uint32_t) addr, value);
|
1110 |
s->in ++; |
1111 |
s->mem_write[2](s->opaque, addr, value);
|
1112 |
s->in --; |
1113 |
} |
1114 |
|
1115 |
static CPUReadMemoryFunc *io_readfn[] = { io_readb, io_readh, io_readw, };
|
1116 |
static CPUWriteMemoryFunc *io_writefn[] = { io_writeb, io_writeh, io_writew, };
|
1117 |
|
1118 |
inline static int debug_register_io_memory( |
1119 |
CPUReadMemoryFunc **mem_read, CPUWriteMemoryFunc **mem_write, |
1120 |
void *opaque)
|
1121 |
{ |
1122 |
struct io_fn *s = qemu_malloc(sizeof(struct io_fn)); |
1123 |
|
1124 |
s->mem_read = mem_read; |
1125 |
s->mem_write = mem_write; |
1126 |
s->opaque = opaque; |
1127 |
s->in = 0;
|
1128 |
return cpu_register_io_memory(io_readfn, io_writefn, s);
|
1129 |
} |
1130 |
# define cpu_register_io_memory debug_register_io_memory
|
1131 |
# endif
|
1132 |
|
1133 |
/* Define when we want to reduce the number of IO regions registered. */
|
1134 |
/*# define L4_MUX_HACK*/
|
1135 |
|
1136 |
# ifdef L4_MUX_HACK
|
1137 |
# undef l4_register_io_memory
|
1138 |
int l4_register_io_memory(CPUReadMemoryFunc **mem_read,
|
1139 |
CPUWriteMemoryFunc **mem_write, void *opaque);
|
1140 |
# endif
|
1141 |
|
1142 |
#endif /* hw_omap_h */ |