root / hw / mips_mipssim.c @ 7b9cbadb
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1 | f0fc6f8f | ths | /*
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2 | f0fc6f8f | ths | * QEMU/mipssim emulation
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3 | f0fc6f8f | ths | *
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4 | f0fc6f8f | ths | * Emulates a very simple machine model similiar to the one use by the
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5 | f0fc6f8f | ths | * proprietary MIPS emulator.
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6 | a79ee211 | ths | *
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7 | a79ee211 | ths | * Copyright (c) 2007 Thiemo Seufer
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8 | a79ee211 | ths | *
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9 | a79ee211 | ths | * Permission is hereby granted, free of charge, to any person obtaining a copy
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10 | a79ee211 | ths | * of this software and associated documentation files (the "Software"), to deal
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11 | a79ee211 | ths | * in the Software without restriction, including without limitation the rights
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12 | a79ee211 | ths | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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13 | a79ee211 | ths | * copies of the Software, and to permit persons to whom the Software is
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14 | a79ee211 | ths | * furnished to do so, subject to the following conditions:
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15 | a79ee211 | ths | *
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16 | a79ee211 | ths | * The above copyright notice and this permission notice shall be included in
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17 | a79ee211 | ths | * all copies or substantial portions of the Software.
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18 | a79ee211 | ths | *
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19 | a79ee211 | ths | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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20 | a79ee211 | ths | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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21 | a79ee211 | ths | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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22 | a79ee211 | ths | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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23 | a79ee211 | ths | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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24 | a79ee211 | ths | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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25 | a79ee211 | ths | * THE SOFTWARE.
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26 | f0fc6f8f | ths | */
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27 | 87ecb68b | pbrook | #include "hw.h" |
28 | 87ecb68b | pbrook | #include "mips.h" |
29 | 87ecb68b | pbrook | #include "pc.h" |
30 | 87ecb68b | pbrook | #include "isa.h" |
31 | 87ecb68b | pbrook | #include "net.h" |
32 | 87ecb68b | pbrook | #include "sysemu.h" |
33 | 87ecb68b | pbrook | #include "boards.h" |
34 | bba831e8 | Paul Brook | #include "mips-bios.h" |
35 | ca20cf32 | Blue Swirl | #include "loader.h" |
36 | ca20cf32 | Blue Swirl | #include "elf.h" |
37 | f0fc6f8f | ths | |
38 | f0fc6f8f | ths | #ifdef TARGET_MIPS64
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39 | f0fc6f8f | ths | #define PHYS_TO_VIRT(x) ((x) | ~0x7fffffffULL) |
40 | f0fc6f8f | ths | #else
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41 | f0fc6f8f | ths | #define PHYS_TO_VIRT(x) ((x) | ~0x7fffffffU) |
42 | f0fc6f8f | ths | #endif
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43 | f0fc6f8f | ths | |
44 | f0fc6f8f | ths | #define VIRT_TO_PHYS_ADDEND (-((int64_t)(int32_t)0x80000000)) |
45 | f0fc6f8f | ths | |
46 | 7df526e3 | ths | static struct _loaderparams { |
47 | 7df526e3 | ths | int ram_size;
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48 | 7df526e3 | ths | const char *kernel_filename; |
49 | 7df526e3 | ths | const char *kernel_cmdline; |
50 | 7df526e3 | ths | const char *initrd_filename; |
51 | 7df526e3 | ths | } loaderparams; |
52 | 7df526e3 | ths | |
53 | e16ad5b0 | Aurelien Jarno | typedef struct ResetData { |
54 | e16ad5b0 | Aurelien Jarno | CPUState *env; |
55 | e16ad5b0 | Aurelien Jarno | uint64_t vector; |
56 | e16ad5b0 | Aurelien Jarno | } ResetData; |
57 | e16ad5b0 | Aurelien Jarno | |
58 | e16ad5b0 | Aurelien Jarno | static int64_t load_kernel(void) |
59 | f0fc6f8f | ths | { |
60 | f0fc6f8f | ths | int64_t entry, kernel_low, kernel_high; |
61 | f0fc6f8f | ths | long kernel_size;
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62 | f0fc6f8f | ths | long initrd_size;
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63 | c227f099 | Anthony Liguori | ram_addr_t initrd_offset; |
64 | ca20cf32 | Blue Swirl | int big_endian;
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65 | ca20cf32 | Blue Swirl | |
66 | ca20cf32 | Blue Swirl | #ifdef TARGET_WORDS_BIGENDIAN
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67 | ca20cf32 | Blue Swirl | big_endian = 1;
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68 | ca20cf32 | Blue Swirl | #else
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69 | ca20cf32 | Blue Swirl | big_endian = 0;
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70 | ca20cf32 | Blue Swirl | #endif
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71 | f0fc6f8f | ths | |
72 | 7df526e3 | ths | kernel_size = load_elf(loaderparams.kernel_filename, VIRT_TO_PHYS_ADDEND, |
73 | b55266b5 | blueswir1 | (uint64_t *)&entry, (uint64_t *)&kernel_low, |
74 | ca20cf32 | Blue Swirl | (uint64_t *)&kernel_high, big_endian, ELF_MACHINE, 1);
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75 | f0fc6f8f | ths | if (kernel_size >= 0) { |
76 | f0fc6f8f | ths | if ((entry & ~0x7fffffffULL) == 0x80000000) |
77 | f0fc6f8f | ths | entry = (int32_t)entry; |
78 | f0fc6f8f | ths | } else {
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79 | f0fc6f8f | ths | fprintf(stderr, "qemu: could not load kernel '%s'\n",
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80 | 7df526e3 | ths | loaderparams.kernel_filename); |
81 | f0fc6f8f | ths | exit(1);
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82 | f0fc6f8f | ths | } |
83 | f0fc6f8f | ths | |
84 | f0fc6f8f | ths | /* load initrd */
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85 | f0fc6f8f | ths | initrd_size = 0;
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86 | f0fc6f8f | ths | initrd_offset = 0;
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87 | 7df526e3 | ths | if (loaderparams.initrd_filename) {
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88 | 7df526e3 | ths | initrd_size = get_image_size (loaderparams.initrd_filename); |
89 | f0fc6f8f | ths | if (initrd_size > 0) { |
90 | f0fc6f8f | ths | initrd_offset = (kernel_high + ~TARGET_PAGE_MASK) & TARGET_PAGE_MASK; |
91 | 7df526e3 | ths | if (initrd_offset + initrd_size > loaderparams.ram_size) {
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92 | f0fc6f8f | ths | fprintf(stderr, |
93 | f0fc6f8f | ths | "qemu: memory too small for initial ram disk '%s'\n",
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94 | 7df526e3 | ths | loaderparams.initrd_filename); |
95 | f0fc6f8f | ths | exit(1);
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96 | f0fc6f8f | ths | } |
97 | dcac9679 | pbrook | initrd_size = load_image_targphys(loaderparams.initrd_filename, |
98 | dcac9679 | pbrook | initrd_offset, loaderparams.ram_size - initrd_offset); |
99 | f0fc6f8f | ths | } |
100 | f0fc6f8f | ths | if (initrd_size == (target_ulong) -1) { |
101 | f0fc6f8f | ths | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
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102 | 7df526e3 | ths | loaderparams.initrd_filename); |
103 | f0fc6f8f | ths | exit(1);
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104 | f0fc6f8f | ths | } |
105 | f0fc6f8f | ths | } |
106 | e16ad5b0 | Aurelien Jarno | return entry;
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107 | f0fc6f8f | ths | } |
108 | f0fc6f8f | ths | |
109 | f0fc6f8f | ths | static void main_cpu_reset(void *opaque) |
110 | f0fc6f8f | ths | { |
111 | e16ad5b0 | Aurelien Jarno | ResetData *s = (ResetData *)opaque; |
112 | e16ad5b0 | Aurelien Jarno | CPUState *env = s->env; |
113 | f0fc6f8f | ths | |
114 | e16ad5b0 | Aurelien Jarno | cpu_reset(env); |
115 | e16ad5b0 | Aurelien Jarno | env->active_tc.PC = s->vector; |
116 | f0fc6f8f | ths | } |
117 | f0fc6f8f | ths | |
118 | f0fc6f8f | ths | static void |
119 | c227f099 | Anthony Liguori | mips_mipssim_init (ram_addr_t ram_size, |
120 | 3023f332 | aliguori | const char *boot_device, |
121 | f0fc6f8f | ths | const char *kernel_filename, const char *kernel_cmdline, |
122 | f0fc6f8f | ths | const char *initrd_filename, const char *cpu_model) |
123 | f0fc6f8f | ths | { |
124 | 5cea8590 | Paul Brook | char *filename;
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125 | c227f099 | Anthony Liguori | ram_addr_t ram_offset; |
126 | c227f099 | Anthony Liguori | ram_addr_t bios_offset; |
127 | f0fc6f8f | ths | CPUState *env; |
128 | e16ad5b0 | Aurelien Jarno | ResetData *reset_info; |
129 | b5334159 | ths | int bios_size;
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130 | f0fc6f8f | ths | |
131 | f0fc6f8f | ths | /* Init CPUs. */
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132 | f0fc6f8f | ths | if (cpu_model == NULL) { |
133 | f0fc6f8f | ths | #ifdef TARGET_MIPS64
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134 | f0fc6f8f | ths | cpu_model = "5Kf";
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135 | f0fc6f8f | ths | #else
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136 | f0fc6f8f | ths | cpu_model = "24Kf";
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137 | f0fc6f8f | ths | #endif
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138 | f0fc6f8f | ths | } |
139 | aaed909a | bellard | env = cpu_init(cpu_model); |
140 | aaed909a | bellard | if (!env) {
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141 | aaed909a | bellard | fprintf(stderr, "Unable to find CPU definition\n");
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142 | aaed909a | bellard | exit(1);
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143 | aaed909a | bellard | } |
144 | e16ad5b0 | Aurelien Jarno | reset_info = qemu_mallocz(sizeof(ResetData));
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145 | e16ad5b0 | Aurelien Jarno | reset_info->env = env; |
146 | e16ad5b0 | Aurelien Jarno | reset_info->vector = env->active_tc.PC; |
147 | e16ad5b0 | Aurelien Jarno | qemu_register_reset(main_cpu_reset, reset_info); |
148 | f0fc6f8f | ths | |
149 | f0fc6f8f | ths | /* Allocate RAM. */
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150 | dcac9679 | pbrook | ram_offset = qemu_ram_alloc(ram_size); |
151 | dcac9679 | pbrook | bios_offset = qemu_ram_alloc(BIOS_SIZE); |
152 | f0fc6f8f | ths | |
153 | dcac9679 | pbrook | cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);
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154 | dcac9679 | pbrook | |
155 | dcac9679 | pbrook | /* Map the BIOS / boot exception handler. */
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156 | dcac9679 | pbrook | cpu_register_physical_memory(0x1fc00000LL,
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157 | dcac9679 | pbrook | BIOS_SIZE, bios_offset | IO_MEM_ROM); |
158 | f0fc6f8f | ths | /* Load a BIOS / boot exception handler image. */
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159 | f0fc6f8f | ths | if (bios_name == NULL) |
160 | f0fc6f8f | ths | bios_name = BIOS_FILENAME; |
161 | 5cea8590 | Paul Brook | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
162 | 5cea8590 | Paul Brook | if (filename) {
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163 | 5cea8590 | Paul Brook | bios_size = load_image_targphys(filename, 0x1fc00000LL, BIOS_SIZE);
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164 | 5cea8590 | Paul Brook | qemu_free(filename); |
165 | 5cea8590 | Paul Brook | } else {
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166 | 5cea8590 | Paul Brook | bios_size = -1;
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167 | 5cea8590 | Paul Brook | } |
168 | b5334159 | ths | if ((bios_size < 0 || bios_size > BIOS_SIZE) && !kernel_filename) { |
169 | f0fc6f8f | ths | /* Bail out if we have neither a kernel image nor boot vector code. */
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170 | f0fc6f8f | ths | fprintf(stderr, |
171 | f0fc6f8f | ths | "qemu: Could not load MIPS bios '%s', and no -kernel argument was specified\n",
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172 | 5cea8590 | Paul Brook | filename); |
173 | f0fc6f8f | ths | exit(1);
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174 | f0fc6f8f | ths | } else {
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175 | b5334159 | ths | /* We have a boot vector start address. */
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176 | b5dc7732 | ths | env->active_tc.PC = (target_long)(int32_t)0xbfc00000;
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177 | f0fc6f8f | ths | } |
178 | f0fc6f8f | ths | |
179 | f0fc6f8f | ths | if (kernel_filename) {
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180 | 7df526e3 | ths | loaderparams.ram_size = ram_size; |
181 | 7df526e3 | ths | loaderparams.kernel_filename = kernel_filename; |
182 | 7df526e3 | ths | loaderparams.kernel_cmdline = kernel_cmdline; |
183 | 7df526e3 | ths | loaderparams.initrd_filename = initrd_filename; |
184 | e16ad5b0 | Aurelien Jarno | reset_info->vector = load_kernel(); |
185 | f0fc6f8f | ths | } |
186 | f0fc6f8f | ths | |
187 | f0fc6f8f | ths | /* Init CPU internal devices. */
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188 | f0fc6f8f | ths | cpu_mips_irq_init_cpu(env); |
189 | f0fc6f8f | ths | cpu_mips_clock_init(env); |
190 | f0fc6f8f | ths | |
191 | f0fc6f8f | ths | /* Register 64 KB of ISA IO space at 0x1fd00000. */
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192 | f0fc6f8f | ths | isa_mmio_init(0x1fd00000, 0x00010000); |
193 | f0fc6f8f | ths | |
194 | f0fc6f8f | ths | /* A single 16450 sits at offset 0x3f8. It is attached to
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195 | f0fc6f8f | ths | MIPS CPU INT2, which is interrupt 4. */
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196 | f0fc6f8f | ths | if (serial_hds[0]) |
197 | b6cd0ea1 | aurel32 | serial_init(0x3f8, env->irq[4], 115200, serial_hds[0]); |
198 | f0fc6f8f | ths | |
199 | 0ae18cee | aliguori | if (nd_table[0].vlan) |
200 | 0ae18cee | aliguori | /* MIPSnet uses the MIPS CPU INT0, which is interrupt 2. */
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201 | 0ae18cee | aliguori | mipsnet_init(0x4200, env->irq[2], &nd_table[0]); |
202 | f0fc6f8f | ths | } |
203 | f0fc6f8f | ths | |
204 | f80f9ec9 | Anthony Liguori | static QEMUMachine mips_mipssim_machine = {
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205 | eec2743e | ths | .name = "mipssim",
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206 | eec2743e | ths | .desc = "MIPS MIPSsim platform",
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207 | eec2743e | ths | .init = mips_mipssim_init, |
208 | f0fc6f8f | ths | }; |
209 | f80f9ec9 | Anthony Liguori | |
210 | f80f9ec9 | Anthony Liguori | static void mips_mipssim_machine_init(void) |
211 | f80f9ec9 | Anthony Liguori | { |
212 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&mips_mipssim_machine); |
213 | f80f9ec9 | Anthony Liguori | } |
214 | f80f9ec9 | Anthony Liguori | |
215 | f80f9ec9 | Anthony Liguori | machine_init(mips_mipssim_machine_init); |