root / hw / mcf5208.c @ 7ba1e619
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1 | 5fafdf24 | ths | /*
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2 | 20dcee94 | pbrook | * Motorola ColdFire MCF5208 SoC emulation.
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3 | 20dcee94 | pbrook | *
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4 | 20dcee94 | pbrook | * Copyright (c) 2007 CodeSourcery.
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5 | 20dcee94 | pbrook | *
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6 | 20dcee94 | pbrook | * This code is licenced under the GPL
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7 | 20dcee94 | pbrook | */
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8 | 87ecb68b | pbrook | #include "hw.h" |
9 | 87ecb68b | pbrook | #include "mcf.h" |
10 | 87ecb68b | pbrook | #include "qemu-timer.h" |
11 | 87ecb68b | pbrook | #include "sysemu.h" |
12 | 87ecb68b | pbrook | #include "net.h" |
13 | 87ecb68b | pbrook | #include "boards.h" |
14 | 20dcee94 | pbrook | |
15 | 20dcee94 | pbrook | #define SYS_FREQ 66000000 |
16 | 20dcee94 | pbrook | |
17 | 20dcee94 | pbrook | #define PCSR_EN 0x0001 |
18 | 20dcee94 | pbrook | #define PCSR_RLD 0x0002 |
19 | 20dcee94 | pbrook | #define PCSR_PIF 0x0004 |
20 | 20dcee94 | pbrook | #define PCSR_PIE 0x0008 |
21 | 20dcee94 | pbrook | #define PCSR_OVW 0x0010 |
22 | 20dcee94 | pbrook | #define PCSR_DBG 0x0020 |
23 | 20dcee94 | pbrook | #define PCSR_DOZE 0x0040 |
24 | 20dcee94 | pbrook | #define PCSR_PRE_SHIFT 8 |
25 | 20dcee94 | pbrook | #define PCSR_PRE_MASK 0x0f00 |
26 | 20dcee94 | pbrook | |
27 | 20dcee94 | pbrook | typedef struct { |
28 | 20dcee94 | pbrook | qemu_irq irq; |
29 | 20dcee94 | pbrook | ptimer_state *timer; |
30 | 20dcee94 | pbrook | uint16_t pcsr; |
31 | 20dcee94 | pbrook | uint16_t pmr; |
32 | 20dcee94 | pbrook | uint16_t pcntr; |
33 | 20dcee94 | pbrook | } m5208_timer_state; |
34 | 20dcee94 | pbrook | |
35 | 20dcee94 | pbrook | static void m5208_timer_update(m5208_timer_state *s) |
36 | 20dcee94 | pbrook | { |
37 | 20dcee94 | pbrook | if ((s->pcsr & (PCSR_PIE | PCSR_PIF)) == (PCSR_PIE | PCSR_PIF))
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38 | 20dcee94 | pbrook | qemu_irq_raise(s->irq); |
39 | 20dcee94 | pbrook | else
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40 | 20dcee94 | pbrook | qemu_irq_lower(s->irq); |
41 | 20dcee94 | pbrook | } |
42 | 20dcee94 | pbrook | |
43 | 20dcee94 | pbrook | static void m5208_timer_write(m5208_timer_state *s, int offset, |
44 | 20dcee94 | pbrook | uint32_t value) |
45 | 20dcee94 | pbrook | { |
46 | 20dcee94 | pbrook | int prescale;
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47 | 20dcee94 | pbrook | int limit;
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48 | 20dcee94 | pbrook | switch (offset) {
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49 | 20dcee94 | pbrook | case 0: |
50 | 20dcee94 | pbrook | /* The PIF bit is set-to-clear. */
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51 | 20dcee94 | pbrook | if (value & PCSR_PIF) {
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52 | 20dcee94 | pbrook | s->pcsr &= ~PCSR_PIF; |
53 | 20dcee94 | pbrook | value &= ~PCSR_PIF; |
54 | 20dcee94 | pbrook | } |
55 | 20dcee94 | pbrook | /* Avoid frobbing the timer if we're just twiddling IRQ bits. */
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56 | 20dcee94 | pbrook | if (((s->pcsr ^ value) & ~PCSR_PIE) == 0) { |
57 | 20dcee94 | pbrook | s->pcsr = value; |
58 | 20dcee94 | pbrook | m5208_timer_update(s); |
59 | 20dcee94 | pbrook | return;
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60 | 20dcee94 | pbrook | } |
61 | 20dcee94 | pbrook | |
62 | 20dcee94 | pbrook | if (s->pcsr & PCSR_EN)
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63 | 20dcee94 | pbrook | ptimer_stop(s->timer); |
64 | 20dcee94 | pbrook | |
65 | 20dcee94 | pbrook | s->pcsr = value; |
66 | 20dcee94 | pbrook | |
67 | 20dcee94 | pbrook | prescale = 1 << ((s->pcsr & PCSR_PRE_MASK) >> PCSR_PRE_SHIFT);
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68 | 20dcee94 | pbrook | ptimer_set_freq(s->timer, (SYS_FREQ / 2) / prescale);
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69 | 20dcee94 | pbrook | if (s->pcsr & PCSR_RLD)
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70 | 20dcee94 | pbrook | limit = s->pmr; |
71 | 6d9db39c | pbrook | else
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72 | 6d9db39c | pbrook | limit = 0xffff;
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73 | 20dcee94 | pbrook | ptimer_set_limit(s->timer, limit, 0);
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74 | 20dcee94 | pbrook | |
75 | 20dcee94 | pbrook | if (s->pcsr & PCSR_EN)
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76 | 20dcee94 | pbrook | ptimer_run(s->timer, 0);
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77 | 20dcee94 | pbrook | break;
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78 | 20dcee94 | pbrook | case 2: |
79 | 20dcee94 | pbrook | s->pmr = value; |
80 | 20dcee94 | pbrook | s->pcsr &= ~PCSR_PIF; |
81 | 6d9db39c | pbrook | if ((s->pcsr & PCSR_RLD) == 0) { |
82 | 6d9db39c | pbrook | if (s->pcsr & PCSR_OVW)
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83 | 6d9db39c | pbrook | ptimer_set_count(s->timer, value); |
84 | 6d9db39c | pbrook | } else {
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85 | 6d9db39c | pbrook | ptimer_set_limit(s->timer, value, s->pcsr & PCSR_OVW); |
86 | 6d9db39c | pbrook | } |
87 | 20dcee94 | pbrook | break;
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88 | 20dcee94 | pbrook | case 4: |
89 | 20dcee94 | pbrook | break;
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90 | 20dcee94 | pbrook | default:
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91 | 20dcee94 | pbrook | /* Should never happen. */
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92 | 20dcee94 | pbrook | abort(); |
93 | 20dcee94 | pbrook | } |
94 | 20dcee94 | pbrook | m5208_timer_update(s); |
95 | 20dcee94 | pbrook | } |
96 | 20dcee94 | pbrook | |
97 | 20dcee94 | pbrook | static void m5208_timer_trigger(void *opaque) |
98 | 20dcee94 | pbrook | { |
99 | 20dcee94 | pbrook | m5208_timer_state *s = (m5208_timer_state *)opaque; |
100 | 20dcee94 | pbrook | s->pcsr |= PCSR_PIF; |
101 | 20dcee94 | pbrook | m5208_timer_update(s); |
102 | 20dcee94 | pbrook | } |
103 | 20dcee94 | pbrook | |
104 | 20dcee94 | pbrook | typedef struct { |
105 | 20dcee94 | pbrook | m5208_timer_state timer[2];
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106 | 20dcee94 | pbrook | } m5208_sys_state; |
107 | 20dcee94 | pbrook | |
108 | 20dcee94 | pbrook | static uint32_t m5208_sys_read(void *opaque, target_phys_addr_t addr) |
109 | 20dcee94 | pbrook | { |
110 | 20dcee94 | pbrook | m5208_sys_state *s = (m5208_sys_state *)opaque; |
111 | 20dcee94 | pbrook | switch (addr) {
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112 | 20dcee94 | pbrook | /* PIT0 */
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113 | 20dcee94 | pbrook | case 0xfc080000: |
114 | 20dcee94 | pbrook | return s->timer[0].pcsr; |
115 | 20dcee94 | pbrook | case 0xfc080002: |
116 | 20dcee94 | pbrook | return s->timer[0].pmr; |
117 | 20dcee94 | pbrook | case 0xfc080004: |
118 | 20dcee94 | pbrook | return ptimer_get_count(s->timer[0].timer); |
119 | 20dcee94 | pbrook | /* PIT1 */
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120 | 20dcee94 | pbrook | case 0xfc084000: |
121 | 20dcee94 | pbrook | return s->timer[1].pcsr; |
122 | 20dcee94 | pbrook | case 0xfc084002: |
123 | 20dcee94 | pbrook | return s->timer[1].pmr; |
124 | 20dcee94 | pbrook | case 0xfc084004: |
125 | 20dcee94 | pbrook | return ptimer_get_count(s->timer[1].timer); |
126 | 20dcee94 | pbrook | |
127 | 20dcee94 | pbrook | /* SDRAM Controller. */
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128 | 20dcee94 | pbrook | case 0xfc0a8110: /* SDCS0 */ |
129 | 20dcee94 | pbrook | { |
130 | 20dcee94 | pbrook | int n;
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131 | 20dcee94 | pbrook | for (n = 0; n < 32; n++) { |
132 | 20dcee94 | pbrook | if (ram_size < (2u << n)) |
133 | 20dcee94 | pbrook | break;
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134 | 20dcee94 | pbrook | } |
135 | 20dcee94 | pbrook | return (n - 1) | 0x40000000; |
136 | 20dcee94 | pbrook | } |
137 | 20dcee94 | pbrook | case 0xfc0a8114: /* SDCS1 */ |
138 | 20dcee94 | pbrook | return 0; |
139 | 20dcee94 | pbrook | |
140 | 20dcee94 | pbrook | default:
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141 | 20dcee94 | pbrook | cpu_abort(cpu_single_env, "m5208_sys_read: Bad offset 0x%x\n",
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142 | 20dcee94 | pbrook | (int)addr);
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143 | 20dcee94 | pbrook | return 0; |
144 | 20dcee94 | pbrook | } |
145 | 20dcee94 | pbrook | } |
146 | 20dcee94 | pbrook | |
147 | 20dcee94 | pbrook | static void m5208_sys_write(void *opaque, target_phys_addr_t addr, |
148 | 20dcee94 | pbrook | uint32_t value) |
149 | 20dcee94 | pbrook | { |
150 | 20dcee94 | pbrook | m5208_sys_state *s = (m5208_sys_state *)opaque; |
151 | 20dcee94 | pbrook | switch (addr) {
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152 | 20dcee94 | pbrook | /* PIT0 */
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153 | 20dcee94 | pbrook | case 0xfc080000: |
154 | 20dcee94 | pbrook | case 0xfc080002: |
155 | 20dcee94 | pbrook | case 0xfc080004: |
156 | 20dcee94 | pbrook | m5208_timer_write(&s->timer[0], addr & 0xf, value); |
157 | 20dcee94 | pbrook | return;
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158 | 20dcee94 | pbrook | /* PIT1 */
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159 | 20dcee94 | pbrook | case 0xfc084000: |
160 | 20dcee94 | pbrook | case 0xfc084002: |
161 | 20dcee94 | pbrook | case 0xfc084004: |
162 | 20dcee94 | pbrook | m5208_timer_write(&s->timer[1], addr & 0xf, value); |
163 | 20dcee94 | pbrook | return;
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164 | 20dcee94 | pbrook | default:
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165 | 20dcee94 | pbrook | cpu_abort(cpu_single_env, "m5208_sys_write: Bad offset 0x%x\n",
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166 | 20dcee94 | pbrook | (int)addr);
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167 | 20dcee94 | pbrook | break;
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168 | 20dcee94 | pbrook | } |
169 | 20dcee94 | pbrook | } |
170 | 20dcee94 | pbrook | |
171 | 20dcee94 | pbrook | static CPUReadMemoryFunc *m5208_sys_readfn[] = {
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172 | 20dcee94 | pbrook | m5208_sys_read, |
173 | 20dcee94 | pbrook | m5208_sys_read, |
174 | 20dcee94 | pbrook | m5208_sys_read |
175 | 20dcee94 | pbrook | }; |
176 | 20dcee94 | pbrook | |
177 | 20dcee94 | pbrook | static CPUWriteMemoryFunc *m5208_sys_writefn[] = {
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178 | 20dcee94 | pbrook | m5208_sys_write, |
179 | 20dcee94 | pbrook | m5208_sys_write, |
180 | 20dcee94 | pbrook | m5208_sys_write |
181 | 20dcee94 | pbrook | }; |
182 | 20dcee94 | pbrook | |
183 | 20dcee94 | pbrook | static void mcf5208_sys_init(qemu_irq *pic) |
184 | 20dcee94 | pbrook | { |
185 | 20dcee94 | pbrook | int iomemtype;
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186 | 20dcee94 | pbrook | m5208_sys_state *s; |
187 | 20dcee94 | pbrook | QEMUBH *bh; |
188 | 20dcee94 | pbrook | int i;
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189 | 20dcee94 | pbrook | |
190 | 20dcee94 | pbrook | s = (m5208_sys_state *)qemu_mallocz(sizeof(m5208_sys_state));
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191 | 20dcee94 | pbrook | iomemtype = cpu_register_io_memory(0, m5208_sys_readfn,
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192 | 20dcee94 | pbrook | m5208_sys_writefn, s); |
193 | 20dcee94 | pbrook | /* SDRAMC. */
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194 | 20dcee94 | pbrook | cpu_register_physical_memory(0xfc0a8000, 0x00004000, iomemtype); |
195 | 20dcee94 | pbrook | /* Timers. */
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196 | 20dcee94 | pbrook | for (i = 0; i < 2; i++) { |
197 | 20dcee94 | pbrook | bh = qemu_bh_new(m5208_timer_trigger, &s->timer[i]); |
198 | 20dcee94 | pbrook | s->timer[i].timer = ptimer_init(bh); |
199 | 20dcee94 | pbrook | cpu_register_physical_memory(0xfc080000 + 0x4000 * i, 0x00004000, |
200 | 20dcee94 | pbrook | iomemtype); |
201 | 20dcee94 | pbrook | s->timer[i].irq = pic[4 + i];
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202 | 20dcee94 | pbrook | } |
203 | 20dcee94 | pbrook | } |
204 | 20dcee94 | pbrook | |
205 | 00f82b8a | aurel32 | static void mcf5208evb_init(ram_addr_t ram_size, int vga_ram_size, |
206 | 6ac0e82d | balrog | const char *boot_device, DisplayState *ds, |
207 | 20dcee94 | pbrook | const char *kernel_filename, const char *kernel_cmdline, |
208 | 20dcee94 | pbrook | const char *initrd_filename, const char *cpu_model) |
209 | 20dcee94 | pbrook | { |
210 | 20dcee94 | pbrook | CPUState *env; |
211 | 20dcee94 | pbrook | int kernel_size;
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212 | 20dcee94 | pbrook | uint64_t elf_entry; |
213 | 20dcee94 | pbrook | target_ulong entry; |
214 | 20dcee94 | pbrook | qemu_irq *pic; |
215 | 20dcee94 | pbrook | |
216 | 20dcee94 | pbrook | if (!cpu_model)
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217 | 20dcee94 | pbrook | cpu_model = "m5208";
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218 | aaed909a | bellard | env = cpu_init(cpu_model); |
219 | aaed909a | bellard | if (!env) {
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220 | aaed909a | bellard | fprintf(stderr, "Unable to find m68k CPU definition\n");
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221 | aaed909a | bellard | exit(1);
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222 | 20dcee94 | pbrook | } |
223 | 20dcee94 | pbrook | |
224 | 20dcee94 | pbrook | /* Initialize CPU registers. */
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225 | 20dcee94 | pbrook | env->vbr = 0;
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226 | 20dcee94 | pbrook | /* TODO: Configure BARs. */
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227 | 20dcee94 | pbrook | |
228 | 20dcee94 | pbrook | /* DRAM at 0x20000000 */
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229 | 20dcee94 | pbrook | cpu_register_physical_memory(0x40000000, ram_size,
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230 | 20dcee94 | pbrook | qemu_ram_alloc(ram_size) | IO_MEM_RAM); |
231 | 20dcee94 | pbrook | |
232 | 20dcee94 | pbrook | /* Internal SRAM. */
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233 | 20dcee94 | pbrook | cpu_register_physical_memory(0x80000000, 16384, |
234 | 20dcee94 | pbrook | qemu_ram_alloc(16384) | IO_MEM_RAM);
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235 | 20dcee94 | pbrook | |
236 | 20dcee94 | pbrook | /* Internal peripherals. */
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237 | 20dcee94 | pbrook | pic = mcf_intc_init(0xfc048000, env);
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238 | 20dcee94 | pbrook | |
239 | 20dcee94 | pbrook | mcf_uart_mm_init(0xfc060000, pic[26], serial_hds[0]); |
240 | 20dcee94 | pbrook | mcf_uart_mm_init(0xfc064000, pic[27], serial_hds[1]); |
241 | 20dcee94 | pbrook | mcf_uart_mm_init(0xfc068000, pic[28], serial_hds[2]); |
242 | 20dcee94 | pbrook | |
243 | 20dcee94 | pbrook | mcf5208_sys_init(pic); |
244 | 20dcee94 | pbrook | |
245 | 7e049b8a | pbrook | if (nb_nics > 1) { |
246 | 7e049b8a | pbrook | fprintf(stderr, "Too many NICs\n");
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247 | 7e049b8a | pbrook | exit(1);
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248 | 7e049b8a | pbrook | } |
249 | 7e049b8a | pbrook | if (nd_table[0].vlan) { |
250 | 7e049b8a | pbrook | if (nd_table[0].model == NULL |
251 | 7e049b8a | pbrook | || strcmp(nd_table[0].model, "mcf_fec") == 0) { |
252 | 7e049b8a | pbrook | mcf_fec_init(&nd_table[0], 0xfc030000, pic + 36); |
253 | 7e049b8a | pbrook | } else if (strcmp(nd_table[0].model, "?") == 0) { |
254 | 7e049b8a | pbrook | fprintf(stderr, "qemu: Supported NICs: mcf_fec\n");
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255 | 7e049b8a | pbrook | exit (1);
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256 | 7e049b8a | pbrook | } else {
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257 | 7e049b8a | pbrook | fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model); |
258 | 7e049b8a | pbrook | exit (1);
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259 | 7e049b8a | pbrook | } |
260 | 7e049b8a | pbrook | } |
261 | 7e049b8a | pbrook | |
262 | 20dcee94 | pbrook | /* 0xfc000000 SCM. */
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263 | 20dcee94 | pbrook | /* 0xfc004000 XBS. */
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264 | 20dcee94 | pbrook | /* 0xfc008000 FlexBus CS. */
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265 | 7e049b8a | pbrook | /* 0xfc030000 FEC. */
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266 | 20dcee94 | pbrook | /* 0xfc040000 SCM + Power management. */
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267 | 20dcee94 | pbrook | /* 0xfc044000 eDMA. */
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268 | 20dcee94 | pbrook | /* 0xfc048000 INTC. */
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269 | 20dcee94 | pbrook | /* 0xfc058000 I2C. */
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270 | 20dcee94 | pbrook | /* 0xfc05c000 QSPI. */
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271 | 20dcee94 | pbrook | /* 0xfc060000 UART0. */
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272 | 20dcee94 | pbrook | /* 0xfc064000 UART0. */
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273 | 20dcee94 | pbrook | /* 0xfc068000 UART0. */
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274 | 20dcee94 | pbrook | /* 0xfc070000 DMA timers. */
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275 | 20dcee94 | pbrook | /* 0xfc080000 PIT0. */
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276 | 20dcee94 | pbrook | /* 0xfc084000 PIT1. */
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277 | 20dcee94 | pbrook | /* 0xfc088000 EPORT. */
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278 | 20dcee94 | pbrook | /* 0xfc08c000 Watchdog. */
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279 | 20dcee94 | pbrook | /* 0xfc090000 clock module. */
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280 | 20dcee94 | pbrook | /* 0xfc0a0000 CCM + reset. */
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281 | 20dcee94 | pbrook | /* 0xfc0a4000 GPIO. */
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282 | 20dcee94 | pbrook | /* 0xfc0a8000 SDRAM controller. */
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283 | 20dcee94 | pbrook | |
284 | 20dcee94 | pbrook | /* Load kernel. */
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285 | 20dcee94 | pbrook | if (!kernel_filename) {
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286 | 20dcee94 | pbrook | fprintf(stderr, "Kernel image must be specified\n");
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287 | 20dcee94 | pbrook | exit(1);
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288 | 20dcee94 | pbrook | } |
289 | 20dcee94 | pbrook | |
290 | 20dcee94 | pbrook | kernel_size = load_elf(kernel_filename, 0, &elf_entry, NULL, NULL); |
291 | 20dcee94 | pbrook | entry = elf_entry; |
292 | 20dcee94 | pbrook | if (kernel_size < 0) { |
293 | 20dcee94 | pbrook | kernel_size = load_uboot(kernel_filename, &entry, NULL);
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294 | 20dcee94 | pbrook | } |
295 | 20dcee94 | pbrook | if (kernel_size < 0) { |
296 | 20dcee94 | pbrook | kernel_size = load_image(kernel_filename, phys_ram_base); |
297 | 20dcee94 | pbrook | entry = 0x20000000;
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298 | 20dcee94 | pbrook | } |
299 | 20dcee94 | pbrook | if (kernel_size < 0) { |
300 | 20dcee94 | pbrook | fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename);
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301 | 20dcee94 | pbrook | exit(1);
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302 | 20dcee94 | pbrook | } |
303 | 20dcee94 | pbrook | |
304 | 20dcee94 | pbrook | env->pc = entry; |
305 | 20dcee94 | pbrook | } |
306 | 20dcee94 | pbrook | |
307 | 20dcee94 | pbrook | QEMUMachine mcf5208evb_machine = { |
308 | 4b32e168 | aliguori | .name = "mcf5208evb",
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309 | 4b32e168 | aliguori | .desc = "MCF5206EVB",
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310 | 4b32e168 | aliguori | .init = mcf5208evb_init, |
311 | 4b32e168 | aliguori | .ram_require = 16384,
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312 | 20dcee94 | pbrook | }; |