root / hw / tc6393xb.c @ 7ba1e619
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/*
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* Toshiba TC6393XB I/O Controller.
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* Found in Sharp Zaurus SL-6000 (tosa) or some
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* Toshiba e-Series PDAs.
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*
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* Most features are currently unsupported!!!
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*
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* This code is licensed under the GNU GPL v2.
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*/
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#include "hw.h" |
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#include "pxa.h" |
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#include "devices.h" |
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#include "flash.h" |
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#include "console.h" |
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#include "pixel_ops.h" |
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|
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#define IRQ_TC6393_NAND 0 |
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#define IRQ_TC6393_MMC 1 |
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#define IRQ_TC6393_OHCI 2 |
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#define IRQ_TC6393_SERIAL 3 |
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#define IRQ_TC6393_FB 4 |
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|
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#define TC6393XB_NR_IRQS 8 |
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|
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#define TC6393XB_GPIOS 16 |
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|
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#define SCR_REVID 0x08 /* b Revision ID */ |
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#define SCR_ISR 0x50 /* b Interrupt Status */ |
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#define SCR_IMR 0x52 /* b Interrupt Mask */ |
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#define SCR_IRR 0x54 /* b Interrupt Routing */ |
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#define SCR_GPER 0x60 /* w GP Enable */ |
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#define SCR_GPI_SR(i) (0x64 + (i)) /* b3 GPI Status */ |
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#define SCR_GPI_IMR(i) (0x68 + (i)) /* b3 GPI INT Mask */ |
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#define SCR_GPI_EDER(i) (0x6c + (i)) /* b3 GPI Edge Detect Enable */ |
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#define SCR_GPI_LIR(i) (0x70 + (i)) /* b3 GPI Level Invert */ |
| 36 |
#define SCR_GPO_DSR(i) (0x78 + (i)) /* b3 GPO Data Set */ |
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#define SCR_GPO_DOECR(i) (0x7c + (i)) /* b3 GPO Data OE Control */ |
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#define SCR_GP_IARCR(i) (0x80 + (i)) /* b3 GP Internal Active Register Control */ |
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#define SCR_GP_IARLCR(i) (0x84 + (i)) /* b3 GP INTERNAL Active Register Level Control */ |
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#define SCR_GPI_BCR(i) (0x88 + (i)) /* b3 GPI Buffer Control */ |
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#define SCR_GPA_IARCR 0x8c /* w GPa Internal Active Register Control */ |
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#define SCR_GPA_IARLCR 0x90 /* w GPa Internal Active Register Level Control */ |
| 43 |
#define SCR_GPA_BCR 0x94 /* w GPa Buffer Control */ |
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#define SCR_CCR 0x98 /* w Clock Control */ |
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#define SCR_PLL2CR 0x9a /* w PLL2 Control */ |
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#define SCR_PLL1CR 0x9c /* l PLL1 Control */ |
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#define SCR_DIARCR 0xa0 /* b Device Internal Active Register Control */ |
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#define SCR_DBOCR 0xa1 /* b Device Buffer Off Control */ |
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#define SCR_FER 0xe0 /* b Function Enable */ |
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#define SCR_MCR 0xe4 /* w Mode Control */ |
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#define SCR_CONFIG 0xfc /* b Configuration Control */ |
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#define SCR_DEBUG 0xff /* b Debug */ |
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|
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#define NAND_CFG_COMMAND 0x04 /* w Command */ |
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#define NAND_CFG_BASE 0x10 /* l Control Base Address */ |
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#define NAND_CFG_INTP 0x3d /* b Interrupt Pin */ |
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#define NAND_CFG_INTE 0x48 /* b Int Enable */ |
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#define NAND_CFG_EC 0x4a /* b Event Control */ |
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#define NAND_CFG_ICC 0x4c /* b Internal Clock Control */ |
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#define NAND_CFG_ECCC 0x5b /* b ECC Control */ |
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#define NAND_CFG_NFTC 0x60 /* b NAND Flash Transaction Control */ |
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#define NAND_CFG_NFM 0x61 /* b NAND Flash Monitor */ |
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#define NAND_CFG_NFPSC 0x62 /* b NAND Flash Power Supply Control */ |
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#define NAND_CFG_NFDC 0x63 /* b NAND Flash Detect Control */ |
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|
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#define NAND_DATA 0x00 /* l Data */ |
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#define NAND_MODE 0x04 /* b Mode */ |
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#define NAND_STATUS 0x05 /* b Status */ |
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#define NAND_ISR 0x06 /* b Interrupt Status */ |
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#define NAND_IMR 0x07 /* b Interrupt Mask */ |
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|
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#define NAND_MODE_WP 0x80 |
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#define NAND_MODE_CE 0x10 |
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#define NAND_MODE_ALE 0x02 |
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#define NAND_MODE_CLE 0x01 |
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#define NAND_MODE_ECC_MASK 0x60 |
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#define NAND_MODE_ECC_EN 0x20 |
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#define NAND_MODE_ECC_READ 0x40 |
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#define NAND_MODE_ECC_RST 0x60 |
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|
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struct tc6393xb_s {
|
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target_phys_addr_t target_base; |
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qemu_irq irq; |
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qemu_irq *sub_irqs; |
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struct {
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uint8_t ISR; |
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uint8_t IMR; |
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uint8_t IRR; |
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uint16_t GPER; |
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uint8_t GPI_SR[3];
|
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uint8_t GPI_IMR[3];
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uint8_t GPI_EDER[3];
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uint8_t GPI_LIR[3];
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uint8_t GP_IARCR[3];
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uint8_t GP_IARLCR[3];
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uint8_t GPI_BCR[3];
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uint16_t GPA_IARCR; |
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uint16_t GPA_IARLCR; |
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uint16_t CCR; |
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uint16_t PLL2CR; |
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uint32_t PLL1CR; |
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uint8_t DIARCR; |
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uint8_t DBOCR; |
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uint8_t FER; |
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uint16_t MCR; |
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uint8_t CONFIG; |
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uint8_t DEBUG; |
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} scr; |
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uint32_t gpio_dir; |
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uint32_t gpio_level; |
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uint32_t prev_level; |
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qemu_irq handler[TC6393XB_GPIOS]; |
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qemu_irq *gpio_in; |
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|
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struct {
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uint8_t mode; |
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uint8_t isr; |
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uint8_t imr; |
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} nand; |
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int nand_enable;
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uint32_t nand_phys; |
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struct nand_flash_s *flash;
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struct ecc_state_s ecc;
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|
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DisplayState *ds; |
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QEMUConsole *console; |
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ram_addr_t vram_addr; |
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uint32_t scr_width, scr_height; /* in pixels */
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qemu_irq l3v; |
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unsigned blank : 1, |
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blanked : 1;
|
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}; |
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|
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qemu_irq *tc6393xb_gpio_in_get(struct tc6393xb_s *s)
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{
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return s->gpio_in;
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} |
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|
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static void tc6393xb_gpio_set(void *opaque, int line, int level) |
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{
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// struct tc6393xb_s *s = opaque;
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|
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if (line > TC6393XB_GPIOS) {
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printf("%s: No GPIO pin %i\n", __FUNCTION__, line);
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return;
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} |
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|
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// FIXME: how does the chip reflect the GPIO input level change?
|
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} |
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|
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void tc6393xb_gpio_out_set(struct tc6393xb_s *s, int line, |
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qemu_irq handler) |
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{
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if (line >= TC6393XB_GPIOS) {
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fprintf(stderr, "TC6393xb: no GPIO pin %d\n", line);
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return;
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} |
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|
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s->handler[line] = handler; |
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} |
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|
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static void tc6393xb_gpio_handler_update(struct tc6393xb_s *s) |
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{
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uint32_t level, diff; |
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int bit;
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|
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level = s->gpio_level & s->gpio_dir; |
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|
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for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) { |
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bit = ffs(diff) - 1;
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qemu_set_irq(s->handler[bit], (level >> bit) & 1);
|
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} |
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|
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s->prev_level = level; |
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} |
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|
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qemu_irq tc6393xb_l3v_get(struct tc6393xb_s *s)
|
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{
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return s->l3v;
|
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} |
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|
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static void tc6393xb_l3v(void *opaque, int line, int level) |
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{
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struct tc6393xb_s *s = opaque;
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s->blank = !level; |
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fprintf(stderr, "L3V: %d\n", level);
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} |
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|
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static void tc6393xb_sub_irq(void *opaque, int line, int level) { |
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struct tc6393xb_s *s = opaque;
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uint8_t isr = s->scr.ISR; |
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if (level)
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isr |= 1 << line;
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else
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isr &= ~(1 << line);
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s->scr.ISR = isr; |
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qemu_set_irq(s->irq, isr & s->scr.IMR); |
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} |
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#define SCR_REG_B(N) \
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case SCR_ ##N: return s->scr.N |
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#define SCR_REG_W(N) \
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case SCR_ ##N: return s->scr.N; \ |
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case SCR_ ##N + 1: return s->scr.N >> 8; |
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#define SCR_REG_L(N) \
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case SCR_ ##N: return s->scr.N; \ |
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case SCR_ ##N + 1: return s->scr.N >> 8; \ |
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case SCR_ ##N + 2: return s->scr.N >> 16; \ |
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case SCR_ ##N + 3: return s->scr.N >> 24; |
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#define SCR_REG_A(N) \
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case SCR_ ##N(0): return s->scr.N[0]; \ |
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case SCR_ ##N(1): return s->scr.N[1]; \ |
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case SCR_ ##N(2): return s->scr.N[2] |
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|
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static uint32_t tc6393xb_scr_readb(struct tc6393xb_s *s, target_phys_addr_t addr) |
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{
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switch (addr) {
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case SCR_REVID:
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return 3; |
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case SCR_REVID+1: |
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return 0; |
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SCR_REG_B(ISR); |
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SCR_REG_B(IMR); |
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SCR_REG_B(IRR); |
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SCR_REG_W(GPER); |
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SCR_REG_A(GPI_SR); |
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SCR_REG_A(GPI_IMR); |
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SCR_REG_A(GPI_EDER); |
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SCR_REG_A(GPI_LIR); |
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case SCR_GPO_DSR(0): |
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case SCR_GPO_DSR(1): |
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case SCR_GPO_DSR(2): |
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return (s->gpio_level >> ((addr - SCR_GPO_DSR(0)) * 8)) & 0xff; |
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case SCR_GPO_DOECR(0): |
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case SCR_GPO_DOECR(1): |
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case SCR_GPO_DOECR(2): |
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return (s->gpio_dir >> ((addr - SCR_GPO_DOECR(0)) * 8)) & 0xff; |
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SCR_REG_A(GP_IARCR); |
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SCR_REG_A(GP_IARLCR); |
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SCR_REG_A(GPI_BCR); |
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SCR_REG_W(GPA_IARCR); |
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SCR_REG_W(GPA_IARLCR); |
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SCR_REG_W(CCR); |
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SCR_REG_W(PLL2CR); |
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SCR_REG_L(PLL1CR); |
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SCR_REG_B(DIARCR); |
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SCR_REG_B(DBOCR); |
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SCR_REG_B(FER); |
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SCR_REG_W(MCR); |
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SCR_REG_B(CONFIG); |
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SCR_REG_B(DEBUG); |
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} |
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fprintf(stderr, "tc6393xb_scr: unhandled read at %08x\n", (uint32_t) addr);
|
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return 0; |
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} |
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#undef SCR_REG_B
|
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#undef SCR_REG_W
|
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#undef SCR_REG_L
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#undef SCR_REG_A
|
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|
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#define SCR_REG_B(N) \
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case SCR_ ##N: s->scr.N = value; return; |
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#define SCR_REG_W(N) \
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case SCR_ ##N: s->scr.N = (s->scr.N & ~0xff) | (value & 0xff); return; \ |
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case SCR_ ##N + 1: s->scr.N = (s->scr.N & 0xff) | (value << 8); return |
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#define SCR_REG_L(N) \
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case SCR_ ##N: s->scr.N = (s->scr.N & ~0xff) | (value & 0xff); return; \ |
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case SCR_ ##N + 1: s->scr.N = (s->scr.N & ~(0xff << 8)) | (value & (0xff << 8)); return; \ |
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case SCR_ ##N + 2: s->scr.N = (s->scr.N & ~(0xff << 16)) | (value & (0xff << 16)); return; \ |
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case SCR_ ##N + 3: s->scr.N = (s->scr.N & ~(0xff << 24)) | (value & (0xff << 24)); return; |
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#define SCR_REG_A(N) \
|
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case SCR_ ##N(0): s->scr.N[0] = value; return; \ |
| 273 |
case SCR_ ##N(1): s->scr.N[1] = value; return; \ |
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case SCR_ ##N(2): s->scr.N[2] = value; return |
| 275 |
|
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static void tc6393xb_scr_writeb(struct tc6393xb_s *s, target_phys_addr_t addr, uint32_t value) |
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{
|
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switch (addr) {
|
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SCR_REG_B(ISR); |
| 280 |
SCR_REG_B(IMR); |
| 281 |
SCR_REG_B(IRR); |
| 282 |
SCR_REG_W(GPER); |
| 283 |
SCR_REG_A(GPI_SR); |
| 284 |
SCR_REG_A(GPI_IMR); |
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SCR_REG_A(GPI_EDER); |
| 286 |
SCR_REG_A(GPI_LIR); |
| 287 |
case SCR_GPO_DSR(0): |
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case SCR_GPO_DSR(1): |
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case SCR_GPO_DSR(2): |
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s->gpio_level = (s->gpio_level & ~(0xff << ((addr - SCR_GPO_DSR(0))*8))) | ((value & 0xff) << ((addr - SCR_GPO_DSR(0))*8)); |
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tc6393xb_gpio_handler_update(s); |
| 292 |
return;
|
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case SCR_GPO_DOECR(0): |
| 294 |
case SCR_GPO_DOECR(1): |
| 295 |
case SCR_GPO_DOECR(2): |
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s->gpio_dir = (s->gpio_dir & ~(0xff << ((addr - SCR_GPO_DOECR(0))*8))) | ((value & 0xff) << ((addr - SCR_GPO_DOECR(0))*8)); |
| 297 |
tc6393xb_gpio_handler_update(s); |
| 298 |
return;
|
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SCR_REG_A(GP_IARCR); |
| 300 |
SCR_REG_A(GP_IARLCR); |
| 301 |
SCR_REG_A(GPI_BCR); |
| 302 |
SCR_REG_W(GPA_IARCR); |
| 303 |
SCR_REG_W(GPA_IARLCR); |
| 304 |
SCR_REG_W(CCR); |
| 305 |
SCR_REG_W(PLL2CR); |
| 306 |
SCR_REG_L(PLL1CR); |
| 307 |
SCR_REG_B(DIARCR); |
| 308 |
SCR_REG_B(DBOCR); |
| 309 |
SCR_REG_B(FER); |
| 310 |
SCR_REG_W(MCR); |
| 311 |
SCR_REG_B(CONFIG); |
| 312 |
SCR_REG_B(DEBUG); |
| 313 |
} |
| 314 |
fprintf(stderr, "tc6393xb_scr: unhandled write at %08x: %02x\n",
|
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(uint32_t) addr, value & 0xff);
|
| 316 |
} |
| 317 |
#undef SCR_REG_B
|
| 318 |
#undef SCR_REG_W
|
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#undef SCR_REG_L
|
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#undef SCR_REG_A
|
| 321 |
|
| 322 |
static void tc6393xb_nand_irq(struct tc6393xb_s *s) { |
| 323 |
qemu_set_irq(s->sub_irqs[IRQ_TC6393_NAND], |
| 324 |
(s->nand.imr & 0x80) && (s->nand.imr & s->nand.isr));
|
| 325 |
} |
| 326 |
|
| 327 |
static uint32_t tc6393xb_nand_cfg_readb(struct tc6393xb_s *s, target_phys_addr_t addr) { |
| 328 |
switch (addr) {
|
| 329 |
case NAND_CFG_COMMAND:
|
| 330 |
return s->nand_enable ? 2 : 0; |
| 331 |
case NAND_CFG_BASE:
|
| 332 |
case NAND_CFG_BASE + 1: |
| 333 |
case NAND_CFG_BASE + 2: |
| 334 |
case NAND_CFG_BASE + 3: |
| 335 |
return s->nand_phys >> (addr - NAND_CFG_BASE);
|
| 336 |
} |
| 337 |
fprintf(stderr, "tc6393xb_nand_cfg: unhandled read at %08x\n", (uint32_t) addr);
|
| 338 |
return 0; |
| 339 |
} |
| 340 |
static void tc6393xb_nand_cfg_writeb(struct tc6393xb_s *s, target_phys_addr_t addr, uint32_t value) { |
| 341 |
switch (addr) {
|
| 342 |
case NAND_CFG_COMMAND:
|
| 343 |
s->nand_enable = (value & 0x2);
|
| 344 |
return;
|
| 345 |
case NAND_CFG_BASE:
|
| 346 |
case NAND_CFG_BASE + 1: |
| 347 |
case NAND_CFG_BASE + 2: |
| 348 |
case NAND_CFG_BASE + 3: |
| 349 |
s->nand_phys &= ~(0xff << ((addr - NAND_CFG_BASE) * 8)); |
| 350 |
s->nand_phys |= (value & 0xff) << ((addr - NAND_CFG_BASE) * 8); |
| 351 |
return;
|
| 352 |
} |
| 353 |
fprintf(stderr, "tc6393xb_nand_cfg: unhandled write at %08x: %02x\n",
|
| 354 |
(uint32_t) addr, value & 0xff);
|
| 355 |
} |
| 356 |
|
| 357 |
static uint32_t tc6393xb_nand_readb(struct tc6393xb_s *s, target_phys_addr_t addr) { |
| 358 |
switch (addr) {
|
| 359 |
case NAND_DATA + 0: |
| 360 |
case NAND_DATA + 1: |
| 361 |
case NAND_DATA + 2: |
| 362 |
case NAND_DATA + 3: |
| 363 |
return nand_getio(s->flash);
|
| 364 |
case NAND_MODE:
|
| 365 |
return s->nand.mode;
|
| 366 |
case NAND_STATUS:
|
| 367 |
return 0x14; |
| 368 |
case NAND_ISR:
|
| 369 |
return s->nand.isr;
|
| 370 |
case NAND_IMR:
|
| 371 |
return s->nand.imr;
|
| 372 |
} |
| 373 |
fprintf(stderr, "tc6393xb_nand: unhandled read at %08x\n", (uint32_t) addr);
|
| 374 |
return 0; |
| 375 |
} |
| 376 |
static void tc6393xb_nand_writeb(struct tc6393xb_s *s, target_phys_addr_t addr, uint32_t value) { |
| 377 |
// fprintf(stderr, "tc6393xb_nand: write at %08x: %02x\n",
|
| 378 |
// (uint32_t) addr, value & 0xff);
|
| 379 |
switch (addr) {
|
| 380 |
case NAND_DATA + 0: |
| 381 |
case NAND_DATA + 1: |
| 382 |
case NAND_DATA + 2: |
| 383 |
case NAND_DATA + 3: |
| 384 |
nand_setio(s->flash, value); |
| 385 |
s->nand.isr &= 1;
|
| 386 |
tc6393xb_nand_irq(s); |
| 387 |
return;
|
| 388 |
case NAND_MODE:
|
| 389 |
s->nand.mode = value; |
| 390 |
nand_setpins(s->flash, |
| 391 |
value & NAND_MODE_CLE, |
| 392 |
value & NAND_MODE_ALE, |
| 393 |
!(value & NAND_MODE_CE), |
| 394 |
value & NAND_MODE_WP, |
| 395 |
0); // FIXME: gnd |
| 396 |
switch (value & NAND_MODE_ECC_MASK) {
|
| 397 |
case NAND_MODE_ECC_RST:
|
| 398 |
ecc_reset(&s->ecc); |
| 399 |
break;
|
| 400 |
case NAND_MODE_ECC_READ:
|
| 401 |
// FIXME
|
| 402 |
break;
|
| 403 |
case NAND_MODE_ECC_EN:
|
| 404 |
ecc_reset(&s->ecc); |
| 405 |
} |
| 406 |
return;
|
| 407 |
case NAND_ISR:
|
| 408 |
s->nand.isr = value; |
| 409 |
tc6393xb_nand_irq(s); |
| 410 |
return;
|
| 411 |
case NAND_IMR:
|
| 412 |
s->nand.imr = value; |
| 413 |
tc6393xb_nand_irq(s); |
| 414 |
return;
|
| 415 |
} |
| 416 |
fprintf(stderr, "tc6393xb_nand: unhandled write at %08x: %02x\n",
|
| 417 |
(uint32_t) addr, value & 0xff);
|
| 418 |
} |
| 419 |
|
| 420 |
#define BITS 8 |
| 421 |
#include "tc6393xb_template.h" |
| 422 |
#define BITS 15 |
| 423 |
#include "tc6393xb_template.h" |
| 424 |
#define BITS 16 |
| 425 |
#include "tc6393xb_template.h" |
| 426 |
#define BITS 24 |
| 427 |
#include "tc6393xb_template.h" |
| 428 |
#define BITS 32 |
| 429 |
#include "tc6393xb_template.h" |
| 430 |
|
| 431 |
static void tc6393xb_draw_graphic(struct tc6393xb_s *s, int full_update) |
| 432 |
{
|
| 433 |
switch (s->ds->depth) {
|
| 434 |
case 8: |
| 435 |
tc6393xb_draw_graphic8(s); |
| 436 |
break;
|
| 437 |
case 15: |
| 438 |
tc6393xb_draw_graphic15(s); |
| 439 |
break;
|
| 440 |
case 16: |
| 441 |
tc6393xb_draw_graphic16(s); |
| 442 |
break;
|
| 443 |
case 24: |
| 444 |
tc6393xb_draw_graphic24(s); |
| 445 |
break;
|
| 446 |
case 32: |
| 447 |
tc6393xb_draw_graphic32(s); |
| 448 |
break;
|
| 449 |
default:
|
| 450 |
printf("tc6393xb: unknown depth %d\n", s->ds->depth);
|
| 451 |
return;
|
| 452 |
} |
| 453 |
|
| 454 |
dpy_update(s->ds, 0, 0, s->scr_width, s->scr_height); |
| 455 |
} |
| 456 |
|
| 457 |
static void tc6393xb_draw_blank(struct tc6393xb_s *s, int full_update) |
| 458 |
{
|
| 459 |
int i, w;
|
| 460 |
uint8_t *d; |
| 461 |
|
| 462 |
if (!full_update)
|
| 463 |
return;
|
| 464 |
|
| 465 |
w = s->scr_width * ((s->ds->depth + 7) >> 3); |
| 466 |
d = s->ds->data; |
| 467 |
for(i = 0; i < s->scr_height; i++) { |
| 468 |
memset(d, 0, w);
|
| 469 |
d += s->ds->linesize; |
| 470 |
} |
| 471 |
|
| 472 |
dpy_update(s->ds, 0, 0, s->scr_width, s->scr_height); |
| 473 |
} |
| 474 |
|
| 475 |
static void tc6393xb_update_display(void *opaque) |
| 476 |
{
|
| 477 |
struct tc6393xb_s *s = opaque;
|
| 478 |
int full_update;
|
| 479 |
|
| 480 |
if (s->scr_width == 0 || s->scr_height == 0) |
| 481 |
return;
|
| 482 |
|
| 483 |
full_update = 0;
|
| 484 |
if (s->blanked != s->blank) {
|
| 485 |
s->blanked = s->blank; |
| 486 |
full_update = 1;
|
| 487 |
} |
| 488 |
if (s->scr_width != s->ds->width || s->scr_height != s->ds->height) {
|
| 489 |
qemu_console_resize(s->console, s->scr_width, s->scr_height); |
| 490 |
full_update = 1;
|
| 491 |
} |
| 492 |
if (s->blanked)
|
| 493 |
tc6393xb_draw_blank(s, full_update); |
| 494 |
else
|
| 495 |
tc6393xb_draw_graphic(s, full_update); |
| 496 |
} |
| 497 |
|
| 498 |
|
| 499 |
static uint32_t tc6393xb_readb(void *opaque, target_phys_addr_t addr) { |
| 500 |
struct tc6393xb_s *s = opaque;
|
| 501 |
addr -= s->target_base; |
| 502 |
|
| 503 |
switch (addr >> 8) { |
| 504 |
case 0: |
| 505 |
return tc6393xb_scr_readb(s, addr & 0xff); |
| 506 |
case 1: |
| 507 |
return tc6393xb_nand_cfg_readb(s, addr & 0xff); |
| 508 |
}; |
| 509 |
|
| 510 |
if ((addr &~0xff) == s->nand_phys && s->nand_enable) { |
| 511 |
// return tc6393xb_nand_readb(s, addr & 0xff);
|
| 512 |
uint8_t d = tc6393xb_nand_readb(s, addr & 0xff);
|
| 513 |
// fprintf(stderr, "tc6393xb_nand: read at %08x: %02hhx\n", (uint32_t) addr, d);
|
| 514 |
return d;
|
| 515 |
} |
| 516 |
|
| 517 |
// fprintf(stderr, "tc6393xb: unhandled read at %08x\n", (uint32_t) addr);
|
| 518 |
return 0; |
| 519 |
} |
| 520 |
|
| 521 |
static void tc6393xb_writeb(void *opaque, target_phys_addr_t addr, uint32_t value) { |
| 522 |
struct tc6393xb_s *s = opaque;
|
| 523 |
addr -= s->target_base; |
| 524 |
|
| 525 |
switch (addr >> 8) { |
| 526 |
case 0: |
| 527 |
tc6393xb_scr_writeb(s, addr & 0xff, value);
|
| 528 |
return;
|
| 529 |
case 1: |
| 530 |
tc6393xb_nand_cfg_writeb(s, addr & 0xff, value);
|
| 531 |
return;
|
| 532 |
}; |
| 533 |
|
| 534 |
if ((addr &~0xff) == s->nand_phys && s->nand_enable) |
| 535 |
tc6393xb_nand_writeb(s, addr & 0xff, value);
|
| 536 |
else
|
| 537 |
fprintf(stderr, "tc6393xb: unhandled write at %08x: %02x\n",
|
| 538 |
(uint32_t) addr, value & 0xff);
|
| 539 |
} |
| 540 |
|
| 541 |
static uint32_t tc6393xb_readw(void *opaque, target_phys_addr_t addr) |
| 542 |
{
|
| 543 |
return (tc6393xb_readb(opaque, addr) & 0xff) | |
| 544 |
(tc6393xb_readb(opaque, addr + 1) << 8); |
| 545 |
} |
| 546 |
|
| 547 |
static uint32_t tc6393xb_readl(void *opaque, target_phys_addr_t addr) |
| 548 |
{
|
| 549 |
return (tc6393xb_readb(opaque, addr) & 0xff) | |
| 550 |
((tc6393xb_readb(opaque, addr + 1) & 0xff) << 8) | |
| 551 |
((tc6393xb_readb(opaque, addr + 2) & 0xff) << 16) | |
| 552 |
((tc6393xb_readb(opaque, addr + 3) & 0xff) << 24); |
| 553 |
} |
| 554 |
|
| 555 |
static void tc6393xb_writew(void *opaque, target_phys_addr_t addr, uint32_t value) |
| 556 |
{
|
| 557 |
tc6393xb_writeb(opaque, addr, value); |
| 558 |
tc6393xb_writeb(opaque, addr + 1, value >> 8); |
| 559 |
} |
| 560 |
|
| 561 |
static void tc6393xb_writel(void *opaque, target_phys_addr_t addr, uint32_t value) |
| 562 |
{
|
| 563 |
tc6393xb_writeb(opaque, addr, value); |
| 564 |
tc6393xb_writeb(opaque, addr + 1, value >> 8); |
| 565 |
tc6393xb_writeb(opaque, addr + 2, value >> 16); |
| 566 |
tc6393xb_writeb(opaque, addr + 3, value >> 24); |
| 567 |
} |
| 568 |
|
| 569 |
struct tc6393xb_s *tc6393xb_init(uint32_t base, qemu_irq irq, DisplayState *ds)
|
| 570 |
{
|
| 571 |
int iomemtype;
|
| 572 |
struct tc6393xb_s *s;
|
| 573 |
CPUReadMemoryFunc *tc6393xb_readfn[] = {
|
| 574 |
tc6393xb_readb, |
| 575 |
tc6393xb_readw, |
| 576 |
tc6393xb_readl, |
| 577 |
}; |
| 578 |
CPUWriteMemoryFunc *tc6393xb_writefn[] = {
|
| 579 |
tc6393xb_writeb, |
| 580 |
tc6393xb_writew, |
| 581 |
tc6393xb_writel, |
| 582 |
}; |
| 583 |
|
| 584 |
s = (struct tc6393xb_s *) qemu_mallocz(sizeof(struct tc6393xb_s)); |
| 585 |
s->target_base = base; |
| 586 |
s->irq = irq; |
| 587 |
s->gpio_in = qemu_allocate_irqs(tc6393xb_gpio_set, s, TC6393XB_GPIOS); |
| 588 |
|
| 589 |
s->l3v = *qemu_allocate_irqs(tc6393xb_l3v, s, 1);
|
| 590 |
s->blanked = 1;
|
| 591 |
|
| 592 |
s->sub_irqs = qemu_allocate_irqs(tc6393xb_sub_irq, s, TC6393XB_NR_IRQS); |
| 593 |
|
| 594 |
s->flash = nand_init(NAND_MFR_TOSHIBA, 0x76);
|
| 595 |
|
| 596 |
iomemtype = cpu_register_io_memory(0, tc6393xb_readfn,
|
| 597 |
tc6393xb_writefn, s); |
| 598 |
cpu_register_physical_memory(s->target_base, 0x10000, iomemtype);
|
| 599 |
|
| 600 |
if (ds) {
|
| 601 |
s->ds = ds; |
| 602 |
s->vram_addr = qemu_ram_alloc(0x100000);
|
| 603 |
cpu_register_physical_memory(s->target_base + 0x100000, 0x100000, s->vram_addr); |
| 604 |
s->scr_width = 480;
|
| 605 |
s->scr_height = 640;
|
| 606 |
s->console = graphic_console_init(ds, |
| 607 |
tc6393xb_update_display, |
| 608 |
NULL, /* invalidate */ |
| 609 |
NULL, /* screen_dump */ |
| 610 |
NULL, /* text_update */ |
| 611 |
s); |
| 612 |
} |
| 613 |
|
| 614 |
return s;
|
| 615 |
} |