root / hw / pxa2xx_timer.c @ 7bc3018b
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1 | a171fe39 | balrog | /*
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2 | a171fe39 | balrog | * Intel XScale PXA255/270 OS Timers.
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3 | a171fe39 | balrog | *
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4 | a171fe39 | balrog | * Copyright (c) 2006 Openedhand Ltd.
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5 | a171fe39 | balrog | * Copyright (c) 2006 Thorsten Zitterell
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6 | a171fe39 | balrog | *
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7 | 8e31bf38 | Matthew Fernandez | * This code is licensed under the GPL.
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8 | a171fe39 | balrog | */
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9 | a171fe39 | balrog | |
10 | 87ecb68b | pbrook | #include "hw.h" |
11 | 87ecb68b | pbrook | #include "qemu-timer.h" |
12 | 87ecb68b | pbrook | #include "sysemu.h" |
13 | 87ecb68b | pbrook | #include "pxa.h" |
14 | 797e9542 | Dmitry Eremin-Solenikov | #include "sysbus.h" |
15 | a171fe39 | balrog | |
16 | a171fe39 | balrog | #define OSMR0 0x00 |
17 | a171fe39 | balrog | #define OSMR1 0x04 |
18 | a171fe39 | balrog | #define OSMR2 0x08 |
19 | a171fe39 | balrog | #define OSMR3 0x0c |
20 | a171fe39 | balrog | #define OSMR4 0x80 |
21 | a171fe39 | balrog | #define OSMR5 0x84 |
22 | a171fe39 | balrog | #define OSMR6 0x88 |
23 | a171fe39 | balrog | #define OSMR7 0x8c |
24 | a171fe39 | balrog | #define OSMR8 0x90 |
25 | a171fe39 | balrog | #define OSMR9 0x94 |
26 | a171fe39 | balrog | #define OSMR10 0x98 |
27 | a171fe39 | balrog | #define OSMR11 0x9c |
28 | a171fe39 | balrog | #define OSCR 0x10 /* OS Timer Count */ |
29 | a171fe39 | balrog | #define OSCR4 0x40 |
30 | a171fe39 | balrog | #define OSCR5 0x44 |
31 | a171fe39 | balrog | #define OSCR6 0x48 |
32 | a171fe39 | balrog | #define OSCR7 0x4c |
33 | a171fe39 | balrog | #define OSCR8 0x50 |
34 | a171fe39 | balrog | #define OSCR9 0x54 |
35 | a171fe39 | balrog | #define OSCR10 0x58 |
36 | a171fe39 | balrog | #define OSCR11 0x5c |
37 | a171fe39 | balrog | #define OSSR 0x14 /* Timer status register */ |
38 | a171fe39 | balrog | #define OWER 0x18 |
39 | a171fe39 | balrog | #define OIER 0x1c /* Interrupt enable register 3-0 to E3-E0 */ |
40 | a171fe39 | balrog | #define OMCR4 0xc0 /* OS Match Control registers */ |
41 | a171fe39 | balrog | #define OMCR5 0xc4 |
42 | a171fe39 | balrog | #define OMCR6 0xc8 |
43 | a171fe39 | balrog | #define OMCR7 0xcc |
44 | a171fe39 | balrog | #define OMCR8 0xd0 |
45 | a171fe39 | balrog | #define OMCR9 0xd4 |
46 | a171fe39 | balrog | #define OMCR10 0xd8 |
47 | a171fe39 | balrog | #define OMCR11 0xdc |
48 | a171fe39 | balrog | #define OSNR 0x20 |
49 | a171fe39 | balrog | |
50 | a171fe39 | balrog | #define PXA25X_FREQ 3686400 /* 3.6864 MHz */ |
51 | a171fe39 | balrog | #define PXA27X_FREQ 3250000 /* 3.25 MHz */ |
52 | a171fe39 | balrog | |
53 | a171fe39 | balrog | static int pxa2xx_timer4_freq[8] = { |
54 | a171fe39 | balrog | [0] = 0, |
55 | a171fe39 | balrog | [1] = 32768, |
56 | a171fe39 | balrog | [2] = 1000, |
57 | a171fe39 | balrog | [3] = 1, |
58 | a171fe39 | balrog | [4] = 1000000, |
59 | a171fe39 | balrog | /* [5] is the "Externally supplied clock". Assign if necessary. */
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60 | a171fe39 | balrog | [5 ... 7] = 0, |
61 | a171fe39 | balrog | }; |
62 | a171fe39 | balrog | |
63 | 797e9542 | Dmitry Eremin-Solenikov | typedef struct PXA2xxTimerInfo PXA2xxTimerInfo; |
64 | 797e9542 | Dmitry Eremin-Solenikov | |
65 | bc24a225 | Paul Brook | typedef struct { |
66 | a171fe39 | balrog | uint32_t value; |
67 | 5251d196 | Andrzej Zaborowski | qemu_irq irq; |
68 | a171fe39 | balrog | QEMUTimer *qtimer; |
69 | a171fe39 | balrog | int num;
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70 | 797e9542 | Dmitry Eremin-Solenikov | PXA2xxTimerInfo *info; |
71 | bc24a225 | Paul Brook | } PXA2xxTimer0; |
72 | a171fe39 | balrog | |
73 | bc24a225 | Paul Brook | typedef struct { |
74 | bc24a225 | Paul Brook | PXA2xxTimer0 tm; |
75 | a171fe39 | balrog | int32_t oldclock; |
76 | a171fe39 | balrog | int32_t clock; |
77 | a171fe39 | balrog | uint64_t lastload; |
78 | a171fe39 | balrog | uint32_t freq; |
79 | a171fe39 | balrog | uint32_t control; |
80 | bc24a225 | Paul Brook | } PXA2xxTimer4; |
81 | a171fe39 | balrog | |
82 | 797e9542 | Dmitry Eremin-Solenikov | struct PXA2xxTimerInfo {
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83 | 797e9542 | Dmitry Eremin-Solenikov | SysBusDevice busdev; |
84 | b755bde3 | Benoît Canet | MemoryRegion iomem; |
85 | 797e9542 | Dmitry Eremin-Solenikov | uint32_t flags; |
86 | 797e9542 | Dmitry Eremin-Solenikov | |
87 | a171fe39 | balrog | int32_t clock; |
88 | a171fe39 | balrog | int32_t oldclock; |
89 | a171fe39 | balrog | uint64_t lastload; |
90 | a171fe39 | balrog | uint32_t freq; |
91 | bc24a225 | Paul Brook | PXA2xxTimer0 timer[4];
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92 | a171fe39 | balrog | uint32_t events; |
93 | a171fe39 | balrog | uint32_t irq_enabled; |
94 | a171fe39 | balrog | uint32_t reset3; |
95 | a171fe39 | balrog | uint32_t snapshot; |
96 | 797e9542 | Dmitry Eremin-Solenikov | |
97 | 4ff927cc | Dmitry Eremin-Solenikov | qemu_irq irq4; |
98 | 797e9542 | Dmitry Eremin-Solenikov | PXA2xxTimer4 tm4[8];
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99 | 797e9542 | Dmitry Eremin-Solenikov | }; |
100 | 797e9542 | Dmitry Eremin-Solenikov | |
101 | 797e9542 | Dmitry Eremin-Solenikov | #define PXA2XX_TIMER_HAVE_TM4 0 |
102 | 797e9542 | Dmitry Eremin-Solenikov | |
103 | 797e9542 | Dmitry Eremin-Solenikov | static inline int pxa2xx_timer_has_tm4(PXA2xxTimerInfo *s) |
104 | 797e9542 | Dmitry Eremin-Solenikov | { |
105 | 797e9542 | Dmitry Eremin-Solenikov | return s->flags & (1 << PXA2XX_TIMER_HAVE_TM4); |
106 | 797e9542 | Dmitry Eremin-Solenikov | } |
107 | a171fe39 | balrog | |
108 | a171fe39 | balrog | static void pxa2xx_timer_update(void *opaque, uint64_t now_qemu) |
109 | a171fe39 | balrog | { |
110 | d353eb43 | Dmitry Eremin-Solenikov | PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque; |
111 | a171fe39 | balrog | int i;
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112 | a171fe39 | balrog | uint32_t now_vm; |
113 | a171fe39 | balrog | uint64_t new_qemu; |
114 | a171fe39 | balrog | |
115 | a171fe39 | balrog | now_vm = s->clock + |
116 | 6ee093c9 | Juan Quintela | muldiv64(now_qemu - s->lastload, s->freq, get_ticks_per_sec()); |
117 | a171fe39 | balrog | |
118 | a171fe39 | balrog | for (i = 0; i < 4; i ++) { |
119 | a171fe39 | balrog | new_qemu = now_qemu + muldiv64((uint32_t) (s->timer[i].value - now_vm), |
120 | 6ee093c9 | Juan Quintela | get_ticks_per_sec(), s->freq); |
121 | a171fe39 | balrog | qemu_mod_timer(s->timer[i].qtimer, new_qemu); |
122 | a171fe39 | balrog | } |
123 | a171fe39 | balrog | } |
124 | a171fe39 | balrog | |
125 | a171fe39 | balrog | static void pxa2xx_timer_update4(void *opaque, uint64_t now_qemu, int n) |
126 | a171fe39 | balrog | { |
127 | d353eb43 | Dmitry Eremin-Solenikov | PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque; |
128 | a171fe39 | balrog | uint32_t now_vm; |
129 | a171fe39 | balrog | uint64_t new_qemu; |
130 | a171fe39 | balrog | static const int counters[8] = { 0, 0, 0, 0, 4, 4, 6, 6 }; |
131 | a171fe39 | balrog | int counter;
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132 | a171fe39 | balrog | |
133 | a171fe39 | balrog | if (s->tm4[n].control & (1 << 7)) |
134 | a171fe39 | balrog | counter = n; |
135 | a171fe39 | balrog | else
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136 | a171fe39 | balrog | counter = counters[n]; |
137 | a171fe39 | balrog | |
138 | a171fe39 | balrog | if (!s->tm4[counter].freq) {
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139 | 3f582262 | balrog | qemu_del_timer(s->tm4[n].tm.qtimer); |
140 | a171fe39 | balrog | return;
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141 | a171fe39 | balrog | } |
142 | a171fe39 | balrog | |
143 | a171fe39 | balrog | now_vm = s->tm4[counter].clock + muldiv64(now_qemu - |
144 | a171fe39 | balrog | s->tm4[counter].lastload, |
145 | 6ee093c9 | Juan Quintela | s->tm4[counter].freq, get_ticks_per_sec()); |
146 | a171fe39 | balrog | |
147 | 3bdd58a4 | balrog | new_qemu = now_qemu + muldiv64((uint32_t) (s->tm4[n].tm.value - now_vm), |
148 | 6ee093c9 | Juan Quintela | get_ticks_per_sec(), s->tm4[counter].freq); |
149 | 3f582262 | balrog | qemu_mod_timer(s->tm4[n].tm.qtimer, new_qemu); |
150 | a171fe39 | balrog | } |
151 | a171fe39 | balrog | |
152 | b755bde3 | Benoît Canet | static uint64_t pxa2xx_timer_read(void *opaque, target_phys_addr_t offset, |
153 | b755bde3 | Benoît Canet | unsigned size)
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154 | a171fe39 | balrog | { |
155 | d353eb43 | Dmitry Eremin-Solenikov | PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque; |
156 | a171fe39 | balrog | int tm = 0; |
157 | a171fe39 | balrog | |
158 | a171fe39 | balrog | switch (offset) {
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159 | a171fe39 | balrog | case OSMR3: tm ++;
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160 | a171fe39 | balrog | case OSMR2: tm ++;
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161 | a171fe39 | balrog | case OSMR1: tm ++;
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162 | a171fe39 | balrog | case OSMR0:
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163 | a171fe39 | balrog | return s->timer[tm].value;
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164 | a171fe39 | balrog | case OSMR11: tm ++;
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165 | a171fe39 | balrog | case OSMR10: tm ++;
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166 | a171fe39 | balrog | case OSMR9: tm ++;
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167 | a171fe39 | balrog | case OSMR8: tm ++;
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168 | a171fe39 | balrog | case OSMR7: tm ++;
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169 | a171fe39 | balrog | case OSMR6: tm ++;
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170 | a171fe39 | balrog | case OSMR5: tm ++;
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171 | a171fe39 | balrog | case OSMR4:
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172 | 797e9542 | Dmitry Eremin-Solenikov | if (!pxa2xx_timer_has_tm4(s))
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173 | a171fe39 | balrog | goto badreg;
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174 | 3bdd58a4 | balrog | return s->tm4[tm].tm.value;
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175 | a171fe39 | balrog | case OSCR:
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176 | 74475455 | Paolo Bonzini | return s->clock + muldiv64(qemu_get_clock_ns(vm_clock) -
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177 | 6ee093c9 | Juan Quintela | s->lastload, s->freq, get_ticks_per_sec()); |
178 | a171fe39 | balrog | case OSCR11: tm ++;
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179 | a171fe39 | balrog | case OSCR10: tm ++;
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180 | a171fe39 | balrog | case OSCR9: tm ++;
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181 | a171fe39 | balrog | case OSCR8: tm ++;
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182 | a171fe39 | balrog | case OSCR7: tm ++;
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183 | a171fe39 | balrog | case OSCR6: tm ++;
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184 | a171fe39 | balrog | case OSCR5: tm ++;
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185 | a171fe39 | balrog | case OSCR4:
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186 | 797e9542 | Dmitry Eremin-Solenikov | if (!pxa2xx_timer_has_tm4(s))
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187 | a171fe39 | balrog | goto badreg;
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188 | a171fe39 | balrog | |
189 | a171fe39 | balrog | if ((tm == 9 - 4 || tm == 11 - 4) && (s->tm4[tm].control & (1 << 9))) { |
190 | a171fe39 | balrog | if (s->tm4[tm - 1].freq) |
191 | a171fe39 | balrog | s->snapshot = s->tm4[tm - 1].clock + muldiv64(
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192 | 74475455 | Paolo Bonzini | qemu_get_clock_ns(vm_clock) - |
193 | a171fe39 | balrog | s->tm4[tm - 1].lastload,
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194 | 6ee093c9 | Juan Quintela | s->tm4[tm - 1].freq, get_ticks_per_sec());
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195 | a171fe39 | balrog | else
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196 | a171fe39 | balrog | s->snapshot = s->tm4[tm - 1].clock;
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197 | a171fe39 | balrog | } |
198 | a171fe39 | balrog | |
199 | a171fe39 | balrog | if (!s->tm4[tm].freq)
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200 | a171fe39 | balrog | return s->tm4[tm].clock;
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201 | 74475455 | Paolo Bonzini | return s->tm4[tm].clock + muldiv64(qemu_get_clock_ns(vm_clock) -
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202 | 6ee093c9 | Juan Quintela | s->tm4[tm].lastload, s->tm4[tm].freq, get_ticks_per_sec()); |
203 | a171fe39 | balrog | case OIER:
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204 | a171fe39 | balrog | return s->irq_enabled;
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205 | a171fe39 | balrog | case OSSR: /* Status register */ |
206 | a171fe39 | balrog | return s->events;
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207 | a171fe39 | balrog | case OWER:
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208 | a171fe39 | balrog | return s->reset3;
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209 | a171fe39 | balrog | case OMCR11: tm ++;
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210 | a171fe39 | balrog | case OMCR10: tm ++;
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211 | a171fe39 | balrog | case OMCR9: tm ++;
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212 | a171fe39 | balrog | case OMCR8: tm ++;
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213 | a171fe39 | balrog | case OMCR7: tm ++;
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214 | a171fe39 | balrog | case OMCR6: tm ++;
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215 | a171fe39 | balrog | case OMCR5: tm ++;
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216 | a171fe39 | balrog | case OMCR4:
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217 | 797e9542 | Dmitry Eremin-Solenikov | if (!pxa2xx_timer_has_tm4(s))
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218 | a171fe39 | balrog | goto badreg;
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219 | a171fe39 | balrog | return s->tm4[tm].control;
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220 | a171fe39 | balrog | case OSNR:
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221 | a171fe39 | balrog | return s->snapshot;
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222 | a171fe39 | balrog | default:
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223 | a171fe39 | balrog | badreg:
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224 | 2ac71179 | Paul Brook | hw_error("pxa2xx_timer_read: Bad offset " REG_FMT "\n", offset); |
225 | a171fe39 | balrog | } |
226 | a171fe39 | balrog | |
227 | a171fe39 | balrog | return 0; |
228 | a171fe39 | balrog | } |
229 | a171fe39 | balrog | |
230 | c227f099 | Anthony Liguori | static void pxa2xx_timer_write(void *opaque, target_phys_addr_t offset, |
231 | b755bde3 | Benoît Canet | uint64_t value, unsigned size)
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232 | a171fe39 | balrog | { |
233 | a171fe39 | balrog | int i, tm = 0; |
234 | d353eb43 | Dmitry Eremin-Solenikov | PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque; |
235 | a171fe39 | balrog | |
236 | a171fe39 | balrog | switch (offset) {
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237 | a171fe39 | balrog | case OSMR3: tm ++;
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238 | a171fe39 | balrog | case OSMR2: tm ++;
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239 | a171fe39 | balrog | case OSMR1: tm ++;
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240 | a171fe39 | balrog | case OSMR0:
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241 | a171fe39 | balrog | s->timer[tm].value = value; |
242 | 74475455 | Paolo Bonzini | pxa2xx_timer_update(s, qemu_get_clock_ns(vm_clock)); |
243 | a171fe39 | balrog | break;
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244 | a171fe39 | balrog | case OSMR11: tm ++;
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245 | a171fe39 | balrog | case OSMR10: tm ++;
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246 | a171fe39 | balrog | case OSMR9: tm ++;
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247 | a171fe39 | balrog | case OSMR8: tm ++;
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248 | a171fe39 | balrog | case OSMR7: tm ++;
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249 | a171fe39 | balrog | case OSMR6: tm ++;
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250 | a171fe39 | balrog | case OSMR5: tm ++;
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251 | a171fe39 | balrog | case OSMR4:
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252 | 797e9542 | Dmitry Eremin-Solenikov | if (!pxa2xx_timer_has_tm4(s))
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253 | a171fe39 | balrog | goto badreg;
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254 | 3bdd58a4 | balrog | s->tm4[tm].tm.value = value; |
255 | 74475455 | Paolo Bonzini | pxa2xx_timer_update4(s, qemu_get_clock_ns(vm_clock), tm); |
256 | a171fe39 | balrog | break;
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257 | a171fe39 | balrog | case OSCR:
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258 | a171fe39 | balrog | s->oldclock = s->clock; |
259 | 74475455 | Paolo Bonzini | s->lastload = qemu_get_clock_ns(vm_clock); |
260 | a171fe39 | balrog | s->clock = value; |
261 | a171fe39 | balrog | pxa2xx_timer_update(s, s->lastload); |
262 | a171fe39 | balrog | break;
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263 | a171fe39 | balrog | case OSCR11: tm ++;
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264 | a171fe39 | balrog | case OSCR10: tm ++;
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265 | a171fe39 | balrog | case OSCR9: tm ++;
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266 | a171fe39 | balrog | case OSCR8: tm ++;
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267 | a171fe39 | balrog | case OSCR7: tm ++;
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268 | a171fe39 | balrog | case OSCR6: tm ++;
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269 | a171fe39 | balrog | case OSCR5: tm ++;
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270 | a171fe39 | balrog | case OSCR4:
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271 | 797e9542 | Dmitry Eremin-Solenikov | if (!pxa2xx_timer_has_tm4(s))
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272 | a171fe39 | balrog | goto badreg;
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273 | a171fe39 | balrog | s->tm4[tm].oldclock = s->tm4[tm].clock; |
274 | 74475455 | Paolo Bonzini | s->tm4[tm].lastload = qemu_get_clock_ns(vm_clock); |
275 | a171fe39 | balrog | s->tm4[tm].clock = value; |
276 | a171fe39 | balrog | pxa2xx_timer_update4(s, s->tm4[tm].lastload, tm); |
277 | a171fe39 | balrog | break;
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278 | a171fe39 | balrog | case OIER:
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279 | a171fe39 | balrog | s->irq_enabled = value & 0xfff;
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280 | a171fe39 | balrog | break;
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281 | a171fe39 | balrog | case OSSR: /* Status register */ |
282 | 8034ce7d | Andrzej Zaborowski | value &= s->events; |
283 | a171fe39 | balrog | s->events &= ~value; |
284 | 8034ce7d | Andrzej Zaborowski | for (i = 0; i < 4; i ++, value >>= 1) |
285 | 8034ce7d | Andrzej Zaborowski | if (value & 1) |
286 | 5251d196 | Andrzej Zaborowski | qemu_irq_lower(s->timer[i].irq); |
287 | 8034ce7d | Andrzej Zaborowski | if (pxa2xx_timer_has_tm4(s) && !(s->events & 0xff0) && value) |
288 | 8034ce7d | Andrzej Zaborowski | qemu_irq_lower(s->irq4); |
289 | a171fe39 | balrog | break;
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290 | a171fe39 | balrog | case OWER: /* XXX: Reset on OSMR3 match? */ |
291 | a171fe39 | balrog | s->reset3 = value; |
292 | a171fe39 | balrog | break;
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293 | a171fe39 | balrog | case OMCR7: tm ++;
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294 | a171fe39 | balrog | case OMCR6: tm ++;
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295 | a171fe39 | balrog | case OMCR5: tm ++;
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296 | a171fe39 | balrog | case OMCR4:
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297 | 797e9542 | Dmitry Eremin-Solenikov | if (!pxa2xx_timer_has_tm4(s))
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298 | a171fe39 | balrog | goto badreg;
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299 | a171fe39 | balrog | s->tm4[tm].control = value & 0x0ff;
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300 | a171fe39 | balrog | /* XXX Stop if running (shouldn't happen) */
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301 | a171fe39 | balrog | if ((value & (1 << 7)) || tm == 0) |
302 | a171fe39 | balrog | s->tm4[tm].freq = pxa2xx_timer4_freq[value & 7];
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303 | a171fe39 | balrog | else {
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304 | a171fe39 | balrog | s->tm4[tm].freq = 0;
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305 | 74475455 | Paolo Bonzini | pxa2xx_timer_update4(s, qemu_get_clock_ns(vm_clock), tm); |
306 | a171fe39 | balrog | } |
307 | a171fe39 | balrog | break;
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308 | a171fe39 | balrog | case OMCR11: tm ++;
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309 | a171fe39 | balrog | case OMCR10: tm ++;
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310 | a171fe39 | balrog | case OMCR9: tm ++;
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311 | a171fe39 | balrog | case OMCR8: tm += 4; |
312 | 797e9542 | Dmitry Eremin-Solenikov | if (!pxa2xx_timer_has_tm4(s))
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313 | a171fe39 | balrog | goto badreg;
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314 | a171fe39 | balrog | s->tm4[tm].control = value & 0x3ff;
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315 | a171fe39 | balrog | /* XXX Stop if running (shouldn't happen) */
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316 | a171fe39 | balrog | if ((value & (1 << 7)) || !(tm & 1)) |
317 | a171fe39 | balrog | s->tm4[tm].freq = |
318 | a171fe39 | balrog | pxa2xx_timer4_freq[(value & (1 << 8)) ? 0 : (value & 7)]; |
319 | a171fe39 | balrog | else {
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320 | a171fe39 | balrog | s->tm4[tm].freq = 0;
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321 | 74475455 | Paolo Bonzini | pxa2xx_timer_update4(s, qemu_get_clock_ns(vm_clock), tm); |
322 | a171fe39 | balrog | } |
323 | a171fe39 | balrog | break;
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324 | a171fe39 | balrog | default:
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325 | a171fe39 | balrog | badreg:
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326 | 2ac71179 | Paul Brook | hw_error("pxa2xx_timer_write: Bad offset " REG_FMT "\n", offset); |
327 | a171fe39 | balrog | } |
328 | a171fe39 | balrog | } |
329 | a171fe39 | balrog | |
330 | b755bde3 | Benoît Canet | static const MemoryRegionOps pxa2xx_timer_ops = { |
331 | b755bde3 | Benoît Canet | .read = pxa2xx_timer_read, |
332 | b755bde3 | Benoît Canet | .write = pxa2xx_timer_write, |
333 | b755bde3 | Benoît Canet | .endianness = DEVICE_NATIVE_ENDIAN, |
334 | a171fe39 | balrog | }; |
335 | a171fe39 | balrog | |
336 | a171fe39 | balrog | static void pxa2xx_timer_tick(void *opaque) |
337 | a171fe39 | balrog | { |
338 | bc24a225 | Paul Brook | PXA2xxTimer0 *t = (PXA2xxTimer0 *) opaque; |
339 | 797e9542 | Dmitry Eremin-Solenikov | PXA2xxTimerInfo *i = t->info; |
340 | a171fe39 | balrog | |
341 | a171fe39 | balrog | if (i->irq_enabled & (1 << t->num)) { |
342 | a171fe39 | balrog | i->events |= 1 << t->num;
|
343 | 5251d196 | Andrzej Zaborowski | qemu_irq_raise(t->irq); |
344 | a171fe39 | balrog | } |
345 | a171fe39 | balrog | |
346 | a171fe39 | balrog | if (t->num == 3) |
347 | a171fe39 | balrog | if (i->reset3 & 1) { |
348 | a171fe39 | balrog | i->reset3 = 0;
|
349 | 3f582262 | balrog | qemu_system_reset_request(); |
350 | a171fe39 | balrog | } |
351 | a171fe39 | balrog | } |
352 | a171fe39 | balrog | |
353 | a171fe39 | balrog | static void pxa2xx_timer_tick4(void *opaque) |
354 | a171fe39 | balrog | { |
355 | bc24a225 | Paul Brook | PXA2xxTimer4 *t = (PXA2xxTimer4 *) opaque; |
356 | d353eb43 | Dmitry Eremin-Solenikov | PXA2xxTimerInfo *i = (PXA2xxTimerInfo *) t->tm.info; |
357 | a171fe39 | balrog | |
358 | 3bdd58a4 | balrog | pxa2xx_timer_tick(&t->tm); |
359 | a171fe39 | balrog | if (t->control & (1 << 3)) |
360 | a171fe39 | balrog | t->clock = 0;
|
361 | a171fe39 | balrog | if (t->control & (1 << 6)) |
362 | 74475455 | Paolo Bonzini | pxa2xx_timer_update4(i, qemu_get_clock_ns(vm_clock), t->tm.num - 4);
|
363 | 4ff927cc | Dmitry Eremin-Solenikov | if (i->events & 0xff0) |
364 | 4ff927cc | Dmitry Eremin-Solenikov | qemu_irq_raise(i->irq4); |
365 | a171fe39 | balrog | } |
366 | a171fe39 | balrog | |
367 | 797e9542 | Dmitry Eremin-Solenikov | static int pxa25x_timer_post_load(void *opaque, int version_id) |
368 | aa941b94 | balrog | { |
369 | d353eb43 | Dmitry Eremin-Solenikov | PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque; |
370 | aa941b94 | balrog | int64_t now; |
371 | aa941b94 | balrog | int i;
|
372 | aa941b94 | balrog | |
373 | 74475455 | Paolo Bonzini | now = qemu_get_clock_ns(vm_clock); |
374 | aa941b94 | balrog | pxa2xx_timer_update(s, now); |
375 | aa941b94 | balrog | |
376 | 797e9542 | Dmitry Eremin-Solenikov | if (pxa2xx_timer_has_tm4(s))
|
377 | 797e9542 | Dmitry Eremin-Solenikov | for (i = 0; i < 8; i ++) |
378 | aa941b94 | balrog | pxa2xx_timer_update4(s, now, i); |
379 | aa941b94 | balrog | |
380 | aa941b94 | balrog | return 0; |
381 | aa941b94 | balrog | } |
382 | aa941b94 | balrog | |
383 | 797e9542 | Dmitry Eremin-Solenikov | static int pxa2xx_timer_init(SysBusDevice *dev) |
384 | a171fe39 | balrog | { |
385 | a171fe39 | balrog | int i;
|
386 | d353eb43 | Dmitry Eremin-Solenikov | PXA2xxTimerInfo *s; |
387 | a171fe39 | balrog | |
388 | 797e9542 | Dmitry Eremin-Solenikov | s = FROM_SYSBUS(PXA2xxTimerInfo, dev); |
389 | a171fe39 | balrog | s->irq_enabled = 0;
|
390 | a171fe39 | balrog | s->oldclock = 0;
|
391 | a171fe39 | balrog | s->clock = 0;
|
392 | 74475455 | Paolo Bonzini | s->lastload = qemu_get_clock_ns(vm_clock); |
393 | a171fe39 | balrog | s->reset3 = 0;
|
394 | a171fe39 | balrog | |
395 | a171fe39 | balrog | for (i = 0; i < 4; i ++) { |
396 | a171fe39 | balrog | s->timer[i].value = 0;
|
397 | 5251d196 | Andrzej Zaborowski | sysbus_init_irq(dev, &s->timer[i].irq); |
398 | a171fe39 | balrog | s->timer[i].info = s; |
399 | a171fe39 | balrog | s->timer[i].num = i; |
400 | 74475455 | Paolo Bonzini | s->timer[i].qtimer = qemu_new_timer_ns(vm_clock, |
401 | a171fe39 | balrog | pxa2xx_timer_tick, &s->timer[i]); |
402 | a171fe39 | balrog | } |
403 | 797e9542 | Dmitry Eremin-Solenikov | if (s->flags & (1 << PXA2XX_TIMER_HAVE_TM4)) { |
404 | 4ff927cc | Dmitry Eremin-Solenikov | sysbus_init_irq(dev, &s->irq4); |
405 | 797e9542 | Dmitry Eremin-Solenikov | |
406 | 797e9542 | Dmitry Eremin-Solenikov | for (i = 0; i < 8; i ++) { |
407 | 797e9542 | Dmitry Eremin-Solenikov | s->tm4[i].tm.value = 0;
|
408 | 797e9542 | Dmitry Eremin-Solenikov | s->tm4[i].tm.info = s; |
409 | 797e9542 | Dmitry Eremin-Solenikov | s->tm4[i].tm.num = i + 4;
|
410 | 797e9542 | Dmitry Eremin-Solenikov | s->tm4[i].freq = 0;
|
411 | 797e9542 | Dmitry Eremin-Solenikov | s->tm4[i].control = 0x0;
|
412 | 74475455 | Paolo Bonzini | s->tm4[i].tm.qtimer = qemu_new_timer_ns(vm_clock, |
413 | 797e9542 | Dmitry Eremin-Solenikov | pxa2xx_timer_tick4, &s->tm4[i]); |
414 | 797e9542 | Dmitry Eremin-Solenikov | } |
415 | 797e9542 | Dmitry Eremin-Solenikov | } |
416 | a171fe39 | balrog | |
417 | b755bde3 | Benoît Canet | memory_region_init_io(&s->iomem, &pxa2xx_timer_ops, s, |
418 | b755bde3 | Benoît Canet | "pxa2xx-timer", 0x00001000); |
419 | 750ecd44 | Avi Kivity | sysbus_init_mmio(dev, &s->iomem); |
420 | aa941b94 | balrog | |
421 | 797e9542 | Dmitry Eremin-Solenikov | return 0; |
422 | a171fe39 | balrog | } |
423 | a171fe39 | balrog | |
424 | 797e9542 | Dmitry Eremin-Solenikov | static const VMStateDescription vmstate_pxa2xx_timer0_regs = { |
425 | 797e9542 | Dmitry Eremin-Solenikov | .name = "pxa2xx_timer0",
|
426 | 8034ce7d | Andrzej Zaborowski | .version_id = 2,
|
427 | 8034ce7d | Andrzej Zaborowski | .minimum_version_id = 2,
|
428 | 8034ce7d | Andrzej Zaborowski | .minimum_version_id_old = 2,
|
429 | 797e9542 | Dmitry Eremin-Solenikov | .fields = (VMStateField[]) { |
430 | 797e9542 | Dmitry Eremin-Solenikov | VMSTATE_UINT32(value, PXA2xxTimer0), |
431 | 797e9542 | Dmitry Eremin-Solenikov | VMSTATE_END_OF_LIST(), |
432 | 797e9542 | Dmitry Eremin-Solenikov | }, |
433 | 797e9542 | Dmitry Eremin-Solenikov | }; |
434 | 797e9542 | Dmitry Eremin-Solenikov | |
435 | 797e9542 | Dmitry Eremin-Solenikov | static const VMStateDescription vmstate_pxa2xx_timer4_regs = { |
436 | 797e9542 | Dmitry Eremin-Solenikov | .name = "pxa2xx_timer4",
|
437 | 797e9542 | Dmitry Eremin-Solenikov | .version_id = 1,
|
438 | 797e9542 | Dmitry Eremin-Solenikov | .minimum_version_id = 1,
|
439 | 797e9542 | Dmitry Eremin-Solenikov | .minimum_version_id_old = 1,
|
440 | 797e9542 | Dmitry Eremin-Solenikov | .fields = (VMStateField[]) { |
441 | 797e9542 | Dmitry Eremin-Solenikov | VMSTATE_STRUCT(tm, PXA2xxTimer4, 1,
|
442 | 797e9542 | Dmitry Eremin-Solenikov | vmstate_pxa2xx_timer0_regs, PXA2xxTimer0), |
443 | 797e9542 | Dmitry Eremin-Solenikov | VMSTATE_INT32(oldclock, PXA2xxTimer4), |
444 | 797e9542 | Dmitry Eremin-Solenikov | VMSTATE_INT32(clock, PXA2xxTimer4), |
445 | 797e9542 | Dmitry Eremin-Solenikov | VMSTATE_UINT64(lastload, PXA2xxTimer4), |
446 | 797e9542 | Dmitry Eremin-Solenikov | VMSTATE_UINT32(freq, PXA2xxTimer4), |
447 | 797e9542 | Dmitry Eremin-Solenikov | VMSTATE_UINT32(control, PXA2xxTimer4), |
448 | 797e9542 | Dmitry Eremin-Solenikov | VMSTATE_END_OF_LIST(), |
449 | 797e9542 | Dmitry Eremin-Solenikov | }, |
450 | 797e9542 | Dmitry Eremin-Solenikov | }; |
451 | 797e9542 | Dmitry Eremin-Solenikov | |
452 | 797e9542 | Dmitry Eremin-Solenikov | static bool pxa2xx_timer_has_tm4_test(void *opaque, int version_id) |
453 | a171fe39 | balrog | { |
454 | 797e9542 | Dmitry Eremin-Solenikov | return pxa2xx_timer_has_tm4(opaque);
|
455 | a171fe39 | balrog | } |
456 | a171fe39 | balrog | |
457 | 797e9542 | Dmitry Eremin-Solenikov | static const VMStateDescription vmstate_pxa2xx_timer_regs = { |
458 | 797e9542 | Dmitry Eremin-Solenikov | .name = "pxa2xx_timer",
|
459 | 797e9542 | Dmitry Eremin-Solenikov | .version_id = 1,
|
460 | 797e9542 | Dmitry Eremin-Solenikov | .minimum_version_id = 1,
|
461 | 797e9542 | Dmitry Eremin-Solenikov | .minimum_version_id_old = 1,
|
462 | 797e9542 | Dmitry Eremin-Solenikov | .post_load = pxa25x_timer_post_load, |
463 | 797e9542 | Dmitry Eremin-Solenikov | .fields = (VMStateField[]) { |
464 | 797e9542 | Dmitry Eremin-Solenikov | VMSTATE_INT32(clock, PXA2xxTimerInfo), |
465 | 797e9542 | Dmitry Eremin-Solenikov | VMSTATE_INT32(oldclock, PXA2xxTimerInfo), |
466 | 797e9542 | Dmitry Eremin-Solenikov | VMSTATE_UINT64(lastload, PXA2xxTimerInfo), |
467 | 797e9542 | Dmitry Eremin-Solenikov | VMSTATE_STRUCT_ARRAY(timer, PXA2xxTimerInfo, 4, 1, |
468 | 797e9542 | Dmitry Eremin-Solenikov | vmstate_pxa2xx_timer0_regs, PXA2xxTimer0), |
469 | 797e9542 | Dmitry Eremin-Solenikov | VMSTATE_UINT32(events, PXA2xxTimerInfo), |
470 | 797e9542 | Dmitry Eremin-Solenikov | VMSTATE_UINT32(irq_enabled, PXA2xxTimerInfo), |
471 | 797e9542 | Dmitry Eremin-Solenikov | VMSTATE_UINT32(reset3, PXA2xxTimerInfo), |
472 | 797e9542 | Dmitry Eremin-Solenikov | VMSTATE_UINT32(snapshot, PXA2xxTimerInfo), |
473 | 797e9542 | Dmitry Eremin-Solenikov | VMSTATE_STRUCT_ARRAY_TEST(tm4, PXA2xxTimerInfo, 8,
|
474 | 797e9542 | Dmitry Eremin-Solenikov | pxa2xx_timer_has_tm4_test, 0,
|
475 | 797e9542 | Dmitry Eremin-Solenikov | vmstate_pxa2xx_timer4_regs, PXA2xxTimer4), |
476 | 797e9542 | Dmitry Eremin-Solenikov | VMSTATE_END_OF_LIST(), |
477 | a171fe39 | balrog | } |
478 | 797e9542 | Dmitry Eremin-Solenikov | }; |
479 | 797e9542 | Dmitry Eremin-Solenikov | |
480 | 999e12bb | Anthony Liguori | static Property pxa25x_timer_dev_properties[] = {
|
481 | 999e12bb | Anthony Liguori | DEFINE_PROP_UINT32("freq", PXA2xxTimerInfo, freq, PXA25X_FREQ),
|
482 | 999e12bb | Anthony Liguori | DEFINE_PROP_BIT("tm4", PXA2xxTimerInfo, flags,
|
483 | 999e12bb | Anthony Liguori | PXA2XX_TIMER_HAVE_TM4, false),
|
484 | 999e12bb | Anthony Liguori | DEFINE_PROP_END_OF_LIST(), |
485 | 797e9542 | Dmitry Eremin-Solenikov | }; |
486 | 797e9542 | Dmitry Eremin-Solenikov | |
487 | 999e12bb | Anthony Liguori | static void pxa25x_timer_dev_class_init(ObjectClass *klass, void *data) |
488 | 999e12bb | Anthony Liguori | { |
489 | 39bffca2 | Anthony Liguori | DeviceClass *dc = DEVICE_CLASS(klass); |
490 | 999e12bb | Anthony Liguori | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
491 | 999e12bb | Anthony Liguori | |
492 | 999e12bb | Anthony Liguori | k->init = pxa2xx_timer_init; |
493 | 39bffca2 | Anthony Liguori | dc->desc = "PXA25x timer";
|
494 | 39bffca2 | Anthony Liguori | dc->vmsd = &vmstate_pxa2xx_timer_regs; |
495 | 39bffca2 | Anthony Liguori | dc->props = pxa25x_timer_dev_properties; |
496 | 999e12bb | Anthony Liguori | } |
497 | 999e12bb | Anthony Liguori | |
498 | 39bffca2 | Anthony Liguori | static TypeInfo pxa25x_timer_dev_info = {
|
499 | 39bffca2 | Anthony Liguori | .name = "pxa25x-timer",
|
500 | 39bffca2 | Anthony Liguori | .parent = TYPE_SYS_BUS_DEVICE, |
501 | 39bffca2 | Anthony Liguori | .instance_size = sizeof(PXA2xxTimerInfo),
|
502 | 39bffca2 | Anthony Liguori | .class_init = pxa25x_timer_dev_class_init, |
503 | 999e12bb | Anthony Liguori | }; |
504 | 999e12bb | Anthony Liguori | |
505 | 999e12bb | Anthony Liguori | static Property pxa27x_timer_dev_properties[] = {
|
506 | 999e12bb | Anthony Liguori | DEFINE_PROP_UINT32("freq", PXA2xxTimerInfo, freq, PXA27X_FREQ),
|
507 | 999e12bb | Anthony Liguori | DEFINE_PROP_BIT("tm4", PXA2xxTimerInfo, flags,
|
508 | 999e12bb | Anthony Liguori | PXA2XX_TIMER_HAVE_TM4, true),
|
509 | 999e12bb | Anthony Liguori | DEFINE_PROP_END_OF_LIST(), |
510 | 999e12bb | Anthony Liguori | }; |
511 | 999e12bb | Anthony Liguori | |
512 | 999e12bb | Anthony Liguori | static void pxa27x_timer_dev_class_init(ObjectClass *klass, void *data) |
513 | 999e12bb | Anthony Liguori | { |
514 | 39bffca2 | Anthony Liguori | DeviceClass *dc = DEVICE_CLASS(klass); |
515 | 999e12bb | Anthony Liguori | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
516 | 999e12bb | Anthony Liguori | |
517 | 999e12bb | Anthony Liguori | k->init = pxa2xx_timer_init; |
518 | 39bffca2 | Anthony Liguori | dc->desc = "PXA27x timer";
|
519 | 39bffca2 | Anthony Liguori | dc->vmsd = &vmstate_pxa2xx_timer_regs; |
520 | 39bffca2 | Anthony Liguori | dc->props = pxa27x_timer_dev_properties; |
521 | 999e12bb | Anthony Liguori | } |
522 | 999e12bb | Anthony Liguori | |
523 | 39bffca2 | Anthony Liguori | static TypeInfo pxa27x_timer_dev_info = {
|
524 | 39bffca2 | Anthony Liguori | .name = "pxa27x-timer",
|
525 | 39bffca2 | Anthony Liguori | .parent = TYPE_SYS_BUS_DEVICE, |
526 | 39bffca2 | Anthony Liguori | .instance_size = sizeof(PXA2xxTimerInfo),
|
527 | 39bffca2 | Anthony Liguori | .class_init = pxa27x_timer_dev_class_init, |
528 | 797e9542 | Dmitry Eremin-Solenikov | }; |
529 | 797e9542 | Dmitry Eremin-Solenikov | |
530 | 83f7d43a | Andreas Färber | static void pxa2xx_timer_register_types(void) |
531 | 797e9542 | Dmitry Eremin-Solenikov | { |
532 | 39bffca2 | Anthony Liguori | type_register_static(&pxa25x_timer_dev_info); |
533 | 39bffca2 | Anthony Liguori | type_register_static(&pxa27x_timer_dev_info); |
534 | 83f7d43a | Andreas Färber | } |
535 | 83f7d43a | Andreas Färber | |
536 | 83f7d43a | Andreas Färber | type_init(pxa2xx_timer_register_types) |