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/*
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* ARM Generic/Distributed Interrupt Controller
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*
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* Copyright (c) 2006-2007 CodeSourcery.
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* Written by Paul Brook
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*
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* This code is licensed under the GPL.
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*/
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/* This file contains implementation code for the RealView EB interrupt
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* controller, MPCore distributed interrupt controller and ARMv7-M
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* Nested Vectored Interrupt Controller.
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* It is compiled in two ways:
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* (1) as a standalone file to produce a sysbus device which is a GIC
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* that can be used on the realview board and as one of the builtin
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* private peripherals for the ARM MP CPUs (11MPCore, A9, etc)
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* (2) by being directly #included into armv7m_nvic.c to produce the
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* armv7m_nvic device.
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*/
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#include "sysbus.h" |
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/* Maximum number of possible interrupts, determined by the GIC architecture */
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#define GIC_MAXIRQ 1020 |
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/* First 32 are private to each CPU (SGIs and PPIs). */
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#define GIC_INTERNAL 32 |
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/* Maximum number of possible CPU interfaces, determined by GIC architecture */
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#ifdef NVIC
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#define NCPU 1 |
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#else
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#define NCPU 8 |
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#endif
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//#define DEBUG_GIC
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#ifdef DEBUG_GIC
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#define DPRINTF(fmt, ...) \
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do { printf("arm_gic: " fmt , ## __VA_ARGS__); } while (0) |
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#else
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#define DPRINTF(fmt, ...) do {} while(0) |
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#endif
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#ifdef NVIC
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static const uint8_t gic_id[] = |
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{ 0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1 }; |
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/* The NVIC has 16 internal vectors. However these are not exposed
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through the normal GIC interface. */
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#define GIC_BASE_IRQ 32 |
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#else
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static const uint8_t gic_id[] = |
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{ 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 }; |
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#define GIC_BASE_IRQ 0 |
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#endif
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|
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#define FROM_SYSBUSGIC(type, dev) \
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DO_UPCAST(type, gic, FROM_SYSBUS(gic_state, dev)) |
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typedef struct gic_irq_state |
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{ |
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/* The enable bits are only banked for per-cpu interrupts. */
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unsigned enabled:NCPU;
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unsigned pending:NCPU;
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unsigned active:NCPU;
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unsigned level:NCPU;
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unsigned model:1; /* 0 = N:N, 1 = 1:N */ |
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unsigned trigger:1; /* nonzero = edge triggered. */ |
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} gic_irq_state; |
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#define ALL_CPU_MASK ((unsigned)(((1 << NCPU) - 1))) |
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#if NCPU > 1 |
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#define NUM_CPU(s) ((s)->num_cpu)
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#else
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#define NUM_CPU(s) 1 |
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#endif
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#define GIC_SET_ENABLED(irq, cm) s->irq_state[irq].enabled |= (cm)
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#define GIC_CLEAR_ENABLED(irq, cm) s->irq_state[irq].enabled &= ~(cm)
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#define GIC_TEST_ENABLED(irq, cm) ((s->irq_state[irq].enabled & (cm)) != 0) |
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#define GIC_SET_PENDING(irq, cm) s->irq_state[irq].pending |= (cm)
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#define GIC_CLEAR_PENDING(irq, cm) s->irq_state[irq].pending &= ~(cm)
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#define GIC_TEST_PENDING(irq, cm) ((s->irq_state[irq].pending & (cm)) != 0) |
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#define GIC_SET_ACTIVE(irq, cm) s->irq_state[irq].active |= (cm)
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#define GIC_CLEAR_ACTIVE(irq, cm) s->irq_state[irq].active &= ~(cm)
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#define GIC_TEST_ACTIVE(irq, cm) ((s->irq_state[irq].active & (cm)) != 0) |
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#define GIC_SET_MODEL(irq) s->irq_state[irq].model = 1 |
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#define GIC_CLEAR_MODEL(irq) s->irq_state[irq].model = 0 |
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#define GIC_TEST_MODEL(irq) s->irq_state[irq].model
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#define GIC_SET_LEVEL(irq, cm) s->irq_state[irq].level = (cm)
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#define GIC_CLEAR_LEVEL(irq, cm) s->irq_state[irq].level &= ~(cm)
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#define GIC_TEST_LEVEL(irq, cm) ((s->irq_state[irq].level & (cm)) != 0) |
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#define GIC_SET_TRIGGER(irq) s->irq_state[irq].trigger = 1 |
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#define GIC_CLEAR_TRIGGER(irq) s->irq_state[irq].trigger = 0 |
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#define GIC_TEST_TRIGGER(irq) s->irq_state[irq].trigger
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#define GIC_GET_PRIORITY(irq, cpu) (((irq) < GIC_INTERNAL) ? \
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s->priority1[irq][cpu] : \ |
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s->priority2[(irq) - GIC_INTERNAL]) |
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#ifdef NVIC
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#define GIC_TARGET(irq) 1 |
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#else
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#define GIC_TARGET(irq) s->irq_target[irq]
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#endif
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typedef struct gic_state |
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{ |
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SysBusDevice busdev; |
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qemu_irq parent_irq[NCPU]; |
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int enabled;
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int cpu_enabled[NCPU];
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gic_irq_state irq_state[GIC_MAXIRQ]; |
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#ifndef NVIC
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int irq_target[GIC_MAXIRQ];
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#endif
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int priority1[GIC_INTERNAL][NCPU];
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int priority2[GIC_MAXIRQ - GIC_INTERNAL];
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int last_active[GIC_MAXIRQ][NCPU];
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int priority_mask[NCPU];
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int running_irq[NCPU];
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int running_priority[NCPU];
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int current_pending[NCPU];
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#if NCPU > 1 |
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uint32_t num_cpu; |
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#endif
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MemoryRegion iomem; /* Distributor */
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#ifndef NVIC
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/* This is just so we can have an opaque pointer which identifies
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* both this GIC and which CPU interface we should be accessing.
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*/
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struct gic_state *backref[NCPU];
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MemoryRegion cpuiomem[NCPU+1]; /* CPU interfaces */ |
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#endif
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uint32_t num_irq; |
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} gic_state; |
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static inline int gic_get_current_cpu(gic_state *s) |
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{ |
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#if NCPU > 1 |
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if (s->num_cpu > 1) { |
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return cpu_single_env->cpu_index;
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} |
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#endif
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return 0; |
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} |
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/* TODO: Many places that call this routine could be optimized. */
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/* Update interrupt status after enabled or pending bits have been changed. */
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static void gic_update(gic_state *s) |
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{ |
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int best_irq;
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int best_prio;
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int irq;
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int level;
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int cpu;
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int cm;
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for (cpu = 0; cpu < NUM_CPU(s); cpu++) { |
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cm = 1 << cpu;
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s->current_pending[cpu] = 1023;
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if (!s->enabled || !s->cpu_enabled[cpu]) {
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qemu_irq_lower(s->parent_irq[cpu]); |
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return;
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} |
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best_prio = 0x100;
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best_irq = 1023;
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for (irq = 0; irq < s->num_irq; irq++) { |
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if (GIC_TEST_ENABLED(irq, cm) && GIC_TEST_PENDING(irq, cm)) {
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if (GIC_GET_PRIORITY(irq, cpu) < best_prio) {
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best_prio = GIC_GET_PRIORITY(irq, cpu); |
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best_irq = irq; |
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} |
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} |
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} |
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level = 0;
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if (best_prio <= s->priority_mask[cpu]) {
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s->current_pending[cpu] = best_irq; |
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if (best_prio < s->running_priority[cpu]) {
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DPRINTF("Raised pending IRQ %d\n", best_irq);
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level = 1;
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} |
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} |
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qemu_set_irq(s->parent_irq[cpu], level); |
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} |
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} |
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#ifdef NVIC
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static void gic_set_pending_private(gic_state *s, int cpu, int irq) |
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{ |
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int cm = 1 << cpu; |
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if (GIC_TEST_PENDING(irq, cm))
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return;
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DPRINTF("Set %d pending cpu %d\n", irq, cpu);
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GIC_SET_PENDING(irq, cm); |
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gic_update(s); |
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} |
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#endif
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/* Process a change in an external IRQ input. */
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static void gic_set_irq(void *opaque, int irq, int level) |
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{ |
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/* Meaning of the 'irq' parameter:
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* [0..N-1] : external interrupts
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* [N..N+31] : PPI (internal) interrupts for CPU 0
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* [N+32..N+63] : PPI (internal interrupts for CPU 1
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* ...
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*/
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gic_state *s = (gic_state *)opaque; |
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int cm, target;
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if (irq < (s->num_irq - GIC_INTERNAL)) {
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/* The first external input line is internal interrupt 32. */
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cm = ALL_CPU_MASK; |
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irq += GIC_INTERNAL; |
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target = GIC_TARGET(irq); |
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} else {
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int cpu;
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irq -= (s->num_irq - GIC_INTERNAL); |
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cpu = irq / GIC_INTERNAL; |
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irq %= GIC_INTERNAL; |
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cm = 1 << cpu;
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target = cm; |
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} |
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if (level == GIC_TEST_LEVEL(irq, cm)) {
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return;
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} |
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if (level) {
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GIC_SET_LEVEL(irq, cm); |
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if (GIC_TEST_TRIGGER(irq) || GIC_TEST_ENABLED(irq, cm)) {
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DPRINTF("Set %d pending mask %x\n", irq, target);
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GIC_SET_PENDING(irq, target); |
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} |
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} else {
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GIC_CLEAR_LEVEL(irq, cm); |
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} |
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gic_update(s); |
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} |
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static void gic_set_running_irq(gic_state *s, int cpu, int irq) |
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{ |
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s->running_irq[cpu] = irq; |
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if (irq == 1023) { |
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s->running_priority[cpu] = 0x100;
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} else {
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s->running_priority[cpu] = GIC_GET_PRIORITY(irq, cpu); |
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} |
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gic_update(s); |
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} |
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static uint32_t gic_acknowledge_irq(gic_state *s, int cpu) |
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{ |
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int new_irq;
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int cm = 1 << cpu; |
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new_irq = s->current_pending[cpu]; |
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if (new_irq == 1023 |
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|| GIC_GET_PRIORITY(new_irq, cpu) >= s->running_priority[cpu]) { |
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DPRINTF("ACK no pending IRQ\n");
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return 1023; |
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} |
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s->last_active[new_irq][cpu] = s->running_irq[cpu]; |
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/* Clear pending flags for both level and edge triggered interrupts.
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Level triggered IRQs will be reasserted once they become inactive. */
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GIC_CLEAR_PENDING(new_irq, GIC_TEST_MODEL(new_irq) ? ALL_CPU_MASK : cm); |
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gic_set_running_irq(s, cpu, new_irq); |
269 |
DPRINTF("ACK %d\n", new_irq);
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return new_irq;
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} |
272 |
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static void gic_complete_irq(gic_state * s, int cpu, int irq) |
274 |
{ |
275 |
int update = 0; |
276 |
int cm = 1 << cpu; |
277 |
DPRINTF("EOI %d\n", irq);
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if (irq >= s->num_irq) {
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/* This handles two cases:
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* 1. If software writes the ID of a spurious interrupt [ie 1023]
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* to the GICC_EOIR, the GIC ignores that write.
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* 2. If software writes the number of a non-existent interrupt
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* this must be a subcase of "value written does not match the last
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* valid interrupt value read from the Interrupt Acknowledge
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* register" and so this is UNPREDICTABLE. We choose to ignore it.
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*/
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287 |
return;
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288 |
} |
289 |
if (s->running_irq[cpu] == 1023) |
290 |
return; /* No active IRQ. */ |
291 |
/* Mark level triggered interrupts as pending if they are still
|
292 |
raised. */
|
293 |
if (!GIC_TEST_TRIGGER(irq) && GIC_TEST_ENABLED(irq, cm)
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294 |
&& GIC_TEST_LEVEL(irq, cm) && (GIC_TARGET(irq) & cm) != 0) {
|
295 |
DPRINTF("Set %d pending mask %x\n", irq, cm);
|
296 |
GIC_SET_PENDING(irq, cm); |
297 |
update = 1;
|
298 |
} |
299 |
if (irq != s->running_irq[cpu]) {
|
300 |
/* Complete an IRQ that is not currently running. */
|
301 |
int tmp = s->running_irq[cpu];
|
302 |
while (s->last_active[tmp][cpu] != 1023) { |
303 |
if (s->last_active[tmp][cpu] == irq) {
|
304 |
s->last_active[tmp][cpu] = s->last_active[irq][cpu]; |
305 |
break;
|
306 |
} |
307 |
tmp = s->last_active[tmp][cpu]; |
308 |
} |
309 |
if (update) {
|
310 |
gic_update(s); |
311 |
} |
312 |
} else {
|
313 |
/* Complete the current running IRQ. */
|
314 |
gic_set_running_irq(s, cpu, s->last_active[s->running_irq[cpu]][cpu]); |
315 |
} |
316 |
} |
317 |
|
318 |
static uint32_t gic_dist_readb(void *opaque, target_phys_addr_t offset) |
319 |
{ |
320 |
gic_state *s = (gic_state *)opaque; |
321 |
uint32_t res; |
322 |
int irq;
|
323 |
int i;
|
324 |
int cpu;
|
325 |
int cm;
|
326 |
int mask;
|
327 |
|
328 |
cpu = gic_get_current_cpu(s); |
329 |
cm = 1 << cpu;
|
330 |
if (offset < 0x100) { |
331 |
#ifndef NVIC
|
332 |
if (offset == 0) |
333 |
return s->enabled;
|
334 |
if (offset == 4) |
335 |
return ((s->num_irq / 32) - 1) | ((NUM_CPU(s) - 1) << 5); |
336 |
if (offset < 0x08) |
337 |
return 0; |
338 |
if (offset >= 0x80) { |
339 |
/* Interrupt Security , RAZ/WI */
|
340 |
return 0; |
341 |
} |
342 |
#endif
|
343 |
goto bad_reg;
|
344 |
} else if (offset < 0x200) { |
345 |
/* Interrupt Set/Clear Enable. */
|
346 |
if (offset < 0x180) |
347 |
irq = (offset - 0x100) * 8; |
348 |
else
|
349 |
irq = (offset - 0x180) * 8; |
350 |
irq += GIC_BASE_IRQ; |
351 |
if (irq >= s->num_irq)
|
352 |
goto bad_reg;
|
353 |
res = 0;
|
354 |
for (i = 0; i < 8; i++) { |
355 |
if (GIC_TEST_ENABLED(irq + i, cm)) {
|
356 |
res |= (1 << i);
|
357 |
} |
358 |
} |
359 |
} else if (offset < 0x300) { |
360 |
/* Interrupt Set/Clear Pending. */
|
361 |
if (offset < 0x280) |
362 |
irq = (offset - 0x200) * 8; |
363 |
else
|
364 |
irq = (offset - 0x280) * 8; |
365 |
irq += GIC_BASE_IRQ; |
366 |
if (irq >= s->num_irq)
|
367 |
goto bad_reg;
|
368 |
res = 0;
|
369 |
mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK; |
370 |
for (i = 0; i < 8; i++) { |
371 |
if (GIC_TEST_PENDING(irq + i, mask)) {
|
372 |
res |= (1 << i);
|
373 |
} |
374 |
} |
375 |
} else if (offset < 0x400) { |
376 |
/* Interrupt Active. */
|
377 |
irq = (offset - 0x300) * 8 + GIC_BASE_IRQ; |
378 |
if (irq >= s->num_irq)
|
379 |
goto bad_reg;
|
380 |
res = 0;
|
381 |
mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK; |
382 |
for (i = 0; i < 8; i++) { |
383 |
if (GIC_TEST_ACTIVE(irq + i, mask)) {
|
384 |
res |= (1 << i);
|
385 |
} |
386 |
} |
387 |
} else if (offset < 0x800) { |
388 |
/* Interrupt Priority. */
|
389 |
irq = (offset - 0x400) + GIC_BASE_IRQ;
|
390 |
if (irq >= s->num_irq)
|
391 |
goto bad_reg;
|
392 |
res = GIC_GET_PRIORITY(irq, cpu); |
393 |
#ifndef NVIC
|
394 |
} else if (offset < 0xc00) { |
395 |
/* Interrupt CPU Target. */
|
396 |
irq = (offset - 0x800) + GIC_BASE_IRQ;
|
397 |
if (irq >= s->num_irq)
|
398 |
goto bad_reg;
|
399 |
if (irq >= 29 && irq <= 31) { |
400 |
res = cm; |
401 |
} else {
|
402 |
res = GIC_TARGET(irq); |
403 |
} |
404 |
} else if (offset < 0xf00) { |
405 |
/* Interrupt Configuration. */
|
406 |
irq = (offset - 0xc00) * 2 + GIC_BASE_IRQ; |
407 |
if (irq >= s->num_irq)
|
408 |
goto bad_reg;
|
409 |
res = 0;
|
410 |
for (i = 0; i < 4; i++) { |
411 |
if (GIC_TEST_MODEL(irq + i))
|
412 |
res |= (1 << (i * 2)); |
413 |
if (GIC_TEST_TRIGGER(irq + i))
|
414 |
res |= (2 << (i * 2)); |
415 |
} |
416 |
#endif
|
417 |
} else if (offset < 0xfe0) { |
418 |
goto bad_reg;
|
419 |
} else /* offset >= 0xfe0 */ { |
420 |
if (offset & 3) { |
421 |
res = 0;
|
422 |
} else {
|
423 |
res = gic_id[(offset - 0xfe0) >> 2]; |
424 |
} |
425 |
} |
426 |
return res;
|
427 |
bad_reg:
|
428 |
hw_error("gic_dist_readb: Bad offset %x\n", (int)offset); |
429 |
return 0; |
430 |
} |
431 |
|
432 |
static uint32_t gic_dist_readw(void *opaque, target_phys_addr_t offset) |
433 |
{ |
434 |
uint32_t val; |
435 |
val = gic_dist_readb(opaque, offset); |
436 |
val |= gic_dist_readb(opaque, offset + 1) << 8; |
437 |
return val;
|
438 |
} |
439 |
|
440 |
static uint32_t gic_dist_readl(void *opaque, target_phys_addr_t offset) |
441 |
{ |
442 |
uint32_t val; |
443 |
#ifdef NVIC
|
444 |
gic_state *s = (gic_state *)opaque; |
445 |
uint32_t addr; |
446 |
addr = offset; |
447 |
if (addr < 0x100 || addr > 0xd00) |
448 |
return nvic_readl(s, addr);
|
449 |
#endif
|
450 |
val = gic_dist_readw(opaque, offset); |
451 |
val |= gic_dist_readw(opaque, offset + 2) << 16; |
452 |
return val;
|
453 |
} |
454 |
|
455 |
static void gic_dist_writeb(void *opaque, target_phys_addr_t offset, |
456 |
uint32_t value) |
457 |
{ |
458 |
gic_state *s = (gic_state *)opaque; |
459 |
int irq;
|
460 |
int i;
|
461 |
int cpu;
|
462 |
|
463 |
cpu = gic_get_current_cpu(s); |
464 |
if (offset < 0x100) { |
465 |
#ifdef NVIC
|
466 |
goto bad_reg;
|
467 |
#else
|
468 |
if (offset == 0) { |
469 |
s->enabled = (value & 1);
|
470 |
DPRINTF("Distribution %sabled\n", s->enabled ? "En" : "Dis"); |
471 |
} else if (offset < 4) { |
472 |
/* ignored. */
|
473 |
} else if (offset >= 0x80) { |
474 |
/* Interrupt Security Registers, RAZ/WI */
|
475 |
} else {
|
476 |
goto bad_reg;
|
477 |
} |
478 |
#endif
|
479 |
} else if (offset < 0x180) { |
480 |
/* Interrupt Set Enable. */
|
481 |
irq = (offset - 0x100) * 8 + GIC_BASE_IRQ; |
482 |
if (irq >= s->num_irq)
|
483 |
goto bad_reg;
|
484 |
if (irq < 16) |
485 |
value = 0xff;
|
486 |
for (i = 0; i < 8; i++) { |
487 |
if (value & (1 << i)) { |
488 |
int mask = (irq < GIC_INTERNAL) ? (1 << cpu) : GIC_TARGET(irq); |
489 |
int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; |
490 |
|
491 |
if (!GIC_TEST_ENABLED(irq + i, cm)) {
|
492 |
DPRINTF("Enabled IRQ %d\n", irq + i);
|
493 |
} |
494 |
GIC_SET_ENABLED(irq + i, cm); |
495 |
/* If a raised level triggered IRQ enabled then mark
|
496 |
is as pending. */
|
497 |
if (GIC_TEST_LEVEL(irq + i, mask)
|
498 |
&& !GIC_TEST_TRIGGER(irq + i)) { |
499 |
DPRINTF("Set %d pending mask %x\n", irq + i, mask);
|
500 |
GIC_SET_PENDING(irq + i, mask); |
501 |
} |
502 |
} |
503 |
} |
504 |
} else if (offset < 0x200) { |
505 |
/* Interrupt Clear Enable. */
|
506 |
irq = (offset - 0x180) * 8 + GIC_BASE_IRQ; |
507 |
if (irq >= s->num_irq)
|
508 |
goto bad_reg;
|
509 |
if (irq < 16) |
510 |
value = 0;
|
511 |
for (i = 0; i < 8; i++) { |
512 |
if (value & (1 << i)) { |
513 |
int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; |
514 |
|
515 |
if (GIC_TEST_ENABLED(irq + i, cm)) {
|
516 |
DPRINTF("Disabled IRQ %d\n", irq + i);
|
517 |
} |
518 |
GIC_CLEAR_ENABLED(irq + i, cm); |
519 |
} |
520 |
} |
521 |
} else if (offset < 0x280) { |
522 |
/* Interrupt Set Pending. */
|
523 |
irq = (offset - 0x200) * 8 + GIC_BASE_IRQ; |
524 |
if (irq >= s->num_irq)
|
525 |
goto bad_reg;
|
526 |
if (irq < 16) |
527 |
irq = 0;
|
528 |
|
529 |
for (i = 0; i < 8; i++) { |
530 |
if (value & (1 << i)) { |
531 |
GIC_SET_PENDING(irq + i, GIC_TARGET(irq)); |
532 |
} |
533 |
} |
534 |
} else if (offset < 0x300) { |
535 |
/* Interrupt Clear Pending. */
|
536 |
irq = (offset - 0x280) * 8 + GIC_BASE_IRQ; |
537 |
if (irq >= s->num_irq)
|
538 |
goto bad_reg;
|
539 |
for (i = 0; i < 8; i++) { |
540 |
/* ??? This currently clears the pending bit for all CPUs, even
|
541 |
for per-CPU interrupts. It's unclear whether this is the
|
542 |
corect behavior. */
|
543 |
if (value & (1 << i)) { |
544 |
GIC_CLEAR_PENDING(irq + i, ALL_CPU_MASK); |
545 |
} |
546 |
} |
547 |
} else if (offset < 0x400) { |
548 |
/* Interrupt Active. */
|
549 |
goto bad_reg;
|
550 |
} else if (offset < 0x800) { |
551 |
/* Interrupt Priority. */
|
552 |
irq = (offset - 0x400) + GIC_BASE_IRQ;
|
553 |
if (irq >= s->num_irq)
|
554 |
goto bad_reg;
|
555 |
if (irq < GIC_INTERNAL) {
|
556 |
s->priority1[irq][cpu] = value; |
557 |
} else {
|
558 |
s->priority2[irq - GIC_INTERNAL] = value; |
559 |
} |
560 |
#ifndef NVIC
|
561 |
} else if (offset < 0xc00) { |
562 |
/* Interrupt CPU Target. */
|
563 |
irq = (offset - 0x800) + GIC_BASE_IRQ;
|
564 |
if (irq >= s->num_irq)
|
565 |
goto bad_reg;
|
566 |
if (irq < 29) |
567 |
value = 0;
|
568 |
else if (irq < GIC_INTERNAL) |
569 |
value = ALL_CPU_MASK; |
570 |
s->irq_target[irq] = value & ALL_CPU_MASK; |
571 |
} else if (offset < 0xf00) { |
572 |
/* Interrupt Configuration. */
|
573 |
irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ; |
574 |
if (irq >= s->num_irq)
|
575 |
goto bad_reg;
|
576 |
if (irq < GIC_INTERNAL)
|
577 |
value |= 0xaa;
|
578 |
for (i = 0; i < 4; i++) { |
579 |
if (value & (1 << (i * 2))) { |
580 |
GIC_SET_MODEL(irq + i); |
581 |
} else {
|
582 |
GIC_CLEAR_MODEL(irq + i); |
583 |
} |
584 |
if (value & (2 << (i * 2))) { |
585 |
GIC_SET_TRIGGER(irq + i); |
586 |
} else {
|
587 |
GIC_CLEAR_TRIGGER(irq + i); |
588 |
} |
589 |
} |
590 |
#endif
|
591 |
} else {
|
592 |
/* 0xf00 is only handled for 32-bit writes. */
|
593 |
goto bad_reg;
|
594 |
} |
595 |
gic_update(s); |
596 |
return;
|
597 |
bad_reg:
|
598 |
hw_error("gic_dist_writeb: Bad offset %x\n", (int)offset); |
599 |
} |
600 |
|
601 |
static void gic_dist_writew(void *opaque, target_phys_addr_t offset, |
602 |
uint32_t value) |
603 |
{ |
604 |
gic_dist_writeb(opaque, offset, value & 0xff);
|
605 |
gic_dist_writeb(opaque, offset + 1, value >> 8); |
606 |
} |
607 |
|
608 |
static void gic_dist_writel(void *opaque, target_phys_addr_t offset, |
609 |
uint32_t value) |
610 |
{ |
611 |
gic_state *s = (gic_state *)opaque; |
612 |
#ifdef NVIC
|
613 |
uint32_t addr; |
614 |
addr = offset; |
615 |
if (addr < 0x100 || (addr > 0xd00 && addr != 0xf00)) { |
616 |
nvic_writel(s, addr, value); |
617 |
return;
|
618 |
} |
619 |
#endif
|
620 |
if (offset == 0xf00) { |
621 |
int cpu;
|
622 |
int irq;
|
623 |
int mask;
|
624 |
|
625 |
cpu = gic_get_current_cpu(s); |
626 |
irq = value & 0x3ff;
|
627 |
switch ((value >> 24) & 3) { |
628 |
case 0: |
629 |
mask = (value >> 16) & ALL_CPU_MASK;
|
630 |
break;
|
631 |
case 1: |
632 |
mask = ALL_CPU_MASK ^ (1 << cpu);
|
633 |
break;
|
634 |
case 2: |
635 |
mask = 1 << cpu;
|
636 |
break;
|
637 |
default:
|
638 |
DPRINTF("Bad Soft Int target filter\n");
|
639 |
mask = ALL_CPU_MASK; |
640 |
break;
|
641 |
} |
642 |
GIC_SET_PENDING(irq, mask); |
643 |
gic_update(s); |
644 |
return;
|
645 |
} |
646 |
gic_dist_writew(opaque, offset, value & 0xffff);
|
647 |
gic_dist_writew(opaque, offset + 2, value >> 16); |
648 |
} |
649 |
|
650 |
static const MemoryRegionOps gic_dist_ops = { |
651 |
.old_mmio = { |
652 |
.read = { gic_dist_readb, gic_dist_readw, gic_dist_readl, }, |
653 |
.write = { gic_dist_writeb, gic_dist_writew, gic_dist_writel, }, |
654 |
}, |
655 |
.endianness = DEVICE_NATIVE_ENDIAN, |
656 |
}; |
657 |
|
658 |
#ifndef NVIC
|
659 |
static uint32_t gic_cpu_read(gic_state *s, int cpu, int offset) |
660 |
{ |
661 |
switch (offset) {
|
662 |
case 0x00: /* Control */ |
663 |
return s->cpu_enabled[cpu];
|
664 |
case 0x04: /* Priority mask */ |
665 |
return s->priority_mask[cpu];
|
666 |
case 0x08: /* Binary Point */ |
667 |
/* ??? Not implemented. */
|
668 |
return 0; |
669 |
case 0x0c: /* Acknowledge */ |
670 |
return gic_acknowledge_irq(s, cpu);
|
671 |
case 0x14: /* Running Priority */ |
672 |
return s->running_priority[cpu];
|
673 |
case 0x18: /* Highest Pending Interrupt */ |
674 |
return s->current_pending[cpu];
|
675 |
default:
|
676 |
hw_error("gic_cpu_read: Bad offset %x\n", (int)offset); |
677 |
return 0; |
678 |
} |
679 |
} |
680 |
|
681 |
static void gic_cpu_write(gic_state *s, int cpu, int offset, uint32_t value) |
682 |
{ |
683 |
switch (offset) {
|
684 |
case 0x00: /* Control */ |
685 |
s->cpu_enabled[cpu] = (value & 1);
|
686 |
DPRINTF("CPU %d %sabled\n", cpu, s->cpu_enabled ? "En" : "Dis"); |
687 |
break;
|
688 |
case 0x04: /* Priority mask */ |
689 |
s->priority_mask[cpu] = (value & 0xff);
|
690 |
break;
|
691 |
case 0x08: /* Binary Point */ |
692 |
/* ??? Not implemented. */
|
693 |
break;
|
694 |
case 0x10: /* End Of Interrupt */ |
695 |
return gic_complete_irq(s, cpu, value & 0x3ff); |
696 |
default:
|
697 |
hw_error("gic_cpu_write: Bad offset %x\n", (int)offset); |
698 |
return;
|
699 |
} |
700 |
gic_update(s); |
701 |
} |
702 |
|
703 |
/* Wrappers to read/write the GIC CPU interface for the current CPU */
|
704 |
static uint64_t gic_thiscpu_read(void *opaque, target_phys_addr_t addr, |
705 |
unsigned size)
|
706 |
{ |
707 |
gic_state *s = (gic_state *)opaque; |
708 |
return gic_cpu_read(s, gic_get_current_cpu(s), addr);
|
709 |
} |
710 |
|
711 |
static void gic_thiscpu_write(void *opaque, target_phys_addr_t addr, |
712 |
uint64_t value, unsigned size)
|
713 |
{ |
714 |
gic_state *s = (gic_state *)opaque; |
715 |
gic_cpu_write(s, gic_get_current_cpu(s), addr, value); |
716 |
} |
717 |
|
718 |
/* Wrappers to read/write the GIC CPU interface for a specific CPU.
|
719 |
* These just decode the opaque pointer into gic_state* + cpu id.
|
720 |
*/
|
721 |
static uint64_t gic_do_cpu_read(void *opaque, target_phys_addr_t addr, |
722 |
unsigned size)
|
723 |
{ |
724 |
gic_state **backref = (gic_state **)opaque; |
725 |
gic_state *s = *backref; |
726 |
int id = (backref - s->backref);
|
727 |
return gic_cpu_read(s, id, addr);
|
728 |
} |
729 |
|
730 |
static void gic_do_cpu_write(void *opaque, target_phys_addr_t addr, |
731 |
uint64_t value, unsigned size)
|
732 |
{ |
733 |
gic_state **backref = (gic_state **)opaque; |
734 |
gic_state *s = *backref; |
735 |
int id = (backref - s->backref);
|
736 |
gic_cpu_write(s, id, addr, value); |
737 |
} |
738 |
|
739 |
static const MemoryRegionOps gic_thiscpu_ops = { |
740 |
.read = gic_thiscpu_read, |
741 |
.write = gic_thiscpu_write, |
742 |
.endianness = DEVICE_NATIVE_ENDIAN, |
743 |
}; |
744 |
|
745 |
static const MemoryRegionOps gic_cpu_ops = { |
746 |
.read = gic_do_cpu_read, |
747 |
.write = gic_do_cpu_write, |
748 |
.endianness = DEVICE_NATIVE_ENDIAN, |
749 |
}; |
750 |
#endif
|
751 |
|
752 |
static void gic_reset(DeviceState *dev) |
753 |
{ |
754 |
gic_state *s = FROM_SYSBUS(gic_state, sysbus_from_qdev(dev)); |
755 |
int i;
|
756 |
memset(s->irq_state, 0, GIC_MAXIRQ * sizeof(gic_irq_state)); |
757 |
for (i = 0 ; i < NUM_CPU(s); i++) { |
758 |
s->priority_mask[i] = 0xf0;
|
759 |
s->current_pending[i] = 1023;
|
760 |
s->running_irq[i] = 1023;
|
761 |
s->running_priority[i] = 0x100;
|
762 |
#ifdef NVIC
|
763 |
/* The NVIC doesn't have per-cpu interfaces, so enable by default. */
|
764 |
s->cpu_enabled[i] = 1;
|
765 |
#else
|
766 |
s->cpu_enabled[i] = 0;
|
767 |
#endif
|
768 |
} |
769 |
for (i = 0; i < 16; i++) { |
770 |
GIC_SET_ENABLED(i, ALL_CPU_MASK); |
771 |
GIC_SET_TRIGGER(i); |
772 |
} |
773 |
#ifdef NVIC
|
774 |
/* The NVIC is always enabled. */
|
775 |
s->enabled = 1;
|
776 |
#else
|
777 |
s->enabled = 0;
|
778 |
#endif
|
779 |
} |
780 |
|
781 |
static void gic_save(QEMUFile *f, void *opaque) |
782 |
{ |
783 |
gic_state *s = (gic_state *)opaque; |
784 |
int i;
|
785 |
int j;
|
786 |
|
787 |
qemu_put_be32(f, s->enabled); |
788 |
for (i = 0; i < NUM_CPU(s); i++) { |
789 |
qemu_put_be32(f, s->cpu_enabled[i]); |
790 |
for (j = 0; j < GIC_INTERNAL; j++) |
791 |
qemu_put_be32(f, s->priority1[j][i]); |
792 |
for (j = 0; j < s->num_irq; j++) |
793 |
qemu_put_be32(f, s->last_active[j][i]); |
794 |
qemu_put_be32(f, s->priority_mask[i]); |
795 |
qemu_put_be32(f, s->running_irq[i]); |
796 |
qemu_put_be32(f, s->running_priority[i]); |
797 |
qemu_put_be32(f, s->current_pending[i]); |
798 |
} |
799 |
for (i = 0; i < s->num_irq - GIC_INTERNAL; i++) { |
800 |
qemu_put_be32(f, s->priority2[i]); |
801 |
} |
802 |
for (i = 0; i < s->num_irq; i++) { |
803 |
#ifndef NVIC
|
804 |
qemu_put_be32(f, s->irq_target[i]); |
805 |
#endif
|
806 |
qemu_put_byte(f, s->irq_state[i].enabled); |
807 |
qemu_put_byte(f, s->irq_state[i].pending); |
808 |
qemu_put_byte(f, s->irq_state[i].active); |
809 |
qemu_put_byte(f, s->irq_state[i].level); |
810 |
qemu_put_byte(f, s->irq_state[i].model); |
811 |
qemu_put_byte(f, s->irq_state[i].trigger); |
812 |
} |
813 |
} |
814 |
|
815 |
static int gic_load(QEMUFile *f, void *opaque, int version_id) |
816 |
{ |
817 |
gic_state *s = (gic_state *)opaque; |
818 |
int i;
|
819 |
int j;
|
820 |
|
821 |
if (version_id != 2) |
822 |
return -EINVAL;
|
823 |
|
824 |
s->enabled = qemu_get_be32(f); |
825 |
for (i = 0; i < NUM_CPU(s); i++) { |
826 |
s->cpu_enabled[i] = qemu_get_be32(f); |
827 |
for (j = 0; j < GIC_INTERNAL; j++) |
828 |
s->priority1[j][i] = qemu_get_be32(f); |
829 |
for (j = 0; j < s->num_irq; j++) |
830 |
s->last_active[j][i] = qemu_get_be32(f); |
831 |
s->priority_mask[i] = qemu_get_be32(f); |
832 |
s->running_irq[i] = qemu_get_be32(f); |
833 |
s->running_priority[i] = qemu_get_be32(f); |
834 |
s->current_pending[i] = qemu_get_be32(f); |
835 |
} |
836 |
for (i = 0; i < s->num_irq - GIC_INTERNAL; i++) { |
837 |
s->priority2[i] = qemu_get_be32(f); |
838 |
} |
839 |
for (i = 0; i < s->num_irq; i++) { |
840 |
#ifndef NVIC
|
841 |
s->irq_target[i] = qemu_get_be32(f); |
842 |
#endif
|
843 |
s->irq_state[i].enabled = qemu_get_byte(f); |
844 |
s->irq_state[i].pending = qemu_get_byte(f); |
845 |
s->irq_state[i].active = qemu_get_byte(f); |
846 |
s->irq_state[i].level = qemu_get_byte(f); |
847 |
s->irq_state[i].model = qemu_get_byte(f); |
848 |
s->irq_state[i].trigger = qemu_get_byte(f); |
849 |
} |
850 |
|
851 |
return 0; |
852 |
} |
853 |
|
854 |
#if NCPU > 1 |
855 |
static void gic_init(gic_state *s, int num_cpu, int num_irq) |
856 |
#else
|
857 |
static void gic_init(gic_state *s, int num_irq) |
858 |
#endif
|
859 |
{ |
860 |
int i;
|
861 |
|
862 |
#if NCPU > 1 |
863 |
s->num_cpu = num_cpu; |
864 |
if (s->num_cpu > NCPU) {
|
865 |
hw_error("requested %u CPUs exceeds GIC maximum %d\n",
|
866 |
num_cpu, NCPU); |
867 |
} |
868 |
#endif
|
869 |
s->num_irq = num_irq + GIC_BASE_IRQ; |
870 |
if (s->num_irq > GIC_MAXIRQ) {
|
871 |
hw_error("requested %u interrupt lines exceeds GIC maximum %d\n",
|
872 |
num_irq, GIC_MAXIRQ); |
873 |
} |
874 |
/* ITLinesNumber is represented as (N / 32) - 1 (see
|
875 |
* gic_dist_readb) so this is an implementation imposed
|
876 |
* restriction, not an architectural one:
|
877 |
*/
|
878 |
if (s->num_irq < 32 || (s->num_irq % 32)) { |
879 |
hw_error("%d interrupt lines unsupported: not divisible by 32\n",
|
880 |
num_irq); |
881 |
} |
882 |
|
883 |
i = s->num_irq - GIC_INTERNAL; |
884 |
#ifndef NVIC
|
885 |
/* For the GIC, also expose incoming GPIO lines for PPIs for each CPU.
|
886 |
* GPIO array layout is thus:
|
887 |
* [0..N-1] SPIs
|
888 |
* [N..N+31] PPIs for CPU 0
|
889 |
* [N+32..N+63] PPIs for CPU 1
|
890 |
* ...
|
891 |
*/
|
892 |
i += (GIC_INTERNAL * num_cpu); |
893 |
#endif
|
894 |
qdev_init_gpio_in(&s->busdev.qdev, gic_set_irq, i); |
895 |
for (i = 0; i < NUM_CPU(s); i++) { |
896 |
sysbus_init_irq(&s->busdev, &s->parent_irq[i]); |
897 |
} |
898 |
memory_region_init_io(&s->iomem, &gic_dist_ops, s, "gic_dist", 0x1000); |
899 |
#ifndef NVIC
|
900 |
/* Memory regions for the CPU interfaces (NVIC doesn't have these):
|
901 |
* a region for "CPU interface for this core", then a region for
|
902 |
* "CPU interface for core 0", "for core 1", ...
|
903 |
* NB that the memory region size of 0x100 applies for the 11MPCore
|
904 |
* and also cores following the GIC v1 spec (ie A9).
|
905 |
* GIC v2 defines a larger memory region (0x1000) so this will need
|
906 |
* to be extended when we implement A15.
|
907 |
*/
|
908 |
memory_region_init_io(&s->cpuiomem[0], &gic_thiscpu_ops, s,
|
909 |
"gic_cpu", 0x100); |
910 |
for (i = 0; i < NUM_CPU(s); i++) { |
911 |
s->backref[i] = s; |
912 |
memory_region_init_io(&s->cpuiomem[i+1], &gic_cpu_ops, &s->backref[i],
|
913 |
"gic_cpu", 0x100); |
914 |
} |
915 |
#endif
|
916 |
|
917 |
register_savevm(NULL, "arm_gic", -1, 2, gic_save, gic_load, s); |
918 |
} |
919 |
|
920 |
#ifndef NVIC
|
921 |
|
922 |
static int arm_gic_init(SysBusDevice *dev) |
923 |
{ |
924 |
/* Device instance init function for the GIC sysbus device */
|
925 |
int i;
|
926 |
gic_state *s = FROM_SYSBUS(gic_state, dev); |
927 |
gic_init(s, s->num_cpu, s->num_irq); |
928 |
/* Distributor */
|
929 |
sysbus_init_mmio(dev, &s->iomem); |
930 |
/* cpu interfaces (one for "current cpu" plus one per cpu) */
|
931 |
for (i = 0; i <= NUM_CPU(s); i++) { |
932 |
sysbus_init_mmio(dev, &s->cpuiomem[i]); |
933 |
} |
934 |
return 0; |
935 |
} |
936 |
|
937 |
static Property arm_gic_properties[] = {
|
938 |
DEFINE_PROP_UINT32("num-cpu", gic_state, num_cpu, 1), |
939 |
DEFINE_PROP_UINT32("num-irq", gic_state, num_irq, 32), |
940 |
DEFINE_PROP_END_OF_LIST(), |
941 |
}; |
942 |
|
943 |
static void arm_gic_class_init(ObjectClass *klass, void *data) |
944 |
{ |
945 |
DeviceClass *dc = DEVICE_CLASS(klass); |
946 |
SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass); |
947 |
sbc->init = arm_gic_init; |
948 |
dc->props = arm_gic_properties; |
949 |
dc->reset = gic_reset; |
950 |
dc->no_user = 1;
|
951 |
} |
952 |
|
953 |
static TypeInfo arm_gic_info = {
|
954 |
.name = "arm_gic",
|
955 |
.parent = TYPE_SYS_BUS_DEVICE, |
956 |
.instance_size = sizeof(gic_state),
|
957 |
.class_init = arm_gic_class_init, |
958 |
}; |
959 |
|
960 |
static void arm_gic_register_types(void) |
961 |
{ |
962 |
type_register_static(&arm_gic_info); |
963 |
} |
964 |
|
965 |
type_init(arm_gic_register_types) |
966 |
|
967 |
#endif
|