root / hw / ppc4xx_pci.c @ 7bd427d8
History | View | Annotate | Download (10.5 kB)
1 | 825bb581 | aurel32 | /*
|
---|---|---|---|
2 | 825bb581 | aurel32 | * This program is free software; you can redistribute it and/or modify
|
3 | 825bb581 | aurel32 | * it under the terms of the GNU General Public License, version 2, as
|
4 | 825bb581 | aurel32 | * published by the Free Software Foundation.
|
5 | 825bb581 | aurel32 | *
|
6 | 825bb581 | aurel32 | * This program is distributed in the hope that it will be useful,
|
7 | 825bb581 | aurel32 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
8 | 825bb581 | aurel32 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
9 | 825bb581 | aurel32 | * GNU General Public License for more details.
|
10 | 825bb581 | aurel32 | *
|
11 | 825bb581 | aurel32 | * You should have received a copy of the GNU General Public License
|
12 | 8167ee88 | Blue Swirl | * along with this program; if not, see <http://www.gnu.org/licenses/>.
|
13 | 825bb581 | aurel32 | *
|
14 | 825bb581 | aurel32 | * Copyright IBM Corp. 2008
|
15 | 825bb581 | aurel32 | *
|
16 | 825bb581 | aurel32 | * Authors: Hollis Blanchard <hollisb@us.ibm.com>
|
17 | 825bb581 | aurel32 | */
|
18 | 825bb581 | aurel32 | |
19 | 825bb581 | aurel32 | /* This file implements emulation of the 32-bit PCI controller found in some
|
20 | 825bb581 | aurel32 | * 4xx SoCs, such as the 440EP. */
|
21 | 825bb581 | aurel32 | |
22 | 825bb581 | aurel32 | #include "hw.h" |
23 | 0c34a5d7 | aurel32 | #include "ppc.h" |
24 | 0c34a5d7 | aurel32 | #include "ppc4xx.h" |
25 | 825bb581 | aurel32 | #include "pci.h" |
26 | 825bb581 | aurel32 | #include "pci_host.h" |
27 | 825bb581 | aurel32 | |
28 | 825bb581 | aurel32 | #undef DEBUG
|
29 | 825bb581 | aurel32 | #ifdef DEBUG
|
30 | 825bb581 | aurel32 | #define DPRINTF(fmt, ...) do { printf(fmt, ## __VA_ARGS__); } while (0) |
31 | 825bb581 | aurel32 | #else
|
32 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...)
|
33 | 825bb581 | aurel32 | #endif /* DEBUG */ |
34 | 825bb581 | aurel32 | |
35 | 825bb581 | aurel32 | struct PCIMasterMap {
|
36 | 825bb581 | aurel32 | uint32_t la; |
37 | 825bb581 | aurel32 | uint32_t ma; |
38 | 825bb581 | aurel32 | uint32_t pcila; |
39 | 825bb581 | aurel32 | uint32_t pciha; |
40 | 825bb581 | aurel32 | }; |
41 | 825bb581 | aurel32 | |
42 | 825bb581 | aurel32 | struct PCITargetMap {
|
43 | 825bb581 | aurel32 | uint32_t ms; |
44 | 825bb581 | aurel32 | uint32_t la; |
45 | 825bb581 | aurel32 | }; |
46 | 825bb581 | aurel32 | |
47 | 825bb581 | aurel32 | #define PPC4xx_PCI_NR_PMMS 3 |
48 | 825bb581 | aurel32 | #define PPC4xx_PCI_NR_PTMS 2 |
49 | 825bb581 | aurel32 | |
50 | 825bb581 | aurel32 | struct PPC4xxPCIState {
|
51 | 825bb581 | aurel32 | struct PCIMasterMap pmm[PPC4xx_PCI_NR_PMMS];
|
52 | 825bb581 | aurel32 | struct PCITargetMap ptm[PPC4xx_PCI_NR_PTMS];
|
53 | 825bb581 | aurel32 | |
54 | 825bb581 | aurel32 | PCIHostState pci_state; |
55 | 825bb581 | aurel32 | PCIDevice *pci_dev; |
56 | 825bb581 | aurel32 | }; |
57 | 825bb581 | aurel32 | typedef struct PPC4xxPCIState PPC4xxPCIState; |
58 | 825bb581 | aurel32 | |
59 | 825bb581 | aurel32 | #define PCIC0_CFGADDR 0x0 |
60 | 825bb581 | aurel32 | #define PCIC0_CFGDATA 0x4 |
61 | 825bb581 | aurel32 | |
62 | 825bb581 | aurel32 | /* PLB Memory Map (PMM) registers specify which PLB addresses are translated to
|
63 | 825bb581 | aurel32 | * PCI accesses. */
|
64 | 825bb581 | aurel32 | #define PCIL0_PMM0LA 0x0 |
65 | 825bb581 | aurel32 | #define PCIL0_PMM0MA 0x4 |
66 | 825bb581 | aurel32 | #define PCIL0_PMM0PCILA 0x8 |
67 | 825bb581 | aurel32 | #define PCIL0_PMM0PCIHA 0xc |
68 | 825bb581 | aurel32 | #define PCIL0_PMM1LA 0x10 |
69 | 825bb581 | aurel32 | #define PCIL0_PMM1MA 0x14 |
70 | 825bb581 | aurel32 | #define PCIL0_PMM1PCILA 0x18 |
71 | 825bb581 | aurel32 | #define PCIL0_PMM1PCIHA 0x1c |
72 | 825bb581 | aurel32 | #define PCIL0_PMM2LA 0x20 |
73 | 825bb581 | aurel32 | #define PCIL0_PMM2MA 0x24 |
74 | 825bb581 | aurel32 | #define PCIL0_PMM2PCILA 0x28 |
75 | 825bb581 | aurel32 | #define PCIL0_PMM2PCIHA 0x2c |
76 | 825bb581 | aurel32 | |
77 | 825bb581 | aurel32 | /* PCI Target Map (PTM) registers specify which PCI addresses are translated to
|
78 | 825bb581 | aurel32 | * PLB accesses. */
|
79 | 825bb581 | aurel32 | #define PCIL0_PTM1MS 0x30 |
80 | 825bb581 | aurel32 | #define PCIL0_PTM1LA 0x34 |
81 | 825bb581 | aurel32 | #define PCIL0_PTM2MS 0x38 |
82 | 825bb581 | aurel32 | #define PCIL0_PTM2LA 0x3c |
83 | 825bb581 | aurel32 | #define PCI_REG_SIZE 0x40 |
84 | 825bb581 | aurel32 | |
85 | 825bb581 | aurel32 | |
86 | c227f099 | Anthony Liguori | static uint32_t pci4xx_cfgaddr_readl(void *opaque, target_phys_addr_t addr) |
87 | 825bb581 | aurel32 | { |
88 | 825bb581 | aurel32 | PPC4xxPCIState *ppc4xx_pci = opaque; |
89 | 825bb581 | aurel32 | |
90 | 825bb581 | aurel32 | return ppc4xx_pci->pci_state.config_reg;
|
91 | 825bb581 | aurel32 | } |
92 | 825bb581 | aurel32 | |
93 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const pci4xx_cfgaddr_read[] = { |
94 | 825bb581 | aurel32 | &pci4xx_cfgaddr_readl, |
95 | 825bb581 | aurel32 | &pci4xx_cfgaddr_readl, |
96 | 825bb581 | aurel32 | &pci4xx_cfgaddr_readl, |
97 | 825bb581 | aurel32 | }; |
98 | 825bb581 | aurel32 | |
99 | c227f099 | Anthony Liguori | static void pci4xx_cfgaddr_writel(void *opaque, target_phys_addr_t addr, |
100 | 825bb581 | aurel32 | uint32_t value) |
101 | 825bb581 | aurel32 | { |
102 | 825bb581 | aurel32 | PPC4xxPCIState *ppc4xx_pci = opaque; |
103 | 825bb581 | aurel32 | |
104 | 825bb581 | aurel32 | ppc4xx_pci->pci_state.config_reg = value & ~0x3;
|
105 | 825bb581 | aurel32 | } |
106 | 825bb581 | aurel32 | |
107 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const pci4xx_cfgaddr_write[] = { |
108 | 825bb581 | aurel32 | &pci4xx_cfgaddr_writel, |
109 | 825bb581 | aurel32 | &pci4xx_cfgaddr_writel, |
110 | 825bb581 | aurel32 | &pci4xx_cfgaddr_writel, |
111 | 825bb581 | aurel32 | }; |
112 | 825bb581 | aurel32 | |
113 | c227f099 | Anthony Liguori | static void ppc4xx_pci_reg_write4(void *opaque, target_phys_addr_t offset, |
114 | 825bb581 | aurel32 | uint32_t value) |
115 | 825bb581 | aurel32 | { |
116 | 825bb581 | aurel32 | struct PPC4xxPCIState *pci = opaque;
|
117 | 825bb581 | aurel32 | |
118 | 825bb581 | aurel32 | /* We ignore all target attempts at PCI configuration, effectively
|
119 | 825bb581 | aurel32 | * assuming a bidirectional 1:1 mapping of PLB and PCI space. */
|
120 | 825bb581 | aurel32 | |
121 | 825bb581 | aurel32 | switch (offset) {
|
122 | 825bb581 | aurel32 | case PCIL0_PMM0LA:
|
123 | 825bb581 | aurel32 | pci->pmm[0].la = value;
|
124 | 825bb581 | aurel32 | break;
|
125 | 825bb581 | aurel32 | case PCIL0_PMM0MA:
|
126 | 825bb581 | aurel32 | pci->pmm[0].ma = value;
|
127 | 825bb581 | aurel32 | break;
|
128 | 825bb581 | aurel32 | case PCIL0_PMM0PCIHA:
|
129 | 825bb581 | aurel32 | pci->pmm[0].pciha = value;
|
130 | 825bb581 | aurel32 | break;
|
131 | 825bb581 | aurel32 | case PCIL0_PMM0PCILA:
|
132 | 825bb581 | aurel32 | pci->pmm[0].pcila = value;
|
133 | 825bb581 | aurel32 | break;
|
134 | 825bb581 | aurel32 | |
135 | 825bb581 | aurel32 | case PCIL0_PMM1LA:
|
136 | 825bb581 | aurel32 | pci->pmm[1].la = value;
|
137 | 825bb581 | aurel32 | break;
|
138 | 825bb581 | aurel32 | case PCIL0_PMM1MA:
|
139 | 825bb581 | aurel32 | pci->pmm[1].ma = value;
|
140 | 825bb581 | aurel32 | break;
|
141 | 825bb581 | aurel32 | case PCIL0_PMM1PCIHA:
|
142 | 825bb581 | aurel32 | pci->pmm[1].pciha = value;
|
143 | 825bb581 | aurel32 | break;
|
144 | 825bb581 | aurel32 | case PCIL0_PMM1PCILA:
|
145 | 825bb581 | aurel32 | pci->pmm[1].pcila = value;
|
146 | 825bb581 | aurel32 | break;
|
147 | 825bb581 | aurel32 | |
148 | 825bb581 | aurel32 | case PCIL0_PMM2LA:
|
149 | 825bb581 | aurel32 | pci->pmm[2].la = value;
|
150 | 825bb581 | aurel32 | break;
|
151 | 825bb581 | aurel32 | case PCIL0_PMM2MA:
|
152 | 825bb581 | aurel32 | pci->pmm[2].ma = value;
|
153 | 825bb581 | aurel32 | break;
|
154 | 825bb581 | aurel32 | case PCIL0_PMM2PCIHA:
|
155 | 825bb581 | aurel32 | pci->pmm[2].pciha = value;
|
156 | 825bb581 | aurel32 | break;
|
157 | 825bb581 | aurel32 | case PCIL0_PMM2PCILA:
|
158 | 825bb581 | aurel32 | pci->pmm[2].pcila = value;
|
159 | 825bb581 | aurel32 | break;
|
160 | 825bb581 | aurel32 | |
161 | 825bb581 | aurel32 | case PCIL0_PTM1MS:
|
162 | 825bb581 | aurel32 | pci->ptm[0].ms = value;
|
163 | 825bb581 | aurel32 | break;
|
164 | 825bb581 | aurel32 | case PCIL0_PTM1LA:
|
165 | 825bb581 | aurel32 | pci->ptm[0].la = value;
|
166 | 825bb581 | aurel32 | break;
|
167 | 825bb581 | aurel32 | case PCIL0_PTM2MS:
|
168 | 825bb581 | aurel32 | pci->ptm[1].ms = value;
|
169 | 825bb581 | aurel32 | break;
|
170 | 825bb581 | aurel32 | case PCIL0_PTM2LA:
|
171 | 825bb581 | aurel32 | pci->ptm[1].la = value;
|
172 | 825bb581 | aurel32 | break;
|
173 | 825bb581 | aurel32 | |
174 | 825bb581 | aurel32 | default:
|
175 | 825bb581 | aurel32 | printf("%s: unhandled PCI internal register 0x%lx\n", __func__,
|
176 | 825bb581 | aurel32 | (unsigned long)offset); |
177 | 825bb581 | aurel32 | break;
|
178 | 825bb581 | aurel32 | } |
179 | 825bb581 | aurel32 | } |
180 | 825bb581 | aurel32 | |
181 | c227f099 | Anthony Liguori | static uint32_t ppc4xx_pci_reg_read4(void *opaque, target_phys_addr_t offset) |
182 | 825bb581 | aurel32 | { |
183 | 825bb581 | aurel32 | struct PPC4xxPCIState *pci = opaque;
|
184 | 825bb581 | aurel32 | uint32_t value; |
185 | 825bb581 | aurel32 | |
186 | 825bb581 | aurel32 | switch (offset) {
|
187 | 825bb581 | aurel32 | case PCIL0_PMM0LA:
|
188 | 825bb581 | aurel32 | value = pci->pmm[0].la;
|
189 | 825bb581 | aurel32 | break;
|
190 | 825bb581 | aurel32 | case PCIL0_PMM0MA:
|
191 | 825bb581 | aurel32 | value = pci->pmm[0].ma;
|
192 | 825bb581 | aurel32 | break;
|
193 | 825bb581 | aurel32 | case PCIL0_PMM0PCIHA:
|
194 | 825bb581 | aurel32 | value = pci->pmm[0].pciha;
|
195 | 825bb581 | aurel32 | break;
|
196 | 825bb581 | aurel32 | case PCIL0_PMM0PCILA:
|
197 | 825bb581 | aurel32 | value = pci->pmm[0].pcila;
|
198 | 825bb581 | aurel32 | break;
|
199 | 825bb581 | aurel32 | |
200 | 825bb581 | aurel32 | case PCIL0_PMM1LA:
|
201 | 825bb581 | aurel32 | value = pci->pmm[1].la;
|
202 | 825bb581 | aurel32 | break;
|
203 | 825bb581 | aurel32 | case PCIL0_PMM1MA:
|
204 | 825bb581 | aurel32 | value = pci->pmm[1].ma;
|
205 | 825bb581 | aurel32 | break;
|
206 | 825bb581 | aurel32 | case PCIL0_PMM1PCIHA:
|
207 | 825bb581 | aurel32 | value = pci->pmm[1].pciha;
|
208 | 825bb581 | aurel32 | break;
|
209 | 825bb581 | aurel32 | case PCIL0_PMM1PCILA:
|
210 | 825bb581 | aurel32 | value = pci->pmm[1].pcila;
|
211 | 825bb581 | aurel32 | break;
|
212 | 825bb581 | aurel32 | |
213 | 825bb581 | aurel32 | case PCIL0_PMM2LA:
|
214 | 825bb581 | aurel32 | value = pci->pmm[2].la;
|
215 | 825bb581 | aurel32 | break;
|
216 | 825bb581 | aurel32 | case PCIL0_PMM2MA:
|
217 | 825bb581 | aurel32 | value = pci->pmm[2].ma;
|
218 | 825bb581 | aurel32 | break;
|
219 | 825bb581 | aurel32 | case PCIL0_PMM2PCIHA:
|
220 | 825bb581 | aurel32 | value = pci->pmm[2].pciha;
|
221 | 825bb581 | aurel32 | break;
|
222 | 825bb581 | aurel32 | case PCIL0_PMM2PCILA:
|
223 | 825bb581 | aurel32 | value = pci->pmm[2].pcila;
|
224 | 825bb581 | aurel32 | break;
|
225 | 825bb581 | aurel32 | |
226 | 825bb581 | aurel32 | case PCIL0_PTM1MS:
|
227 | 825bb581 | aurel32 | value = pci->ptm[0].ms;
|
228 | 825bb581 | aurel32 | break;
|
229 | 825bb581 | aurel32 | case PCIL0_PTM1LA:
|
230 | 825bb581 | aurel32 | value = pci->ptm[0].la;
|
231 | 825bb581 | aurel32 | break;
|
232 | 825bb581 | aurel32 | case PCIL0_PTM2MS:
|
233 | 825bb581 | aurel32 | value = pci->ptm[1].ms;
|
234 | 825bb581 | aurel32 | break;
|
235 | 825bb581 | aurel32 | case PCIL0_PTM2LA:
|
236 | 825bb581 | aurel32 | value = pci->ptm[1].la;
|
237 | 825bb581 | aurel32 | break;
|
238 | 825bb581 | aurel32 | |
239 | 825bb581 | aurel32 | default:
|
240 | 825bb581 | aurel32 | printf("%s: invalid PCI internal register 0x%lx\n", __func__,
|
241 | 825bb581 | aurel32 | (unsigned long)offset); |
242 | 825bb581 | aurel32 | value = 0;
|
243 | 825bb581 | aurel32 | } |
244 | 825bb581 | aurel32 | |
245 | 825bb581 | aurel32 | return value;
|
246 | 825bb581 | aurel32 | } |
247 | 825bb581 | aurel32 | |
248 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const pci_reg_read[] = { |
249 | 825bb581 | aurel32 | &ppc4xx_pci_reg_read4, |
250 | 825bb581 | aurel32 | &ppc4xx_pci_reg_read4, |
251 | 825bb581 | aurel32 | &ppc4xx_pci_reg_read4, |
252 | 825bb581 | aurel32 | }; |
253 | 825bb581 | aurel32 | |
254 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const pci_reg_write[] = { |
255 | 825bb581 | aurel32 | &ppc4xx_pci_reg_write4, |
256 | 825bb581 | aurel32 | &ppc4xx_pci_reg_write4, |
257 | 825bb581 | aurel32 | &ppc4xx_pci_reg_write4, |
258 | 825bb581 | aurel32 | }; |
259 | 825bb581 | aurel32 | |
260 | 825bb581 | aurel32 | static void ppc4xx_pci_reset(void *opaque) |
261 | 825bb581 | aurel32 | { |
262 | 825bb581 | aurel32 | struct PPC4xxPCIState *pci = opaque;
|
263 | 825bb581 | aurel32 | |
264 | 825bb581 | aurel32 | memset(pci->pmm, 0, sizeof(pci->pmm)); |
265 | 825bb581 | aurel32 | memset(pci->ptm, 0, sizeof(pci->ptm)); |
266 | 825bb581 | aurel32 | } |
267 | 825bb581 | aurel32 | |
268 | 825bb581 | aurel32 | /* On Bamboo, all pins from each slot are tied to a single board IRQ. This
|
269 | 825bb581 | aurel32 | * may need further refactoring for other boards. */
|
270 | 825bb581 | aurel32 | static int ppc4xx_pci_map_irq(PCIDevice *pci_dev, int irq_num) |
271 | 825bb581 | aurel32 | { |
272 | 825bb581 | aurel32 | int slot = pci_dev->devfn >> 3; |
273 | 825bb581 | aurel32 | |
274 | 825bb581 | aurel32 | DPRINTF("%s: devfn %x irq %d -> %d\n", __func__,
|
275 | 825bb581 | aurel32 | pci_dev->devfn, irq_num, slot); |
276 | 825bb581 | aurel32 | |
277 | 825bb581 | aurel32 | return slot - 1; |
278 | 825bb581 | aurel32 | } |
279 | 825bb581 | aurel32 | |
280 | 5d4e84c8 | Juan Quintela | static void ppc4xx_pci_set_irq(void *opaque, int irq_num, int level) |
281 | 825bb581 | aurel32 | { |
282 | 5d4e84c8 | Juan Quintela | qemu_irq *pci_irqs = opaque; |
283 | 5d4e84c8 | Juan Quintela | |
284 | 825bb581 | aurel32 | DPRINTF("%s: PCI irq %d\n", __func__, irq_num);
|
285 | 825bb581 | aurel32 | qemu_set_irq(pci_irqs[irq_num], level); |
286 | 825bb581 | aurel32 | } |
287 | 825bb581 | aurel32 | |
288 | 825bb581 | aurel32 | static void ppc4xx_pci_save(QEMUFile *f, void *opaque) |
289 | 825bb581 | aurel32 | { |
290 | 825bb581 | aurel32 | PPC4xxPCIState *controller = opaque; |
291 | 825bb581 | aurel32 | int i;
|
292 | 825bb581 | aurel32 | |
293 | 3476f891 | aurel32 | pci_device_save(controller->pci_dev, f); |
294 | 825bb581 | aurel32 | |
295 | 825bb581 | aurel32 | for (i = 0; i < PPC4xx_PCI_NR_PMMS; i++) { |
296 | 825bb581 | aurel32 | qemu_put_be32s(f, &controller->pmm[i].la); |
297 | 825bb581 | aurel32 | qemu_put_be32s(f, &controller->pmm[i].ma); |
298 | 825bb581 | aurel32 | qemu_put_be32s(f, &controller->pmm[i].pcila); |
299 | 825bb581 | aurel32 | qemu_put_be32s(f, &controller->pmm[i].pciha); |
300 | 825bb581 | aurel32 | } |
301 | 825bb581 | aurel32 | |
302 | 825bb581 | aurel32 | for (i = 0; i < PPC4xx_PCI_NR_PTMS; i++) { |
303 | 825bb581 | aurel32 | qemu_put_be32s(f, &controller->ptm[i].ms); |
304 | 825bb581 | aurel32 | qemu_put_be32s(f, &controller->ptm[i].la); |
305 | 825bb581 | aurel32 | } |
306 | 825bb581 | aurel32 | } |
307 | 825bb581 | aurel32 | |
308 | 825bb581 | aurel32 | static int ppc4xx_pci_load(QEMUFile *f, void *opaque, int version_id) |
309 | 825bb581 | aurel32 | { |
310 | 825bb581 | aurel32 | PPC4xxPCIState *controller = opaque; |
311 | 825bb581 | aurel32 | int i;
|
312 | 825bb581 | aurel32 | |
313 | 825bb581 | aurel32 | if (version_id != 1) |
314 | 825bb581 | aurel32 | return -EINVAL;
|
315 | 825bb581 | aurel32 | |
316 | 3476f891 | aurel32 | pci_device_load(controller->pci_dev, f); |
317 | 825bb581 | aurel32 | |
318 | 825bb581 | aurel32 | for (i = 0; i < PPC4xx_PCI_NR_PMMS; i++) { |
319 | 825bb581 | aurel32 | qemu_get_be32s(f, &controller->pmm[i].la); |
320 | 825bb581 | aurel32 | qemu_get_be32s(f, &controller->pmm[i].ma); |
321 | 825bb581 | aurel32 | qemu_get_be32s(f, &controller->pmm[i].pcila); |
322 | 825bb581 | aurel32 | qemu_get_be32s(f, &controller->pmm[i].pciha); |
323 | 825bb581 | aurel32 | } |
324 | 825bb581 | aurel32 | |
325 | 825bb581 | aurel32 | for (i = 0; i < PPC4xx_PCI_NR_PTMS; i++) { |
326 | 825bb581 | aurel32 | qemu_get_be32s(f, &controller->ptm[i].ms); |
327 | 825bb581 | aurel32 | qemu_get_be32s(f, &controller->ptm[i].la); |
328 | 825bb581 | aurel32 | } |
329 | 825bb581 | aurel32 | |
330 | 825bb581 | aurel32 | return 0; |
331 | 825bb581 | aurel32 | } |
332 | 825bb581 | aurel32 | |
333 | 825bb581 | aurel32 | /* XXX Interrupt acknowledge cycles not supported. */
|
334 | 825bb581 | aurel32 | PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4],
|
335 | c227f099 | Anthony Liguori | target_phys_addr_t config_space, |
336 | c227f099 | Anthony Liguori | target_phys_addr_t int_ack, |
337 | c227f099 | Anthony Liguori | target_phys_addr_t special_cycle, |
338 | c227f099 | Anthony Liguori | target_phys_addr_t registers) |
339 | 825bb581 | aurel32 | { |
340 | 825bb581 | aurel32 | PPC4xxPCIState *controller; |
341 | 825bb581 | aurel32 | int index;
|
342 | 825bb581 | aurel32 | static int ppc4xx_pci_id; |
343 | deb54399 | aliguori | uint8_t *pci_conf; |
344 | 825bb581 | aurel32 | |
345 | 825bb581 | aurel32 | controller = qemu_mallocz(sizeof(PPC4xxPCIState));
|
346 | 825bb581 | aurel32 | |
347 | 02e2da45 | Paul Brook | controller->pci_state.bus = pci_register_bus(NULL, "pci", |
348 | 02e2da45 | Paul Brook | ppc4xx_pci_set_irq, |
349 | 825bb581 | aurel32 | ppc4xx_pci_map_irq, |
350 | 825bb581 | aurel32 | pci_irqs, 0, 4); |
351 | 825bb581 | aurel32 | |
352 | 825bb581 | aurel32 | controller->pci_dev = pci_register_device(controller->pci_state.bus, |
353 | 825bb581 | aurel32 | "host bridge", sizeof(PCIDevice), |
354 | 825bb581 | aurel32 | 0, NULL, NULL); |
355 | deb54399 | aliguori | pci_conf = controller->pci_dev->config; |
356 | deb54399 | aliguori | pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_IBM); |
357 | a770dc7e | aliguori | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_IBM_440GX); |
358 | 173a543b | blueswir1 | pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER); |
359 | 825bb581 | aurel32 | |
360 | 825bb581 | aurel32 | /* CFGADDR */
|
361 | 1eed09cb | Avi Kivity | index = cpu_register_io_memory(pci4xx_cfgaddr_read, |
362 | 2507c12a | Alexander Graf | pci4xx_cfgaddr_write, controller, |
363 | 0d2a73b3 | Alexander Graf | DEVICE_LITTLE_ENDIAN); |
364 | 825bb581 | aurel32 | if (index < 0) |
365 | 825bb581 | aurel32 | goto free;
|
366 | 825bb581 | aurel32 | cpu_register_physical_memory(config_space + PCIC0_CFGADDR, 4, index);
|
367 | 825bb581 | aurel32 | |
368 | 825bb581 | aurel32 | /* CFGDATA */
|
369 | 952760bb | Blue Swirl | index = pci_host_data_register_mmio(&controller->pci_state, 1);
|
370 | 825bb581 | aurel32 | if (index < 0) |
371 | 825bb581 | aurel32 | goto free;
|
372 | 825bb581 | aurel32 | cpu_register_physical_memory(config_space + PCIC0_CFGDATA, 4, index);
|
373 | 825bb581 | aurel32 | |
374 | 825bb581 | aurel32 | /* Internal registers */
|
375 | 2507c12a | Alexander Graf | index = cpu_register_io_memory(pci_reg_read, pci_reg_write, controller, |
376 | 0d2a73b3 | Alexander Graf | DEVICE_LITTLE_ENDIAN); |
377 | 825bb581 | aurel32 | if (index < 0) |
378 | 825bb581 | aurel32 | goto free;
|
379 | 825bb581 | aurel32 | cpu_register_physical_memory(registers, PCI_REG_SIZE, index); |
380 | 825bb581 | aurel32 | |
381 | a08d4367 | Jan Kiszka | qemu_register_reset(ppc4xx_pci_reset, controller); |
382 | 825bb581 | aurel32 | |
383 | 825bb581 | aurel32 | /* XXX load/save code not tested. */
|
384 | 0be71e32 | Alex Williamson | register_savevm(&controller->pci_dev->qdev, "ppc4xx_pci", ppc4xx_pci_id++,
|
385 | 0be71e32 | Alex Williamson | 1, ppc4xx_pci_save, ppc4xx_pci_load, controller);
|
386 | 825bb581 | aurel32 | |
387 | 825bb581 | aurel32 | return controller->pci_state.bus;
|
388 | 825bb581 | aurel32 | |
389 | 825bb581 | aurel32 | free:
|
390 | 825bb581 | aurel32 | printf("%s error\n", __func__);
|
391 | 825bb581 | aurel32 | qemu_free(controller); |
392 | 825bb581 | aurel32 | return NULL; |
393 | 825bb581 | aurel32 | } |