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1
/*
2
 * QEMU USB OHCI Emulation
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 * Copyright (c) 2004 Gianni Tedesco
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 * Copyright (c) 2006 CodeSourcery
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 * Copyright (c) 2006 Openedhand Ltd.
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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 *
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 * TODO:
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 *  o Isochronous transfers
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 *  o Allocate bandwidth in frames properly
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 *  o Disable timers when nothing needs to be done, or remove timer usage
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 *    all together.
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 *  o Handle unrecoverable errors properly
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 *  o BIOS work to boot from USB storage
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*/
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#include "vl.h"
31

    
32
//#define DEBUG_OHCI
33
/* Dump packet contents.  */
34
//#define DEBUG_PACKET
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//#define DEBUG_ISOCH
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/* This causes frames to occur 1000x slower */
37
//#define OHCI_TIME_WARP 1
38

    
39
#ifdef DEBUG_OHCI
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#define dprintf printf
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#else
42
#define dprintf(...)
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#endif
44

    
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/* Number of Downstream Ports on the root hub.  */
46

    
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#define OHCI_MAX_PORTS 15
48

    
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static int64_t usb_frame_time;
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static int64_t usb_bit_time;
51

    
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typedef struct OHCIPort {
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    USBPort port;
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    uint32_t ctrl;
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} OHCIPort;
56

    
57
enum ohci_type {
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    OHCI_TYPE_PCI,
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    OHCI_TYPE_PXA
60
};
61

    
62
typedef struct {
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    qemu_irq irq;
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    enum ohci_type type;
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    target_phys_addr_t mem_base;
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    int mem;
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    int num_ports;
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    const char *name;
69

    
70
    QEMUTimer *eof_timer;
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    int64_t sof_time;
72

    
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    /* OHCI state */
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    /* Control partition */
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    uint32_t ctl, status;
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    uint32_t intr_status;
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    uint32_t intr;
78

    
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    /* memory pointer partition */
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    uint32_t hcca;
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    uint32_t ctrl_head, ctrl_cur;
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    uint32_t bulk_head, bulk_cur;
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    uint32_t per_cur;
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    uint32_t done;
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    int done_count;
86

    
87
    /* Frame counter partition */
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    uint32_t fsmps:15;
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    uint32_t fit:1;
90
    uint32_t fi:14;
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    uint32_t frt:1;
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    uint16_t frame_number;
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    uint16_t padding;
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    uint32_t pstart;
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    uint32_t lst;
96

    
97
    /* Root Hub partition */
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    uint32_t rhdesc_a, rhdesc_b;
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    uint32_t rhstatus;
100
    OHCIPort rhport[OHCI_MAX_PORTS];
101

    
102
    /* PXA27x Non-OHCI events */
103
    uint32_t hstatus;
104
    uint32_t hmask;
105
    uint32_t hreset;
106
    uint32_t htest;
107

    
108
    /* Active packets.  */
109
    uint32_t old_ctl;
110
    USBPacket usb_packet;
111
    uint8_t usb_buf[8192];
112
    uint32_t async_td;
113
    int async_complete;
114

    
115
} OHCIState;
116

    
117
/* Host Controller Communications Area */
118
struct ohci_hcca {
119
    uint32_t intr[32];
120
    uint16_t frame, pad;
121
    uint32_t done;
122
};
123

    
124
static void ohci_bus_stop(OHCIState *ohci);
125

    
126
/* Bitfields for the first word of an Endpoint Desciptor.  */
127
#define OHCI_ED_FA_SHIFT  0
128
#define OHCI_ED_FA_MASK   (0x7f<<OHCI_ED_FA_SHIFT)
129
#define OHCI_ED_EN_SHIFT  7
130
#define OHCI_ED_EN_MASK   (0xf<<OHCI_ED_EN_SHIFT)
131
#define OHCI_ED_D_SHIFT   11
132
#define OHCI_ED_D_MASK    (3<<OHCI_ED_D_SHIFT)
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#define OHCI_ED_S         (1<<13)
134
#define OHCI_ED_K         (1<<14)
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#define OHCI_ED_F         (1<<15)
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#define OHCI_ED_MPS_SHIFT 16
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#define OHCI_ED_MPS_MASK  (0x7ff<<OHCI_ED_MPS_SHIFT)
138

    
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/* Flags in the head field of an Endpoint Desciptor.  */
140
#define OHCI_ED_H         1
141
#define OHCI_ED_C         2
142

    
143
/* Bitfields for the first word of a Transfer Desciptor.  */
144
#define OHCI_TD_R         (1<<18)
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#define OHCI_TD_DP_SHIFT  19
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#define OHCI_TD_DP_MASK   (3<<OHCI_TD_DP_SHIFT)
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#define OHCI_TD_DI_SHIFT  21
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#define OHCI_TD_DI_MASK   (7<<OHCI_TD_DI_SHIFT)
149
#define OHCI_TD_T0        (1<<24)
150
#define OHCI_TD_T1        (1<<24)
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#define OHCI_TD_EC_SHIFT  26
152
#define OHCI_TD_EC_MASK   (3<<OHCI_TD_EC_SHIFT)
153
#define OHCI_TD_CC_SHIFT  28
154
#define OHCI_TD_CC_MASK   (0xf<<OHCI_TD_CC_SHIFT)
155

    
156
/* Bitfields for the first word of an Isochronous Transfer Desciptor.  */
157
/* CC & DI - same as in the General Transfer Desciptor */
158
#define OHCI_TD_SF_SHIFT  0
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#define OHCI_TD_SF_MASK   (0xffff<<OHCI_TD_SF_SHIFT)
160
#define OHCI_TD_FC_SHIFT  24
161
#define OHCI_TD_FC_MASK   (7<<OHCI_TD_FC_SHIFT)
162

    
163
/* Isochronous Transfer Desciptor - Offset / PacketStatusWord */
164
#define OHCI_TD_PSW_CC_SHIFT 12
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#define OHCI_TD_PSW_CC_MASK  (0xf<<OHCI_TD_PSW_CC_SHIFT)
166
#define OHCI_TD_PSW_SIZE_SHIFT 0
167
#define OHCI_TD_PSW_SIZE_MASK  (0xfff<<OHCI_TD_PSW_SIZE_SHIFT)
168

    
169
#define OHCI_PAGE_MASK    0xfffff000
170
#define OHCI_OFFSET_MASK  0xfff
171

    
172
#define OHCI_DPTR_MASK    0xfffffff0
173

    
174
#define OHCI_BM(val, field) \
175
  (((val) & OHCI_##field##_MASK) >> OHCI_##field##_SHIFT)
176

    
177
#define OHCI_SET_BM(val, field, newval) do { \
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    val &= ~OHCI_##field##_MASK; \
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    val |= ((newval) << OHCI_##field##_SHIFT) & OHCI_##field##_MASK; \
180
    } while(0)
181

    
182
/* endpoint descriptor */
183
struct ohci_ed {
184
    uint32_t flags;
185
    uint32_t tail;
186
    uint32_t head;
187
    uint32_t next;
188
};
189

    
190
/* General transfer descriptor */
191
struct ohci_td {
192
    uint32_t flags;
193
    uint32_t cbp;
194
    uint32_t next;
195
    uint32_t be;
196
};
197

    
198
/* Isochronous transfer descriptor */
199
struct ohci_iso_td {
200
    uint32_t flags;
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    uint32_t bp;
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    uint32_t next;
203
    uint32_t be;
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    uint16_t offset[8];
205
};
206

    
207
#define USB_HZ                      12000000
208

    
209
/* OHCI Local stuff */
210
#define OHCI_CTL_CBSR         ((1<<0)|(1<<1))
211
#define OHCI_CTL_PLE          (1<<2)
212
#define OHCI_CTL_IE           (1<<3)
213
#define OHCI_CTL_CLE          (1<<4)
214
#define OHCI_CTL_BLE          (1<<5)
215
#define OHCI_CTL_HCFS         ((1<<6)|(1<<7))
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#define  OHCI_USB_RESET       0x00
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#define  OHCI_USB_RESUME      0x40
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#define  OHCI_USB_OPERATIONAL 0x80
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#define  OHCI_USB_SUSPEND     0xc0
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#define OHCI_CTL_IR           (1<<8)
221
#define OHCI_CTL_RWC          (1<<9)
222
#define OHCI_CTL_RWE          (1<<10)
223

    
224
#define OHCI_STATUS_HCR       (1<<0)
225
#define OHCI_STATUS_CLF       (1<<1)
226
#define OHCI_STATUS_BLF       (1<<2)
227
#define OHCI_STATUS_OCR       (1<<3)
228
#define OHCI_STATUS_SOC       ((1<<6)|(1<<7))
229

    
230
#define OHCI_INTR_SO          (1<<0) /* Scheduling overrun */
231
#define OHCI_INTR_WD          (1<<1) /* HcDoneHead writeback */
232
#define OHCI_INTR_SF          (1<<2) /* Start of frame */
233
#define OHCI_INTR_RD          (1<<3) /* Resume detect */
234
#define OHCI_INTR_UE          (1<<4) /* Unrecoverable error */
235
#define OHCI_INTR_FNO         (1<<5) /* Frame number overflow */
236
#define OHCI_INTR_RHSC        (1<<6) /* Root hub status change */
237
#define OHCI_INTR_OC          (1<<30) /* Ownership change */
238
#define OHCI_INTR_MIE         (1<<31) /* Master Interrupt Enable */
239

    
240
#define OHCI_HCCA_SIZE        0x100
241
#define OHCI_HCCA_MASK        0xffffff00
242

    
243
#define OHCI_EDPTR_MASK       0xfffffff0
244

    
245
#define OHCI_FMI_FI           0x00003fff
246
#define OHCI_FMI_FSMPS        0xffff0000
247
#define OHCI_FMI_FIT          0x80000000
248

    
249
#define OHCI_FR_RT            (1<<31)
250

    
251
#define OHCI_LS_THRESH        0x628
252

    
253
#define OHCI_RHA_RW_MASK      0x00000000 /* Mask of supported features.  */
254
#define OHCI_RHA_PSM          (1<<8)
255
#define OHCI_RHA_NPS          (1<<9)
256
#define OHCI_RHA_DT           (1<<10)
257
#define OHCI_RHA_OCPM         (1<<11)
258
#define OHCI_RHA_NOCP         (1<<12)
259
#define OHCI_RHA_POTPGT_MASK  0xff000000
260

    
261
#define OHCI_RHS_LPS          (1<<0)
262
#define OHCI_RHS_OCI          (1<<1)
263
#define OHCI_RHS_DRWE         (1<<15)
264
#define OHCI_RHS_LPSC         (1<<16)
265
#define OHCI_RHS_OCIC         (1<<17)
266
#define OHCI_RHS_CRWE         (1<<31)
267

    
268
#define OHCI_PORT_CCS         (1<<0)
269
#define OHCI_PORT_PES         (1<<1)
270
#define OHCI_PORT_PSS         (1<<2)
271
#define OHCI_PORT_POCI        (1<<3)
272
#define OHCI_PORT_PRS         (1<<4)
273
#define OHCI_PORT_PPS         (1<<8)
274
#define OHCI_PORT_LSDA        (1<<9)
275
#define OHCI_PORT_CSC         (1<<16)
276
#define OHCI_PORT_PESC        (1<<17)
277
#define OHCI_PORT_PSSC        (1<<18)
278
#define OHCI_PORT_OCIC        (1<<19)
279
#define OHCI_PORT_PRSC        (1<<20)
280
#define OHCI_PORT_WTC         (OHCI_PORT_CSC|OHCI_PORT_PESC|OHCI_PORT_PSSC \
281
                               |OHCI_PORT_OCIC|OHCI_PORT_PRSC)
282

    
283
#define OHCI_TD_DIR_SETUP     0x0
284
#define OHCI_TD_DIR_OUT       0x1
285
#define OHCI_TD_DIR_IN        0x2
286
#define OHCI_TD_DIR_RESERVED  0x3
287

    
288
#define OHCI_CC_NOERROR             0x0
289
#define OHCI_CC_CRC                 0x1
290
#define OHCI_CC_BITSTUFFING         0x2
291
#define OHCI_CC_DATATOGGLEMISMATCH  0x3
292
#define OHCI_CC_STALL               0x4
293
#define OHCI_CC_DEVICENOTRESPONDING 0x5
294
#define OHCI_CC_PIDCHECKFAILURE     0x6
295
#define OHCI_CC_UNDEXPETEDPID       0x7
296
#define OHCI_CC_DATAOVERRUN         0x8
297
#define OHCI_CC_DATAUNDERRUN        0x9
298
#define OHCI_CC_BUFFEROVERRUN       0xc
299
#define OHCI_CC_BUFFERUNDERRUN      0xd
300

    
301
#define OHCI_HRESET_FSBIR       (1 << 0)
302

    
303
/* Update IRQ levels */
304
static inline void ohci_intr_update(OHCIState *ohci)
305
{
306
    int level = 0;
307

    
308
    if ((ohci->intr & OHCI_INTR_MIE) &&
309
        (ohci->intr_status & ohci->intr))
310
        level = 1;
311

    
312
    qemu_set_irq(ohci->irq, level);
313
}
314

    
315
/* Set an interrupt */
316
static inline void ohci_set_interrupt(OHCIState *ohci, uint32_t intr)
317
{
318
    ohci->intr_status |= intr;
319
    ohci_intr_update(ohci);
320
}
321

    
322
/* Attach or detach a device on a root hub port.  */
323
static void ohci_attach(USBPort *port1, USBDevice *dev)
324
{
325
    OHCIState *s = port1->opaque;
326
    OHCIPort *port = &s->rhport[port1->index];
327
    uint32_t old_state = port->ctrl;
328

    
329
    if (dev) {
330
        if (port->port.dev) {
331
            usb_attach(port1, NULL);
332
        }
333
        /* set connect status */
334
        port->ctrl |= OHCI_PORT_CCS | OHCI_PORT_CSC;
335

    
336
        /* update speed */
337
        if (dev->speed == USB_SPEED_LOW)
338
            port->ctrl |= OHCI_PORT_LSDA;
339
        else
340
            port->ctrl &= ~OHCI_PORT_LSDA;
341
        port->port.dev = dev;
342

    
343
        /* notify of remote-wakeup */
344
        if ((s->ctl & OHCI_CTL_HCFS) == OHCI_USB_SUSPEND)
345
            ohci_set_interrupt(s, OHCI_INTR_RD);
346

    
347
        /* send the attach message */
348
        usb_send_msg(dev, USB_MSG_ATTACH);
349
        dprintf("usb-ohci: Attached port %d\n", port1->index);
350
    } else {
351
        /* set connect status */
352
        if (port->ctrl & OHCI_PORT_CCS) {
353
            port->ctrl &= ~OHCI_PORT_CCS;
354
            port->ctrl |= OHCI_PORT_CSC;
355
        }
356
        /* disable port */
357
        if (port->ctrl & OHCI_PORT_PES) {
358
            port->ctrl &= ~OHCI_PORT_PES;
359
            port->ctrl |= OHCI_PORT_PESC;
360
        }
361
        dev = port->port.dev;
362
        if (dev) {
363
            /* send the detach message */
364
            usb_send_msg(dev, USB_MSG_DETACH);
365
        }
366
        port->port.dev = NULL;
367
        dprintf("usb-ohci: Detached port %d\n", port1->index);
368
    }
369

    
370
    if (old_state != port->ctrl)
371
        ohci_set_interrupt(s, OHCI_INTR_RHSC);
372
}
373

    
374
/* Reset the controller */
375
static void ohci_reset(void *opaque)
376
{
377
    OHCIState *ohci = opaque;
378
    OHCIPort *port;
379
    int i;
380

    
381
    ohci_bus_stop(ohci);
382
    ohci->ctl = 0;
383
    ohci->old_ctl = 0;
384
    ohci->status = 0;
385
    ohci->intr_status = 0;
386
    ohci->intr = OHCI_INTR_MIE;
387

    
388
    ohci->hcca = 0;
389
    ohci->ctrl_head = ohci->ctrl_cur = 0;
390
    ohci->bulk_head = ohci->bulk_cur = 0;
391
    ohci->per_cur = 0;
392
    ohci->done = 0;
393
    ohci->done_count = 7;
394

    
395
    /* FSMPS is marked TBD in OCHI 1.0, what gives ffs?
396
     * I took the value linux sets ...
397
     */
398
    ohci->fsmps = 0x2778;
399
    ohci->fi = 0x2edf;
400
    ohci->fit = 0;
401
    ohci->frt = 0;
402
    ohci->frame_number = 0;
403
    ohci->pstart = 0;
404
    ohci->lst = OHCI_LS_THRESH;
405

    
406
    ohci->rhdesc_a = OHCI_RHA_NPS | ohci->num_ports;
407
    ohci->rhdesc_b = 0x0; /* Impl. specific */
408
    ohci->rhstatus = 0;
409

    
410
    for (i = 0; i < ohci->num_ports; i++)
411
      {
412
        port = &ohci->rhport[i];
413
        port->ctrl = 0;
414
        if (port->port.dev)
415
            ohci_attach(&port->port, port->port.dev);
416
      }
417
    if (ohci->async_td) {
418
        usb_cancel_packet(&ohci->usb_packet);
419
        ohci->async_td = 0;
420
    }
421
    dprintf("usb-ohci: Reset %s\n", ohci->name);
422
}
423

    
424
/* Get an array of dwords from main memory */
425
static inline int get_dwords(uint32_t addr, uint32_t *buf, int num)
426
{
427
    int i;
428

    
429
    for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
430
        cpu_physical_memory_rw(addr, (uint8_t *)buf, sizeof(*buf), 0);
431
        *buf = le32_to_cpu(*buf);
432
    }
433

    
434
    return 1;
435
}
436

    
437
/* Put an array of dwords in to main memory */
438
static inline int put_dwords(uint32_t addr, uint32_t *buf, int num)
439
{
440
    int i;
441

    
442
    for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
443
        uint32_t tmp = cpu_to_le32(*buf);
444
        cpu_physical_memory_rw(addr, (uint8_t *)&tmp, sizeof(tmp), 1);
445
    }
446

    
447
    return 1;
448
}
449

    
450
/* Get an array of words from main memory */
451
static inline int get_words(uint32_t addr, uint16_t *buf, int num)
452
{
453
    int i;
454

    
455
    for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
456
        cpu_physical_memory_rw(addr, (uint8_t *)buf, sizeof(*buf), 0);
457
        *buf = le16_to_cpu(*buf);
458
    }
459

    
460
    return 1;
461
}
462

    
463
/* Put an array of words in to main memory */
464
static inline int put_words(uint32_t addr, uint16_t *buf, int num)
465
{
466
    int i;
467

    
468
    for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
469
        uint16_t tmp = cpu_to_le16(*buf);
470
        cpu_physical_memory_rw(addr, (uint8_t *)&tmp, sizeof(tmp), 1);
471
    }
472

    
473
    return 1;
474
}
475

    
476
static inline int ohci_read_ed(uint32_t addr, struct ohci_ed *ed)
477
{
478
    return get_dwords(addr, (uint32_t *)ed, sizeof(*ed) >> 2);
479
}
480

    
481
static inline int ohci_read_td(uint32_t addr, struct ohci_td *td)
482
{
483
    return get_dwords(addr, (uint32_t *)td, sizeof(*td) >> 2);
484
}
485

    
486
static inline int ohci_read_iso_td(uint32_t addr, struct ohci_iso_td *td)
487
{
488
    return (get_dwords(addr, (uint32_t *)td, 4) &&
489
            get_words(addr + 16, td->offset, 8));
490
}
491

    
492
static inline int ohci_put_ed(uint32_t addr, struct ohci_ed *ed)
493
{
494
    return put_dwords(addr, (uint32_t *)ed, sizeof(*ed) >> 2);
495
}
496

    
497
static inline int ohci_put_td(uint32_t addr, struct ohci_td *td)
498
{
499
    return put_dwords(addr, (uint32_t *)td, sizeof(*td) >> 2);
500
}
501

    
502
static inline int ohci_put_iso_td(uint32_t addr, struct ohci_iso_td *td)
503
{
504
    return (put_dwords(addr, (uint32_t *)td, 4) &&
505
            put_words(addr + 16, td->offset, 8));
506
}
507

    
508
/* Read/Write the contents of a TD from/to main memory.  */
509
static void ohci_copy_td(struct ohci_td *td, uint8_t *buf, int len, int write)
510
{
511
    uint32_t ptr;
512
    uint32_t n;
513

    
514
    ptr = td->cbp;
515
    n = 0x1000 - (ptr & 0xfff);
516
    if (n > len)
517
        n = len;
518
    cpu_physical_memory_rw(ptr, buf, n, write);
519
    if (n == len)
520
        return;
521
    ptr = td->be & ~0xfffu;
522
    buf += n;
523
    cpu_physical_memory_rw(ptr, buf, len - n, write);
524
}
525

    
526
/* Read/Write the contents of an ISO TD from/to main memory.  */
527
static void ohci_copy_iso_td(uint32_t start_addr, uint32_t end_addr,
528
                             uint8_t *buf, int len, int write)
529
{
530
    uint32_t ptr;
531
    uint32_t n;
532

    
533
    ptr = start_addr;
534
    n = 0x1000 - (ptr & 0xfff);
535
    if (n > len)
536
        n = len;
537
    cpu_physical_memory_rw(ptr, buf, n, write);
538
    if (n == len)
539
        return;
540
    ptr = end_addr & ~0xfffu;
541
    buf += n;
542
    cpu_physical_memory_rw(ptr, buf, len - n, write);
543
}
544

    
545
static void ohci_process_lists(OHCIState *ohci, int completion);
546

    
547
static void ohci_async_complete_packet(USBPacket *packet, void *opaque)
548
{
549
    OHCIState *ohci = opaque;
550
#ifdef DEBUG_PACKET
551
    dprintf("Async packet complete\n");
552
#endif
553
    ohci->async_complete = 1;
554
    ohci_process_lists(ohci, 1);
555
}
556

    
557
#define USUB(a, b) ((int16_t)((uint16_t)(a) - (uint16_t)(b)))
558

    
559
static int ohci_service_iso_td(OHCIState *ohci, struct ohci_ed *ed,
560
                               int completion)
561
{
562
    int dir;
563
    size_t len = 0;
564
    char *str = NULL;
565
    int pid;
566
    int ret;
567
    int i;
568
    USBDevice *dev;
569
    struct ohci_iso_td iso_td;
570
    uint32_t addr;
571
    uint16_t starting_frame;
572
    int16_t relative_frame_number;
573
    int frame_count;
574
    uint32_t start_offset, next_offset, end_offset = 0;
575
    uint32_t start_addr, end_addr;
576

    
577
    addr = ed->head & OHCI_DPTR_MASK;
578

    
579
    if (!ohci_read_iso_td(addr, &iso_td)) {
580
        printf("usb-ohci: ISO_TD read error at %x\n", addr);
581
        return 0;
582
    }
583

    
584
    starting_frame = OHCI_BM(iso_td.flags, TD_SF);
585
    frame_count = OHCI_BM(iso_td.flags, TD_FC);
586
    relative_frame_number = USUB(ohci->frame_number, starting_frame); 
587

    
588
#ifdef DEBUG_ISOCH
589
    printf("--- ISO_TD ED head 0x%.8x tailp 0x%.8x\n"
590
           "0x%.8x 0x%.8x 0x%.8x 0x%.8x\n"
591
           "0x%.8x 0x%.8x 0x%.8x 0x%.8x\n"
592
           "0x%.8x 0x%.8x 0x%.8x 0x%.8x\n"
593
           "frame_number 0x%.8x starting_frame 0x%.8x\n"
594
           "frame_count  0x%.8x relative %d\n"
595
           "di 0x%.8x cc 0x%.8x\n",
596
           ed->head & OHCI_DPTR_MASK, ed->tail & OHCI_DPTR_MASK,
597
           iso_td.flags, iso_td.bp, iso_td.next, iso_td.be,
598
           iso_td.offset[0], iso_td.offset[1], iso_td.offset[2], iso_td.offset[3],
599
           iso_td.offset[4], iso_td.offset[5], iso_td.offset[6], iso_td.offset[7],
600
           ohci->frame_number, starting_frame, 
601
           frame_count, relative_frame_number,         
602
           OHCI_BM(iso_td.flags, TD_DI), OHCI_BM(iso_td.flags, TD_CC));
603
#endif
604

    
605
    if (relative_frame_number < 0) {
606
        dprintf("usb-ohci: ISO_TD R=%d < 0\n", relative_frame_number);
607
        return 1;
608
    } else if (relative_frame_number > frame_count) {
609
        /* ISO TD expired - retire the TD to the Done Queue and continue with
610
           the next ISO TD of the same ED */
611
        dprintf("usb-ohci: ISO_TD R=%d > FC=%d\n", relative_frame_number, 
612
               frame_count);
613
        OHCI_SET_BM(iso_td.flags, TD_CC, OHCI_CC_DATAOVERRUN);
614
        ed->head &= ~OHCI_DPTR_MASK;
615
        ed->head |= (iso_td.next & OHCI_DPTR_MASK);
616
        iso_td.next = ohci->done;
617
        ohci->done = addr;
618
        i = OHCI_BM(iso_td.flags, TD_DI);
619
        if (i < ohci->done_count)
620
            ohci->done_count = i;
621
        ohci_put_iso_td(addr, &iso_td);        
622
        return 0;
623
    }
624

    
625
    dir = OHCI_BM(ed->flags, ED_D);
626
    switch (dir) {
627
    case OHCI_TD_DIR_IN:
628
        str = "in";
629
        pid = USB_TOKEN_IN;
630
        break;
631
    case OHCI_TD_DIR_OUT:
632
        str = "out";
633
        pid = USB_TOKEN_OUT;
634
        break;
635
    case OHCI_TD_DIR_SETUP:
636
        str = "setup";
637
        pid = USB_TOKEN_SETUP;
638
        break;
639
    default:
640
        printf("usb-ohci: Bad direction %d\n", dir);
641
        return 1;
642
    }
643

    
644
    if (!iso_td.bp || !iso_td.be) {
645
        printf("usb-ohci: ISO_TD bp 0x%.8x be 0x%.8x\n", iso_td.bp, iso_td.be);
646
        return 1;
647
    }
648

    
649
    start_offset = iso_td.offset[relative_frame_number];
650
    next_offset = iso_td.offset[relative_frame_number + 1];
651

    
652
    if (!(OHCI_BM(start_offset, TD_PSW_CC) & 0xe) || 
653
        ((relative_frame_number < frame_count) && 
654
         !(OHCI_BM(next_offset, TD_PSW_CC) & 0xe))) {
655
        printf("usb-ohci: ISO_TD cc != not accessed 0x%.8x 0x%.8x\n",
656
               start_offset, next_offset);
657
        return 1;
658
    }
659

    
660
    if ((relative_frame_number < frame_count) && (start_offset > next_offset)) {
661
        printf("usb-ohci: ISO_TD start_offset=0x%.8x > next_offset=0x%.8x\n",
662
                start_offset, next_offset);
663
        return 1;
664
    }
665

    
666
    if ((start_offset & 0x1000) == 0) {
667
        start_addr = (iso_td.bp & OHCI_PAGE_MASK) |
668
            (start_offset & OHCI_OFFSET_MASK);
669
    } else {
670
        start_addr = (iso_td.be & OHCI_PAGE_MASK) |
671
            (start_offset & OHCI_OFFSET_MASK);
672
    }
673

    
674
    if (relative_frame_number < frame_count) {
675
        end_offset = next_offset - 1;
676
        if ((end_offset & 0x1000) == 0) {
677
            end_addr = (iso_td.bp & OHCI_PAGE_MASK) |
678
                (end_offset & OHCI_OFFSET_MASK);
679
        } else {
680
            end_addr = (iso_td.be & OHCI_PAGE_MASK) |
681
                (end_offset & OHCI_OFFSET_MASK);
682
        }
683
    } else {
684
        /* Last packet in the ISO TD */
685
        end_addr = iso_td.be;
686
    }
687

    
688
    if ((start_addr & OHCI_PAGE_MASK) != (end_addr & OHCI_PAGE_MASK)) {
689
        len = (end_addr & OHCI_OFFSET_MASK) + 0x1001
690
            - (start_addr & OHCI_OFFSET_MASK);
691
    } else {
692
        len = end_addr - start_addr + 1;
693
    }
694

    
695
    if (len && dir != OHCI_TD_DIR_IN) {
696
        ohci_copy_iso_td(start_addr, end_addr, ohci->usb_buf, len, 0);
697
    }
698

    
699
    if (completion) {
700
        ret = ohci->usb_packet.len;
701
    } else {
702
        ret = USB_RET_NODEV;
703
        for (i = 0; i < ohci->num_ports; i++) {
704
            dev = ohci->rhport[i].port.dev;
705
            if ((ohci->rhport[i].ctrl & OHCI_PORT_PES) == 0)
706
                continue;
707
            ohci->usb_packet.pid = pid;
708
            ohci->usb_packet.devaddr = OHCI_BM(ed->flags, ED_FA);
709
            ohci->usb_packet.devep = OHCI_BM(ed->flags, ED_EN);
710
            ohci->usb_packet.data = ohci->usb_buf;
711
            ohci->usb_packet.len = len;
712
            ohci->usb_packet.complete_cb = ohci_async_complete_packet;
713
            ohci->usb_packet.complete_opaque = ohci;
714
            ret = dev->handle_packet(dev, &ohci->usb_packet);
715
            if (ret != USB_RET_NODEV)
716
                break;
717
        }
718
    
719
        if (ret == USB_RET_ASYNC) {
720
            return 1;
721
        }
722
    }
723

    
724
#ifdef DEBUG_ISOCH
725
    printf("so 0x%.8x eo 0x%.8x\nsa 0x%.8x ea 0x%.8x\ndir %s len %zu ret %d\n",
726
           start_offset, end_offset, start_addr, end_addr, str, len, ret);
727
#endif
728

    
729
    /* Writeback */
730
    if (dir == OHCI_TD_DIR_IN && ret >= 0 && ret <= len) {
731
        /* IN transfer succeeded */
732
        ohci_copy_iso_td(start_addr, end_addr, ohci->usb_buf, ret, 1);
733
        OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
734
                    OHCI_CC_NOERROR);
735
        OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, ret);
736
    } else if (dir == OHCI_TD_DIR_OUT && ret == len) {
737
        /* OUT transfer succeeded */
738
        OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
739
                    OHCI_CC_NOERROR);
740
        OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, 0);
741
    } else {
742
        if (ret > len) {
743
            printf("usb-ohci: DataOverrun %d > %zu\n", ret, len);
744
            OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
745
                        OHCI_CC_DATAOVERRUN);
746
            OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE,
747
                        len);
748
        } else if (ret >= 0) {
749
            printf("usb-ohci: DataUnderrun %d\n", ret);
750
            OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
751
                        OHCI_CC_DATAUNDERRUN);
752
        } else {
753
            switch (ret) {
754
            case USB_RET_NODEV:
755
                OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
756
                            OHCI_CC_DEVICENOTRESPONDING);
757
                OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE,
758
                            0);
759
                break;
760
            case USB_RET_NAK:
761
            case USB_RET_STALL:
762
                printf("usb-ohci: got NAK/STALL %d\n", ret);
763
                OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
764
                            OHCI_CC_STALL);
765
                OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE,
766
                            0);
767
                break;
768
            default:
769
                printf("usb-ohci: Bad device response %d\n", ret);
770
                OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
771
                            OHCI_CC_UNDEXPETEDPID);
772
                break;
773
            }
774
        }
775
    }
776

    
777
    if (relative_frame_number == frame_count) {
778
        /* Last data packet of ISO TD - retire the TD to the Done Queue */
779
        OHCI_SET_BM(iso_td.flags, TD_CC, OHCI_CC_NOERROR);
780
        ed->head &= ~OHCI_DPTR_MASK;
781
        ed->head |= (iso_td.next & OHCI_DPTR_MASK);
782
        iso_td.next = ohci->done;
783
        ohci->done = addr;
784
        i = OHCI_BM(iso_td.flags, TD_DI);
785
        if (i < ohci->done_count)
786
            ohci->done_count = i;
787
    }
788
    ohci_put_iso_td(addr, &iso_td);
789
    return 1;
790
}
791

    
792
/* Service a transport descriptor.
793
   Returns nonzero to terminate processing of this endpoint.  */
794

    
795
static int ohci_service_td(OHCIState *ohci, struct ohci_ed *ed)
796
{
797
    int dir;
798
    size_t len = 0;
799
    char *str = NULL;
800
    int pid;
801
    int ret;
802
    int i;
803
    USBDevice *dev;
804
    struct ohci_td td;
805
    uint32_t addr;
806
    int flag_r;
807
    int completion;
808

    
809
    addr = ed->head & OHCI_DPTR_MASK;
810
    /* See if this TD has already been submitted to the device.  */
811
    completion = (addr == ohci->async_td);
812
    if (completion && !ohci->async_complete) {
813
#ifdef DEBUG_PACKET
814
        dprintf("Skipping async TD\n");
815
#endif
816
        return 1;
817
    }
818
    if (!ohci_read_td(addr, &td)) {
819
        fprintf(stderr, "usb-ohci: TD read error at %x\n", addr);
820
        return 0;
821
    }
822

    
823
    dir = OHCI_BM(ed->flags, ED_D);
824
    switch (dir) {
825
    case OHCI_TD_DIR_OUT:
826
    case OHCI_TD_DIR_IN:
827
        /* Same value.  */
828
        break;
829
    default:
830
        dir = OHCI_BM(td.flags, TD_DP);
831
        break;
832
    }
833

    
834
    switch (dir) {
835
    case OHCI_TD_DIR_IN:
836
        str = "in";
837
        pid = USB_TOKEN_IN;
838
        break;
839
    case OHCI_TD_DIR_OUT:
840
        str = "out";
841
        pid = USB_TOKEN_OUT;
842
        break;
843
    case OHCI_TD_DIR_SETUP:
844
        str = "setup";
845
        pid = USB_TOKEN_SETUP;
846
        break;
847
    default:
848
        fprintf(stderr, "usb-ohci: Bad direction\n");
849
        return 1;
850
    }
851
    if (td.cbp && td.be) {
852
        if ((td.cbp & 0xfffff000) != (td.be & 0xfffff000)) {
853
            len = (td.be & 0xfff) + 0x1001 - (td.cbp & 0xfff);
854
        } else {
855
            len = (td.be - td.cbp) + 1;
856
        }
857

    
858
        if (len && dir != OHCI_TD_DIR_IN && !completion) {
859
            ohci_copy_td(&td, ohci->usb_buf, len, 0);
860
        }
861
    }
862

    
863
    flag_r = (td.flags & OHCI_TD_R) != 0;
864
#ifdef DEBUG_PACKET
865
    dprintf(" TD @ 0x%.8x %u bytes %s r=%d cbp=0x%.8x be=0x%.8x\n",
866
            addr, len, str, flag_r, td.cbp, td.be);
867

    
868
    if (len >= 0 && dir != OHCI_TD_DIR_IN) {
869
        dprintf("  data:");
870
        for (i = 0; i < len; i++)
871
            printf(" %.2x", ohci->usb_buf[i]);
872
        dprintf("\n");
873
    }
874
#endif
875
    if (completion) {
876
        ret = ohci->usb_packet.len;
877
        ohci->async_td = 0;
878
        ohci->async_complete = 0;
879
    } else {
880
        ret = USB_RET_NODEV;
881
        for (i = 0; i < ohci->num_ports; i++) {
882
            dev = ohci->rhport[i].port.dev;
883
            if ((ohci->rhport[i].ctrl & OHCI_PORT_PES) == 0)
884
                continue;
885

    
886
            if (ohci->async_td) {
887
                /* ??? The hardware should allow one active packet per
888
                   endpoint.  We only allow one active packet per controller.
889
                   This should be sufficient as long as devices respond in a
890
                   timely manner.
891
                 */
892
#ifdef DEBUG_PACKET
893
                dprintf("Too many pending packets\n");
894
#endif
895
                return 1;
896
            }
897
            ohci->usb_packet.pid = pid;
898
            ohci->usb_packet.devaddr = OHCI_BM(ed->flags, ED_FA);
899
            ohci->usb_packet.devep = OHCI_BM(ed->flags, ED_EN);
900
            ohci->usb_packet.data = ohci->usb_buf;
901
            ohci->usb_packet.len = len;
902
            ohci->usb_packet.complete_cb = ohci_async_complete_packet;
903
            ohci->usb_packet.complete_opaque = ohci;
904
            ret = dev->handle_packet(dev, &ohci->usb_packet);
905
            if (ret != USB_RET_NODEV)
906
                break;
907
        }
908
#ifdef DEBUG_PACKET
909
        dprintf("ret=%d\n", ret);
910
#endif
911
        if (ret == USB_RET_ASYNC) {
912
            ohci->async_td = addr;
913
            return 1;
914
        }
915
    }
916
    if (ret >= 0) {
917
        if (dir == OHCI_TD_DIR_IN) {
918
            ohci_copy_td(&td, ohci->usb_buf, ret, 1);
919
#ifdef DEBUG_PACKET
920
            dprintf("  data:");
921
            for (i = 0; i < ret; i++)
922
                printf(" %.2x", ohci->usb_buf[i]);
923
            dprintf("\n");
924
#endif
925
        } else {
926
            ret = len;
927
        }
928
    }
929

    
930
    /* Writeback */
931
    if (ret == len || (dir == OHCI_TD_DIR_IN && ret >= 0 && flag_r)) {
932
        /* Transmission succeeded.  */
933
        if (ret == len) {
934
            td.cbp = 0;
935
        } else {
936
            td.cbp += ret;
937
            if ((td.cbp & 0xfff) + ret > 0xfff) {
938
                td.cbp &= 0xfff;
939
                td.cbp |= td.be & ~0xfff;
940
            }
941
        }
942
        td.flags |= OHCI_TD_T1;
943
        td.flags ^= OHCI_TD_T0;
944
        OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_NOERROR);
945
        OHCI_SET_BM(td.flags, TD_EC, 0);
946

    
947
        ed->head &= ~OHCI_ED_C;
948
        if (td.flags & OHCI_TD_T0)
949
            ed->head |= OHCI_ED_C;
950
    } else {
951
        if (ret >= 0) {
952
            dprintf("usb-ohci: Underrun\n");
953
            OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAUNDERRUN);
954
        } else {
955
            switch (ret) {
956
            case USB_RET_NODEV:
957
                OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DEVICENOTRESPONDING);
958
            case USB_RET_NAK:
959
                dprintf("usb-ohci: got NAK\n");
960
                return 1;
961
            case USB_RET_STALL:
962
                dprintf("usb-ohci: got STALL\n");
963
                OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_STALL);
964
                break;
965
            case USB_RET_BABBLE:
966
                dprintf("usb-ohci: got BABBLE\n");
967
                OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAOVERRUN);
968
                break;
969
            default:
970
                fprintf(stderr, "usb-ohci: Bad device response %d\n", ret);
971
                OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_UNDEXPETEDPID);
972
                OHCI_SET_BM(td.flags, TD_EC, 3);
973
                break;
974
            }
975
        }
976
        ed->head |= OHCI_ED_H;
977
    }
978

    
979
    /* Retire this TD */
980
    ed->head &= ~OHCI_DPTR_MASK;
981
    ed->head |= td.next & OHCI_DPTR_MASK;
982
    td.next = ohci->done;
983
    ohci->done = addr;
984
    i = OHCI_BM(td.flags, TD_DI);
985
    if (i < ohci->done_count)
986
        ohci->done_count = i;
987
    ohci_put_td(addr, &td);
988
    return OHCI_BM(td.flags, TD_CC) != OHCI_CC_NOERROR;
989
}
990

    
991
/* Service an endpoint list.  Returns nonzero if active TD were found.  */
992
static int ohci_service_ed_list(OHCIState *ohci, uint32_t head, int completion)
993
{
994
    struct ohci_ed ed;
995
    uint32_t next_ed;
996
    uint32_t cur;
997
    int active;
998

    
999
    active = 0;
1000

    
1001
    if (head == 0)
1002
        return 0;
1003

    
1004
    for (cur = head; cur; cur = next_ed) {
1005
        if (!ohci_read_ed(cur, &ed)) {
1006
            fprintf(stderr, "usb-ohci: ED read error at %x\n", cur);
1007
            return 0;
1008
        }
1009

    
1010
        next_ed = ed.next & OHCI_DPTR_MASK;
1011

    
1012
        if ((ed.head & OHCI_ED_H) || (ed.flags & OHCI_ED_K)) {
1013
            uint32_t addr;
1014
            /* Cancel pending packets for ED that have been paused.  */
1015
            addr = ed.head & OHCI_DPTR_MASK;
1016
            if (ohci->async_td && addr == ohci->async_td) {
1017
                usb_cancel_packet(&ohci->usb_packet);
1018
                ohci->async_td = 0;
1019
            }
1020
            continue;
1021
        }
1022

    
1023
        while ((ed.head & OHCI_DPTR_MASK) != ed.tail) {
1024
#ifdef DEBUG_PACKET
1025
            dprintf("ED @ 0x%.8x fa=%u en=%u d=%u s=%u k=%u f=%u mps=%u "
1026
                    "h=%u c=%u\n  head=0x%.8x tailp=0x%.8x next=0x%.8x\n", cur,
1027
                    OHCI_BM(ed.flags, ED_FA), OHCI_BM(ed.flags, ED_EN),
1028
                    OHCI_BM(ed.flags, ED_D), (ed.flags & OHCI_ED_S)!= 0,
1029
                    (ed.flags & OHCI_ED_K) != 0, (ed.flags & OHCI_ED_F) != 0,
1030
                    OHCI_BM(ed.flags, ED_MPS), (ed.head & OHCI_ED_H) != 0,
1031
                    (ed.head & OHCI_ED_C) != 0, ed.head & OHCI_DPTR_MASK,
1032
                    ed.tail & OHCI_DPTR_MASK, ed.next & OHCI_DPTR_MASK);
1033
#endif
1034
            active = 1;
1035

    
1036
            if ((ed.flags & OHCI_ED_F) == 0) {
1037
                if (ohci_service_td(ohci, &ed))
1038
                    break;
1039
            } else {
1040
                /* Handle isochronous endpoints */
1041
                if (ohci_service_iso_td(ohci, &ed, completion))
1042
                    break;
1043
            }
1044
        }
1045

    
1046
        ohci_put_ed(cur, &ed);
1047
    }
1048

    
1049
    return active;
1050
}
1051

    
1052
/* Generate a SOF event, and set a timer for EOF */
1053
static void ohci_sof(OHCIState *ohci)
1054
{
1055
    ohci->sof_time = qemu_get_clock(vm_clock);
1056
    qemu_mod_timer(ohci->eof_timer, ohci->sof_time + usb_frame_time);
1057
    ohci_set_interrupt(ohci, OHCI_INTR_SF);
1058
}
1059

    
1060
/* Process Control and Bulk lists.  */
1061
static void ohci_process_lists(OHCIState *ohci, int completion)
1062
{
1063
    if ((ohci->ctl & OHCI_CTL_CLE) && (ohci->status & OHCI_STATUS_CLF)) {
1064
        if (ohci->ctrl_cur && ohci->ctrl_cur != ohci->ctrl_head)
1065
          dprintf("usb-ohci: head %x, cur %x\n", ohci->ctrl_head, ohci->ctrl_cur);
1066
        if (!ohci_service_ed_list(ohci, ohci->ctrl_head, completion)) {
1067
            ohci->ctrl_cur = 0;
1068
            ohci->status &= ~OHCI_STATUS_CLF;
1069
        }
1070
    }
1071

    
1072
    if ((ohci->ctl & OHCI_CTL_BLE) && (ohci->status & OHCI_STATUS_BLF)) {
1073
        if (!ohci_service_ed_list(ohci, ohci->bulk_head, completion)) {
1074
            ohci->bulk_cur = 0;
1075
            ohci->status &= ~OHCI_STATUS_BLF;
1076
        }
1077
    }
1078
}
1079

    
1080
/* Do frame processing on frame boundary */
1081
static void ohci_frame_boundary(void *opaque)
1082
{
1083
    OHCIState *ohci = opaque;
1084
    struct ohci_hcca hcca;
1085

    
1086
    cpu_physical_memory_rw(ohci->hcca, (uint8_t *)&hcca, sizeof(hcca), 0);
1087

    
1088
    /* Process all the lists at the end of the frame */
1089
    if (ohci->ctl & OHCI_CTL_PLE) {
1090
        int n;
1091

    
1092
        n = ohci->frame_number & 0x1f;
1093
        ohci_service_ed_list(ohci, le32_to_cpu(hcca.intr[n]), 0);
1094
    }
1095

    
1096
    /* Cancel all pending packets if either of the lists has been disabled.  */
1097
    if (ohci->async_td &&
1098
        ohci->old_ctl & (~ohci->ctl) & (OHCI_CTL_BLE | OHCI_CTL_CLE)) {
1099
        usb_cancel_packet(&ohci->usb_packet);
1100
        ohci->async_td = 0;
1101
    }
1102
    ohci->old_ctl = ohci->ctl;
1103
    ohci_process_lists(ohci, 0);
1104

    
1105
    /* Frame boundary, so do EOF stuf here */
1106
    ohci->frt = ohci->fit;
1107

    
1108
    /* XXX: endianness */
1109
    ohci->frame_number = (ohci->frame_number + 1) & 0xffff;
1110
    hcca.frame = cpu_to_le32(ohci->frame_number);
1111

    
1112
    if (ohci->done_count == 0 && !(ohci->intr_status & OHCI_INTR_WD)) {
1113
        if (!ohci->done)
1114
            abort();
1115
        if (ohci->intr & ohci->intr_status)
1116
            ohci->done |= 1;
1117
        hcca.done = cpu_to_le32(ohci->done);
1118
        ohci->done = 0;
1119
        ohci->done_count = 7;
1120
        ohci_set_interrupt(ohci, OHCI_INTR_WD);
1121
    }
1122

    
1123
    if (ohci->done_count != 7 && ohci->done_count != 0)
1124
        ohci->done_count--;
1125

    
1126
    /* Do SOF stuff here */
1127
    ohci_sof(ohci);
1128

    
1129
    /* Writeback HCCA */
1130
    cpu_physical_memory_rw(ohci->hcca, (uint8_t *)&hcca, sizeof(hcca), 1);
1131
}
1132

    
1133
/* Start sending SOF tokens across the USB bus, lists are processed in
1134
 * next frame
1135
 */
1136
static int ohci_bus_start(OHCIState *ohci)
1137
{
1138
    ohci->eof_timer = qemu_new_timer(vm_clock,
1139
                    ohci_frame_boundary,
1140
                    ohci);
1141

    
1142
    if (ohci->eof_timer == NULL) {
1143
        fprintf(stderr, "usb-ohci: %s: qemu_new_timer failed\n", ohci->name);
1144
        /* TODO: Signal unrecoverable error */
1145
        return 0;
1146
    }
1147

    
1148
    dprintf("usb-ohci: %s: USB Operational\n", ohci->name);
1149

    
1150
    ohci_sof(ohci);
1151

    
1152
    return 1;
1153
}
1154

    
1155
/* Stop sending SOF tokens on the bus */
1156
static void ohci_bus_stop(OHCIState *ohci)
1157
{
1158
    if (ohci->eof_timer)
1159
        qemu_del_timer(ohci->eof_timer);
1160
    ohci->eof_timer = NULL;
1161
}
1162

    
1163
/* Sets a flag in a port status register but only set it if the port is
1164
 * connected, if not set ConnectStatusChange flag. If flag is enabled
1165
 * return 1.
1166
 */
1167
static int ohci_port_set_if_connected(OHCIState *ohci, int i, uint32_t val)
1168
{
1169
    int ret = 1;
1170

    
1171
    /* writing a 0 has no effect */
1172
    if (val == 0)
1173
        return 0;
1174

    
1175
    /* If CurrentConnectStatus is cleared we set
1176
     * ConnectStatusChange
1177
     */
1178
    if (!(ohci->rhport[i].ctrl & OHCI_PORT_CCS)) {
1179
        ohci->rhport[i].ctrl |= OHCI_PORT_CSC;
1180
        if (ohci->rhstatus & OHCI_RHS_DRWE) {
1181
            /* TODO: CSC is a wakeup event */
1182
        }
1183
        return 0;
1184
    }
1185

    
1186
    if (ohci->rhport[i].ctrl & val)
1187
        ret = 0;
1188

    
1189
    /* set the bit */
1190
    ohci->rhport[i].ctrl |= val;
1191

    
1192
    return ret;
1193
}
1194

    
1195
/* Set the frame interval - frame interval toggle is manipulated by the hcd only */
1196
static void ohci_set_frame_interval(OHCIState *ohci, uint16_t val)
1197
{
1198
    val &= OHCI_FMI_FI;
1199

    
1200
    if (val != ohci->fi) {
1201
        dprintf("usb-ohci: %s: FrameInterval = 0x%x (%u)\n",
1202
            ohci->name, ohci->fi, ohci->fi);
1203
    }
1204

    
1205
    ohci->fi = val;
1206
}
1207

    
1208
static void ohci_port_power(OHCIState *ohci, int i, int p)
1209
{
1210
    if (p) {
1211
        ohci->rhport[i].ctrl |= OHCI_PORT_PPS;
1212
    } else {
1213
        ohci->rhport[i].ctrl &= ~(OHCI_PORT_PPS|
1214
                    OHCI_PORT_CCS|
1215
                    OHCI_PORT_PSS|
1216
                    OHCI_PORT_PRS);
1217
    }
1218
}
1219

    
1220
/* Set HcControlRegister */
1221
static void ohci_set_ctl(OHCIState *ohci, uint32_t val)
1222
{
1223
    uint32_t old_state;
1224
    uint32_t new_state;
1225

    
1226
    old_state = ohci->ctl & OHCI_CTL_HCFS;
1227
    ohci->ctl = val;
1228
    new_state = ohci->ctl & OHCI_CTL_HCFS;
1229

    
1230
    /* no state change */
1231
    if (old_state == new_state)
1232
        return;
1233

    
1234
    switch (new_state) {
1235
    case OHCI_USB_OPERATIONAL:
1236
        ohci_bus_start(ohci);
1237
        break;
1238
    case OHCI_USB_SUSPEND:
1239
        ohci_bus_stop(ohci);
1240
        dprintf("usb-ohci: %s: USB Suspended\n", ohci->name);
1241
        break;
1242
    case OHCI_USB_RESUME:
1243
        dprintf("usb-ohci: %s: USB Resume\n", ohci->name);
1244
        break;
1245
    case OHCI_USB_RESET:
1246
        ohci_reset(ohci);
1247
        dprintf("usb-ohci: %s: USB Reset\n", ohci->name);
1248
        break;
1249
    }
1250
}
1251

    
1252
static uint32_t ohci_get_frame_remaining(OHCIState *ohci)
1253
{
1254
    uint16_t fr;
1255
    int64_t tks;
1256

    
1257
    if ((ohci->ctl & OHCI_CTL_HCFS) != OHCI_USB_OPERATIONAL)
1258
        return (ohci->frt << 31);
1259

    
1260
    /* Being in USB operational state guarnatees sof_time was
1261
     * set already.
1262
     */
1263
    tks = qemu_get_clock(vm_clock) - ohci->sof_time;
1264

    
1265
    /* avoid muldiv if possible */
1266
    if (tks >= usb_frame_time)
1267
        return (ohci->frt << 31);
1268

    
1269
    tks = muldiv64(1, tks, usb_bit_time);
1270
    fr = (uint16_t)(ohci->fi - tks);
1271

    
1272
    return (ohci->frt << 31) | fr;
1273
}
1274

    
1275

    
1276
/* Set root hub status */
1277
static void ohci_set_hub_status(OHCIState *ohci, uint32_t val)
1278
{
1279
    uint32_t old_state;
1280

    
1281
    old_state = ohci->rhstatus;
1282

    
1283
    /* write 1 to clear OCIC */
1284
    if (val & OHCI_RHS_OCIC)
1285
        ohci->rhstatus &= ~OHCI_RHS_OCIC;
1286

    
1287
    if (val & OHCI_RHS_LPS) {
1288
        int i;
1289

    
1290
        for (i = 0; i < ohci->num_ports; i++)
1291
            ohci_port_power(ohci, i, 0);
1292
        dprintf("usb-ohci: powered down all ports\n");
1293
    }
1294

    
1295
    if (val & OHCI_RHS_LPSC) {
1296
        int i;
1297

    
1298
        for (i = 0; i < ohci->num_ports; i++)
1299
            ohci_port_power(ohci, i, 1);
1300
        dprintf("usb-ohci: powered up all ports\n");
1301
    }
1302

    
1303
    if (val & OHCI_RHS_DRWE)
1304
        ohci->rhstatus |= OHCI_RHS_DRWE;
1305

    
1306
    if (val & OHCI_RHS_CRWE)
1307
        ohci->rhstatus &= ~OHCI_RHS_DRWE;
1308

    
1309
    if (old_state != ohci->rhstatus)
1310
        ohci_set_interrupt(ohci, OHCI_INTR_RHSC);
1311
}
1312

    
1313
/* Set root hub port status */
1314
static void ohci_port_set_status(OHCIState *ohci, int portnum, uint32_t val)
1315
{
1316
    uint32_t old_state;
1317
    OHCIPort *port;
1318

    
1319
    port = &ohci->rhport[portnum];
1320
    old_state = port->ctrl;
1321

    
1322
    /* Write to clear CSC, PESC, PSSC, OCIC, PRSC */
1323
    if (val & OHCI_PORT_WTC)
1324
        port->ctrl &= ~(val & OHCI_PORT_WTC);
1325

    
1326
    if (val & OHCI_PORT_CCS)
1327
        port->ctrl &= ~OHCI_PORT_PES;
1328

    
1329
    ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PES);
1330

    
1331
    if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PSS))
1332
        dprintf("usb-ohci: port %d: SUSPEND\n", portnum);
1333

    
1334
    if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PRS)) {
1335
        dprintf("usb-ohci: port %d: RESET\n", portnum);
1336
        usb_send_msg(port->port.dev, USB_MSG_RESET);
1337
        port->ctrl &= ~OHCI_PORT_PRS;
1338
        /* ??? Should this also set OHCI_PORT_PESC.  */
1339
        port->ctrl |= OHCI_PORT_PES | OHCI_PORT_PRSC;
1340
    }
1341

    
1342
    /* Invert order here to ensure in ambiguous case, device is
1343
     * powered up...
1344
     */
1345
    if (val & OHCI_PORT_LSDA)
1346
        ohci_port_power(ohci, portnum, 0);
1347
    if (val & OHCI_PORT_PPS)
1348
        ohci_port_power(ohci, portnum, 1);
1349

    
1350
    if (old_state != port->ctrl)
1351
        ohci_set_interrupt(ohci, OHCI_INTR_RHSC);
1352

    
1353
    return;
1354
}
1355

    
1356
static uint32_t ohci_mem_read(void *ptr, target_phys_addr_t addr)
1357
{
1358
    OHCIState *ohci = ptr;
1359

    
1360
    addr -= ohci->mem_base;
1361

    
1362
    /* Only aligned reads are allowed on OHCI */
1363
    if (addr & 3) {
1364
        fprintf(stderr, "usb-ohci: Mis-aligned read\n");
1365
        return 0xffffffff;
1366
    }
1367

    
1368
    if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) {
1369
        /* HcRhPortStatus */
1370
        return ohci->rhport[(addr - 0x54) >> 2].ctrl | OHCI_PORT_PPS;
1371
    }
1372

    
1373
    switch (addr >> 2) {
1374
    case 0: /* HcRevision */
1375
        return 0x10;
1376

    
1377
    case 1: /* HcControl */
1378
        return ohci->ctl;
1379

    
1380
    case 2: /* HcCommandStatus */
1381
        return ohci->status;
1382

    
1383
    case 3: /* HcInterruptStatus */
1384
        return ohci->intr_status;
1385

    
1386
    case 4: /* HcInterruptEnable */
1387
    case 5: /* HcInterruptDisable */
1388
        return ohci->intr;
1389

    
1390
    case 6: /* HcHCCA */
1391
        return ohci->hcca;
1392

    
1393
    case 7: /* HcPeriodCurrentED */
1394
        return ohci->per_cur;
1395

    
1396
    case 8: /* HcControlHeadED */
1397
        return ohci->ctrl_head;
1398

    
1399
    case 9: /* HcControlCurrentED */
1400
        return ohci->ctrl_cur;
1401

    
1402
    case 10: /* HcBulkHeadED */
1403
        return ohci->bulk_head;
1404

    
1405
    case 11: /* HcBulkCurrentED */
1406
        return ohci->bulk_cur;
1407

    
1408
    case 12: /* HcDoneHead */
1409
        return ohci->done;
1410

    
1411
    case 13: /* HcFmInterval */
1412
        return (ohci->fit << 31) | (ohci->fsmps << 16) | (ohci->fi);
1413

    
1414
    case 14: /* HcFmRemaining */
1415
        return ohci_get_frame_remaining(ohci);
1416

    
1417
    case 15: /* HcFmNumber */
1418
        return ohci->frame_number;
1419

    
1420
    case 16: /* HcPeriodicStart */
1421
        return ohci->pstart;
1422

    
1423
    case 17: /* HcLSThreshold */
1424
        return ohci->lst;
1425

    
1426
    case 18: /* HcRhDescriptorA */
1427
        return ohci->rhdesc_a;
1428

    
1429
    case 19: /* HcRhDescriptorB */
1430
        return ohci->rhdesc_b;
1431

    
1432
    case 20: /* HcRhStatus */
1433
        return ohci->rhstatus;
1434

    
1435
    /* PXA27x specific registers */
1436
    case 24: /* HcStatus */
1437
        return ohci->hstatus & ohci->hmask;
1438

    
1439
    case 25: /* HcHReset */
1440
        return ohci->hreset;
1441

    
1442
    case 26: /* HcHInterruptEnable */
1443
        return ohci->hmask;
1444

    
1445
    case 27: /* HcHInterruptTest */
1446
        return ohci->htest;
1447

    
1448
    default:
1449
        fprintf(stderr, "ohci_read: Bad offset %x\n", (int)addr);
1450
        return 0xffffffff;
1451
    }
1452
}
1453

    
1454
static void ohci_mem_write(void *ptr, target_phys_addr_t addr, uint32_t val)
1455
{
1456
    OHCIState *ohci = ptr;
1457

    
1458
    addr -= ohci->mem_base;
1459

    
1460
    /* Only aligned reads are allowed on OHCI */
1461
    if (addr & 3) {
1462
        fprintf(stderr, "usb-ohci: Mis-aligned write\n");
1463
        return;
1464
    }
1465

    
1466
    if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) {
1467
        /* HcRhPortStatus */
1468
        ohci_port_set_status(ohci, (addr - 0x54) >> 2, val);
1469
        return;
1470
    }
1471

    
1472
    switch (addr >> 2) {
1473
    case 1: /* HcControl */
1474
        ohci_set_ctl(ohci, val);
1475
        break;
1476

    
1477
    case 2: /* HcCommandStatus */
1478
        /* SOC is read-only */
1479
        val = (val & ~OHCI_STATUS_SOC);
1480

    
1481
        /* Bits written as '0' remain unchanged in the register */
1482
        ohci->status |= val;
1483

    
1484
        if (ohci->status & OHCI_STATUS_HCR)
1485
            ohci_reset(ohci);
1486
        break;
1487

    
1488
    case 3: /* HcInterruptStatus */
1489
        ohci->intr_status &= ~val;
1490
        ohci_intr_update(ohci);
1491
        break;
1492

    
1493
    case 4: /* HcInterruptEnable */
1494
        ohci->intr |= val;
1495
        ohci_intr_update(ohci);
1496
        break;
1497

    
1498
    case 5: /* HcInterruptDisable */
1499
        ohci->intr &= ~val;
1500
        ohci_intr_update(ohci);
1501
        break;
1502

    
1503
    case 6: /* HcHCCA */
1504
        ohci->hcca = val & OHCI_HCCA_MASK;
1505
        break;
1506

    
1507
    case 8: /* HcControlHeadED */
1508
        ohci->ctrl_head = val & OHCI_EDPTR_MASK;
1509
        break;
1510

    
1511
    case 9: /* HcControlCurrentED */
1512
        ohci->ctrl_cur = val & OHCI_EDPTR_MASK;
1513
        break;
1514

    
1515
    case 10: /* HcBulkHeadED */
1516
        ohci->bulk_head = val & OHCI_EDPTR_MASK;
1517
        break;
1518

    
1519
    case 11: /* HcBulkCurrentED */
1520
        ohci->bulk_cur = val & OHCI_EDPTR_MASK;
1521
        break;
1522

    
1523
    case 13: /* HcFmInterval */
1524
        ohci->fsmps = (val & OHCI_FMI_FSMPS) >> 16;
1525
        ohci->fit = (val & OHCI_FMI_FIT) >> 31;
1526
        ohci_set_frame_interval(ohci, val);
1527
        break;
1528

    
1529
    case 15: /* HcFmNumber */
1530
        break;
1531

    
1532
    case 16: /* HcPeriodicStart */
1533
        ohci->pstart = val & 0xffff;
1534
        break;
1535

    
1536
    case 17: /* HcLSThreshold */
1537
        ohci->lst = val & 0xffff;
1538
        break;
1539

    
1540
    case 18: /* HcRhDescriptorA */
1541
        ohci->rhdesc_a &= ~OHCI_RHA_RW_MASK;
1542
        ohci->rhdesc_a |= val & OHCI_RHA_RW_MASK;
1543
        break;
1544

    
1545
    case 19: /* HcRhDescriptorB */
1546
        break;
1547

    
1548
    case 20: /* HcRhStatus */
1549
        ohci_set_hub_status(ohci, val);
1550
        break;
1551

    
1552
    /* PXA27x specific registers */
1553
    case 24: /* HcStatus */
1554
        ohci->hstatus &= ~(val & ohci->hmask);
1555

    
1556
    case 25: /* HcHReset */
1557
        ohci->hreset = val & ~OHCI_HRESET_FSBIR;
1558
        if (val & OHCI_HRESET_FSBIR)
1559
            ohci_reset(ohci);
1560
        break;
1561

    
1562
    case 26: /* HcHInterruptEnable */
1563
        ohci->hmask = val;
1564
        break;
1565

    
1566
    case 27: /* HcHInterruptTest */
1567
        ohci->htest = val;
1568
        break;
1569

    
1570
    default:
1571
        fprintf(stderr, "ohci_write: Bad offset %x\n", (int)addr);
1572
        break;
1573
    }
1574
}
1575

    
1576
/* Only dword reads are defined on OHCI register space */
1577
static CPUReadMemoryFunc *ohci_readfn[3]={
1578
    ohci_mem_read,
1579
    ohci_mem_read,
1580
    ohci_mem_read
1581
};
1582

    
1583
/* Only dword writes are defined on OHCI register space */
1584
static CPUWriteMemoryFunc *ohci_writefn[3]={
1585
    ohci_mem_write,
1586
    ohci_mem_write,
1587
    ohci_mem_write
1588
};
1589

    
1590
static void usb_ohci_init(OHCIState *ohci, int num_ports, int devfn,
1591
            qemu_irq irq, enum ohci_type type, const char *name)
1592
{
1593
    int i;
1594

    
1595
    if (usb_frame_time == 0) {
1596
#if OHCI_TIME_WARP
1597
        usb_frame_time = ticks_per_sec;
1598
        usb_bit_time = muldiv64(1, ticks_per_sec, USB_HZ/1000);
1599
#else
1600
        usb_frame_time = muldiv64(1, ticks_per_sec, 1000);
1601
        if (ticks_per_sec >= USB_HZ) {
1602
            usb_bit_time = muldiv64(1, ticks_per_sec, USB_HZ);
1603
        } else {
1604
            usb_bit_time = 1;
1605
        }
1606
#endif
1607
        dprintf("usb-ohci: usb_bit_time=%lli usb_frame_time=%lli\n",
1608
                usb_frame_time, usb_bit_time);
1609
    }
1610

    
1611
    ohci->mem = cpu_register_io_memory(0, ohci_readfn, ohci_writefn, ohci);
1612
    ohci->name = name;
1613

    
1614
    ohci->irq = irq;
1615
    ohci->type = type;
1616

    
1617
    ohci->num_ports = num_ports;
1618
    for (i = 0; i < num_ports; i++) {
1619
        qemu_register_usb_port(&ohci->rhport[i].port, ohci, i, ohci_attach);
1620
    }
1621

    
1622
    ohci->async_td = 0;
1623
    qemu_register_reset(ohci_reset, ohci);
1624
    ohci_reset(ohci);
1625
}
1626

    
1627
typedef struct {
1628
    PCIDevice pci_dev;
1629
    OHCIState state;
1630
} OHCIPCIState;
1631

    
1632
static void ohci_mapfunc(PCIDevice *pci_dev, int i,
1633
            uint32_t addr, uint32_t size, int type)
1634
{
1635
    OHCIPCIState *ohci = (OHCIPCIState *)pci_dev;
1636
    ohci->state.mem_base = addr;
1637
    cpu_register_physical_memory(addr, size, ohci->state.mem);
1638
}
1639

    
1640
void usb_ohci_init_pci(struct PCIBus *bus, int num_ports, int devfn)
1641
{
1642
    OHCIPCIState *ohci;
1643
    int vid = 0x106b;
1644
    int did = 0x003f;
1645

    
1646
    ohci = (OHCIPCIState *)pci_register_device(bus, "OHCI USB", sizeof(*ohci),
1647
                                               devfn, NULL, NULL);
1648
    if (ohci == NULL) {
1649
        fprintf(stderr, "usb-ohci: Failed to register PCI device\n");
1650
        return;
1651
    }
1652

    
1653
    ohci->pci_dev.config[0x00] = vid & 0xff;
1654
    ohci->pci_dev.config[0x01] = (vid >> 8) & 0xff;
1655
    ohci->pci_dev.config[0x02] = did & 0xff;
1656
    ohci->pci_dev.config[0x03] = (did >> 8) & 0xff;
1657
    ohci->pci_dev.config[0x09] = 0x10; /* OHCI */
1658
    ohci->pci_dev.config[0x0a] = 0x3;
1659
    ohci->pci_dev.config[0x0b] = 0xc;
1660
    ohci->pci_dev.config[0x3d] = 0x01; /* interrupt pin 1 */
1661

    
1662
    usb_ohci_init(&ohci->state, num_ports, devfn, ohci->pci_dev.irq[0],
1663
                  OHCI_TYPE_PCI, ohci->pci_dev.name);
1664

    
1665
    pci_register_io_region((struct PCIDevice *)ohci, 0, 256,
1666
                           PCI_ADDRESS_SPACE_MEM, ohci_mapfunc);
1667
}
1668

    
1669
void usb_ohci_init_pxa(target_phys_addr_t base, int num_ports, int devfn,
1670
                       qemu_irq irq)
1671
{
1672
    OHCIState *ohci = (OHCIState *)qemu_mallocz(sizeof(OHCIState));
1673

    
1674
    usb_ohci_init(ohci, num_ports, devfn, irq,
1675
                  OHCI_TYPE_PXA, "OHCI USB");
1676
    ohci->mem_base = base;
1677

    
1678
    cpu_register_physical_memory(ohci->mem_base, 0x1000, ohci->mem);
1679
}