root / target-arm / cpu.c @ 7c1840b6
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/*
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* QEMU ARM CPU
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*
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* Copyright (c) 2012 SUSE LINUX Products GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see
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* <http://www.gnu.org/licenses/gpl-2.0.html>
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*/
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#include "cpu.h" |
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#include "qemu-common.h" |
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#if !defined(CONFIG_USER_ONLY)
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#include "hw/loader.h" |
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#endif
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#include "hw/arm/arm.h" |
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#include "sysemu/sysemu.h" |
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#include "sysemu/kvm.h" |
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static void arm_cpu_set_pc(CPUState *cs, vaddr value) |
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{ |
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ARMCPU *cpu = ARM_CPU(cs); |
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cpu->env.regs[15] = value;
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} |
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static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) |
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{ |
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/* Reset a single ARMCPRegInfo register */
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ARMCPRegInfo *ri = value; |
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ARMCPU *cpu = opaque; |
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if (ri->type & ARM_CP_SPECIAL) {
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return;
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} |
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if (ri->resetfn) {
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ri->resetfn(&cpu->env, ri); |
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return;
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} |
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/* A zero offset is never possible as it would be regs[0]
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* so we use it to indicate that reset is being handled elsewhere.
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* This is basically only used for fields in non-core coprocessors
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* (like the pxa2xx ones).
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*/
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if (!ri->fieldoffset) {
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return;
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} |
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if (ri->type & ARM_CP_64BIT) {
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CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; |
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} else {
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CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; |
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} |
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} |
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/* CPUClass::reset() */
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static void arm_cpu_reset(CPUState *s) |
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{ |
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ARMCPU *cpu = ARM_CPU(s); |
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ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); |
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CPUARMState *env = &cpu->env; |
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acc->parent_reset(s); |
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memset(env, 0, offsetof(CPUARMState, breakpoints));
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g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); |
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env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; |
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env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0; |
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env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1; |
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if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
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env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; |
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} |
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#if defined(CONFIG_USER_ONLY)
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env->uncached_cpsr = ARM_CPU_MODE_USR; |
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/* For user mode we must enable access to coprocessors */
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env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; |
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if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
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env->cp15.c15_cpar = 3;
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} else if (arm_feature(env, ARM_FEATURE_XSCALE)) { |
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env->cp15.c15_cpar = 1;
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} |
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#else
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/* SVC mode with interrupts disabled. */
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env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I; |
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/* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
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clear at reset. Initial SP and PC are loaded from ROM. */
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if (IS_M(env)) {
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uint32_t pc; |
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uint8_t *rom; |
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env->uncached_cpsr &= ~CPSR_I; |
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rom = rom_ptr(0);
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if (rom) {
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/* We should really use ldl_phys here, in case the guest
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modified flash and reset itself. However images
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loaded via -kernel have not been copied yet, so load the
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values directly from there. */
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env->regs[13] = ldl_p(rom);
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pc = ldl_p(rom + 4);
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env->thumb = pc & 1;
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env->regs[15] = pc & ~1; |
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} |
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} |
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env->vfp.xregs[ARM_VFP_FPEXC] = 0;
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#endif
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set_flush_to_zero(1, &env->vfp.standard_fp_status);
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set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
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set_default_nan_mode(1, &env->vfp.standard_fp_status);
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set_float_detect_tininess(float_tininess_before_rounding, |
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&env->vfp.fp_status); |
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set_float_detect_tininess(float_tininess_before_rounding, |
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&env->vfp.standard_fp_status); |
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tlb_flush(env, 1);
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/* Reset is a state change for some CPUARMState fields which we
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* bake assumptions about into translated code, so we need to
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* tb_flush().
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*/
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tb_flush(env); |
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} |
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#ifndef CONFIG_USER_ONLY
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static void arm_cpu_set_irq(void *opaque, int irq, int level) |
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{ |
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ARMCPU *cpu = opaque; |
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CPUState *cs = CPU(cpu); |
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switch (irq) {
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case ARM_CPU_IRQ:
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if (level) {
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cpu_interrupt(cs, CPU_INTERRUPT_HARD); |
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} else {
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cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); |
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} |
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break;
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case ARM_CPU_FIQ:
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if (level) {
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cpu_interrupt(cs, CPU_INTERRUPT_FIQ); |
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} else {
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cpu_reset_interrupt(cs, CPU_INTERRUPT_FIQ); |
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} |
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break;
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default:
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hw_error("arm_cpu_set_irq: Bad interrupt line %d\n", irq);
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} |
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} |
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static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) |
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{ |
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#ifdef CONFIG_KVM
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ARMCPU *cpu = opaque; |
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CPUState *cs = CPU(cpu); |
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int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT;
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switch (irq) {
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case ARM_CPU_IRQ:
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kvm_irq |= KVM_ARM_IRQ_CPU_IRQ; |
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break;
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case ARM_CPU_FIQ:
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kvm_irq |= KVM_ARM_IRQ_CPU_FIQ; |
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break;
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default:
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hw_error("arm_cpu_kvm_set_irq: Bad interrupt line %d\n", irq);
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} |
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kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT; |
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kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0); |
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#endif
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} |
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#endif
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static inline void set_feature(CPUARMState *env, int feature) |
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{ |
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env->features |= 1ULL << feature;
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} |
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static void arm_cpu_initfn(Object *obj) |
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{ |
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CPUState *cs = CPU(obj); |
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ARMCPU *cpu = ARM_CPU(obj); |
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static bool inited; |
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cs->env_ptr = &cpu->env; |
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cpu_exec_init(&cpu->env); |
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cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, |
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g_free, g_free); |
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#ifndef CONFIG_USER_ONLY
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/* Our inbound IRQ and FIQ lines */
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if (kvm_enabled()) {
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qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 2);
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} else {
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qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 2);
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} |
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#endif
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if (tcg_enabled() && !inited) {
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inited = true;
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arm_translate_init(); |
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} |
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} |
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static void arm_cpu_finalizefn(Object *obj) |
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{ |
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ARMCPU *cpu = ARM_CPU(obj); |
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g_hash_table_destroy(cpu->cp_regs); |
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} |
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static void arm_cpu_realizefn(DeviceState *dev, Error **errp) |
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{ |
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CPUState *cs = CPU(dev); |
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ARMCPU *cpu = ARM_CPU(dev); |
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ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); |
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CPUARMState *env = &cpu->env; |
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/* Some features automatically imply others: */
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if (arm_feature(env, ARM_FEATURE_V8)) {
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set_feature(env, ARM_FEATURE_V7); |
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set_feature(env, ARM_FEATURE_ARM_DIV); |
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set_feature(env, ARM_FEATURE_LPAE); |
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} |
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if (arm_feature(env, ARM_FEATURE_V7)) {
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set_feature(env, ARM_FEATURE_VAPA); |
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set_feature(env, ARM_FEATURE_THUMB2); |
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set_feature(env, ARM_FEATURE_MPIDR); |
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if (!arm_feature(env, ARM_FEATURE_M)) {
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set_feature(env, ARM_FEATURE_V6K); |
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} else {
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set_feature(env, ARM_FEATURE_V6); |
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} |
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} |
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if (arm_feature(env, ARM_FEATURE_V6K)) {
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set_feature(env, ARM_FEATURE_V6); |
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set_feature(env, ARM_FEATURE_MVFR); |
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} |
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if (arm_feature(env, ARM_FEATURE_V6)) {
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set_feature(env, ARM_FEATURE_V5); |
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if (!arm_feature(env, ARM_FEATURE_M)) {
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set_feature(env, ARM_FEATURE_AUXCR); |
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} |
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} |
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if (arm_feature(env, ARM_FEATURE_V5)) {
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set_feature(env, ARM_FEATURE_V4T); |
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} |
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if (arm_feature(env, ARM_FEATURE_M)) {
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set_feature(env, ARM_FEATURE_THUMB_DIV); |
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} |
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if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
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set_feature(env, ARM_FEATURE_THUMB_DIV); |
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} |
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if (arm_feature(env, ARM_FEATURE_VFP4)) {
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set_feature(env, ARM_FEATURE_VFP3); |
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} |
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if (arm_feature(env, ARM_FEATURE_VFP3)) {
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set_feature(env, ARM_FEATURE_VFP); |
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} |
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if (arm_feature(env, ARM_FEATURE_LPAE)) {
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set_feature(env, ARM_FEATURE_V7MP); |
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set_feature(env, ARM_FEATURE_PXN); |
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} |
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register_cp_regs_for_features(cpu); |
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arm_cpu_register_gdb_regs_for_features(cpu); |
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init_cpreg_list(cpu); |
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cpu_reset(cs); |
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qemu_init_vcpu(cs); |
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acc->parent_realize(dev, errp); |
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} |
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/* CPU models */
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static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) |
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{ |
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ObjectClass *oc; |
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char *typename;
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if (!cpu_model) {
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return NULL; |
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} |
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typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpu_model);
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oc = object_class_by_name(typename); |
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g_free(typename); |
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if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
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object_class_is_abstract(oc)) { |
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return NULL; |
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} |
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return oc;
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} |
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static void arm926_initfn(Object *obj) |
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{ |
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ARMCPU *cpu = ARM_CPU(obj); |
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set_feature(&cpu->env, ARM_FEATURE_V5); |
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set_feature(&cpu->env, ARM_FEATURE_VFP); |
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set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
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set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); |
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cpu->midr = 0x41069265;
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cpu->reset_fpsid = 0x41011090;
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cpu->ctr = 0x1dd20d2;
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cpu->reset_sctlr = 0x00090078;
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} |
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static void arm946_initfn(Object *obj) |
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{ |
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ARMCPU *cpu = ARM_CPU(obj); |
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set_feature(&cpu->env, ARM_FEATURE_V5); |
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set_feature(&cpu->env, ARM_FEATURE_MPU); |
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set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
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cpu->midr = 0x41059461;
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cpu->ctr = 0x0f004006;
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cpu->reset_sctlr = 0x00000078;
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} |
328 |
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static void arm1026_initfn(Object *obj) |
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{ |
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ARMCPU *cpu = ARM_CPU(obj); |
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set_feature(&cpu->env, ARM_FEATURE_V5); |
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set_feature(&cpu->env, ARM_FEATURE_VFP); |
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set_feature(&cpu->env, ARM_FEATURE_AUXCR); |
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set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
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set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); |
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cpu->midr = 0x4106a262;
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cpu->reset_fpsid = 0x410110a0;
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cpu->ctr = 0x1dd20d2;
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cpu->reset_sctlr = 0x00090078;
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cpu->reset_auxcr = 1;
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{ |
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/* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
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ARMCPRegInfo ifar = { |
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.name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, |
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.access = PL1_RW, |
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.fieldoffset = offsetof(CPUARMState, cp15.c6_insn), |
348 |
.resetvalue = 0
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}; |
350 |
define_one_arm_cp_reg(cpu, &ifar); |
351 |
} |
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} |
353 |
|
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static void arm1136_r2_initfn(Object *obj) |
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{ |
356 |
ARMCPU *cpu = ARM_CPU(obj); |
357 |
/* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
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* older core than plain "arm1136". In particular this does not
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* have the v6K features.
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* These ID register values are correct for 1136 but may be wrong
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* for 1136_r2 (in particular r0p2 does not actually implement most
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* of the ID registers).
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*/
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set_feature(&cpu->env, ARM_FEATURE_V6); |
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set_feature(&cpu->env, ARM_FEATURE_VFP); |
366 |
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
367 |
set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); |
368 |
set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); |
369 |
cpu->midr = 0x4107b362;
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cpu->reset_fpsid = 0x410120b4;
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cpu->mvfr0 = 0x11111111;
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cpu->mvfr1 = 0x00000000;
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cpu->ctr = 0x1dd20d2;
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cpu->reset_sctlr = 0x00050078;
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cpu->id_pfr0 = 0x111;
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cpu->id_pfr1 = 0x1;
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cpu->id_dfr0 = 0x2;
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cpu->id_afr0 = 0x3;
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cpu->id_mmfr0 = 0x01130003;
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380 |
cpu->id_mmfr1 = 0x10030302;
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381 |
cpu->id_mmfr2 = 0x01222110;
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cpu->id_isar0 = 0x00140011;
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cpu->id_isar1 = 0x12002111;
|
384 |
cpu->id_isar2 = 0x11231111;
|
385 |
cpu->id_isar3 = 0x01102131;
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386 |
cpu->id_isar4 = 0x141;
|
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cpu->reset_auxcr = 7;
|
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} |
389 |
|
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static void arm1136_initfn(Object *obj) |
391 |
{ |
392 |
ARMCPU *cpu = ARM_CPU(obj); |
393 |
set_feature(&cpu->env, ARM_FEATURE_V6K); |
394 |
set_feature(&cpu->env, ARM_FEATURE_V6); |
395 |
set_feature(&cpu->env, ARM_FEATURE_VFP); |
396 |
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
397 |
set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); |
398 |
set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); |
399 |
cpu->midr = 0x4117b363;
|
400 |
cpu->reset_fpsid = 0x410120b4;
|
401 |
cpu->mvfr0 = 0x11111111;
|
402 |
cpu->mvfr1 = 0x00000000;
|
403 |
cpu->ctr = 0x1dd20d2;
|
404 |
cpu->reset_sctlr = 0x00050078;
|
405 |
cpu->id_pfr0 = 0x111;
|
406 |
cpu->id_pfr1 = 0x1;
|
407 |
cpu->id_dfr0 = 0x2;
|
408 |
cpu->id_afr0 = 0x3;
|
409 |
cpu->id_mmfr0 = 0x01130003;
|
410 |
cpu->id_mmfr1 = 0x10030302;
|
411 |
cpu->id_mmfr2 = 0x01222110;
|
412 |
cpu->id_isar0 = 0x00140011;
|
413 |
cpu->id_isar1 = 0x12002111;
|
414 |
cpu->id_isar2 = 0x11231111;
|
415 |
cpu->id_isar3 = 0x01102131;
|
416 |
cpu->id_isar4 = 0x141;
|
417 |
cpu->reset_auxcr = 7;
|
418 |
} |
419 |
|
420 |
static void arm1176_initfn(Object *obj) |
421 |
{ |
422 |
ARMCPU *cpu = ARM_CPU(obj); |
423 |
set_feature(&cpu->env, ARM_FEATURE_V6K); |
424 |
set_feature(&cpu->env, ARM_FEATURE_VFP); |
425 |
set_feature(&cpu->env, ARM_FEATURE_VAPA); |
426 |
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
427 |
set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); |
428 |
set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); |
429 |
cpu->midr = 0x410fb767;
|
430 |
cpu->reset_fpsid = 0x410120b5;
|
431 |
cpu->mvfr0 = 0x11111111;
|
432 |
cpu->mvfr1 = 0x00000000;
|
433 |
cpu->ctr = 0x1dd20d2;
|
434 |
cpu->reset_sctlr = 0x00050078;
|
435 |
cpu->id_pfr0 = 0x111;
|
436 |
cpu->id_pfr1 = 0x11;
|
437 |
cpu->id_dfr0 = 0x33;
|
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cpu->id_afr0 = 0;
|
439 |
cpu->id_mmfr0 = 0x01130003;
|
440 |
cpu->id_mmfr1 = 0x10030302;
|
441 |
cpu->id_mmfr2 = 0x01222100;
|
442 |
cpu->id_isar0 = 0x0140011;
|
443 |
cpu->id_isar1 = 0x12002111;
|
444 |
cpu->id_isar2 = 0x11231121;
|
445 |
cpu->id_isar3 = 0x01102131;
|
446 |
cpu->id_isar4 = 0x01141;
|
447 |
cpu->reset_auxcr = 7;
|
448 |
} |
449 |
|
450 |
static void arm11mpcore_initfn(Object *obj) |
451 |
{ |
452 |
ARMCPU *cpu = ARM_CPU(obj); |
453 |
set_feature(&cpu->env, ARM_FEATURE_V6K); |
454 |
set_feature(&cpu->env, ARM_FEATURE_VFP); |
455 |
set_feature(&cpu->env, ARM_FEATURE_VAPA); |
456 |
set_feature(&cpu->env, ARM_FEATURE_MPIDR); |
457 |
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
458 |
cpu->midr = 0x410fb022;
|
459 |
cpu->reset_fpsid = 0x410120b4;
|
460 |
cpu->mvfr0 = 0x11111111;
|
461 |
cpu->mvfr1 = 0x00000000;
|
462 |
cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */ |
463 |
cpu->id_pfr0 = 0x111;
|
464 |
cpu->id_pfr1 = 0x1;
|
465 |
cpu->id_dfr0 = 0;
|
466 |
cpu->id_afr0 = 0x2;
|
467 |
cpu->id_mmfr0 = 0x01100103;
|
468 |
cpu->id_mmfr1 = 0x10020302;
|
469 |
cpu->id_mmfr2 = 0x01222000;
|
470 |
cpu->id_isar0 = 0x00100011;
|
471 |
cpu->id_isar1 = 0x12002111;
|
472 |
cpu->id_isar2 = 0x11221011;
|
473 |
cpu->id_isar3 = 0x01102131;
|
474 |
cpu->id_isar4 = 0x141;
|
475 |
cpu->reset_auxcr = 1;
|
476 |
} |
477 |
|
478 |
static void cortex_m3_initfn(Object *obj) |
479 |
{ |
480 |
ARMCPU *cpu = ARM_CPU(obj); |
481 |
set_feature(&cpu->env, ARM_FEATURE_V7); |
482 |
set_feature(&cpu->env, ARM_FEATURE_M); |
483 |
cpu->midr = 0x410fc231;
|
484 |
} |
485 |
|
486 |
static void arm_v7m_class_init(ObjectClass *oc, void *data) |
487 |
{ |
488 |
#ifndef CONFIG_USER_ONLY
|
489 |
CPUClass *cc = CPU_CLASS(oc); |
490 |
|
491 |
cc->do_interrupt = arm_v7m_cpu_do_interrupt; |
492 |
#endif
|
493 |
} |
494 |
|
495 |
static const ARMCPRegInfo cortexa8_cp_reginfo[] = { |
496 |
{ .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, |
497 |
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
|
498 |
{ .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, |
499 |
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
|
500 |
REGINFO_SENTINEL |
501 |
}; |
502 |
|
503 |
static void cortex_a8_initfn(Object *obj) |
504 |
{ |
505 |
ARMCPU *cpu = ARM_CPU(obj); |
506 |
set_feature(&cpu->env, ARM_FEATURE_V7); |
507 |
set_feature(&cpu->env, ARM_FEATURE_VFP3); |
508 |
set_feature(&cpu->env, ARM_FEATURE_NEON); |
509 |
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); |
510 |
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
511 |
cpu->midr = 0x410fc080;
|
512 |
cpu->reset_fpsid = 0x410330c0;
|
513 |
cpu->mvfr0 = 0x11110222;
|
514 |
cpu->mvfr1 = 0x00011100;
|
515 |
cpu->ctr = 0x82048004;
|
516 |
cpu->reset_sctlr = 0x00c50078;
|
517 |
cpu->id_pfr0 = 0x1031;
|
518 |
cpu->id_pfr1 = 0x11;
|
519 |
cpu->id_dfr0 = 0x400;
|
520 |
cpu->id_afr0 = 0;
|
521 |
cpu->id_mmfr0 = 0x31100003;
|
522 |
cpu->id_mmfr1 = 0x20000000;
|
523 |
cpu->id_mmfr2 = 0x01202000;
|
524 |
cpu->id_mmfr3 = 0x11;
|
525 |
cpu->id_isar0 = 0x00101111;
|
526 |
cpu->id_isar1 = 0x12112111;
|
527 |
cpu->id_isar2 = 0x21232031;
|
528 |
cpu->id_isar3 = 0x11112131;
|
529 |
cpu->id_isar4 = 0x00111142;
|
530 |
cpu->clidr = (1 << 27) | (2 << 24) | 3; |
531 |
cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ |
532 |
cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ |
533 |
cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ |
534 |
cpu->reset_auxcr = 2;
|
535 |
define_arm_cp_regs(cpu, cortexa8_cp_reginfo); |
536 |
} |
537 |
|
538 |
static const ARMCPRegInfo cortexa9_cp_reginfo[] = { |
539 |
/* power_control should be set to maximum latency. Again,
|
540 |
* default to 0 and set by private hook
|
541 |
*/
|
542 |
{ .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, |
543 |
.access = PL1_RW, .resetvalue = 0,
|
544 |
.fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) }, |
545 |
{ .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1, |
546 |
.access = PL1_RW, .resetvalue = 0,
|
547 |
.fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) }, |
548 |
{ .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2, |
549 |
.access = PL1_RW, .resetvalue = 0,
|
550 |
.fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) }, |
551 |
{ .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, |
552 |
.access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
|
553 |
/* TLB lockdown control */
|
554 |
{ .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2, |
555 |
.access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
|
556 |
{ .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4, |
557 |
.access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
|
558 |
{ .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2, |
559 |
.access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
|
560 |
{ .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2, |
561 |
.access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
|
562 |
{ .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2, |
563 |
.access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
|
564 |
REGINFO_SENTINEL |
565 |
}; |
566 |
|
567 |
static void cortex_a9_initfn(Object *obj) |
568 |
{ |
569 |
ARMCPU *cpu = ARM_CPU(obj); |
570 |
set_feature(&cpu->env, ARM_FEATURE_V7); |
571 |
set_feature(&cpu->env, ARM_FEATURE_VFP3); |
572 |
set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); |
573 |
set_feature(&cpu->env, ARM_FEATURE_NEON); |
574 |
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); |
575 |
/* Note that A9 supports the MP extensions even for
|
576 |
* A9UP and single-core A9MP (which are both different
|
577 |
* and valid configurations; we don't model A9UP).
|
578 |
*/
|
579 |
set_feature(&cpu->env, ARM_FEATURE_V7MP); |
580 |
cpu->midr = 0x410fc090;
|
581 |
cpu->reset_fpsid = 0x41033090;
|
582 |
cpu->mvfr0 = 0x11110222;
|
583 |
cpu->mvfr1 = 0x01111111;
|
584 |
cpu->ctr = 0x80038003;
|
585 |
cpu->reset_sctlr = 0x00c50078;
|
586 |
cpu->id_pfr0 = 0x1031;
|
587 |
cpu->id_pfr1 = 0x11;
|
588 |
cpu->id_dfr0 = 0x000;
|
589 |
cpu->id_afr0 = 0;
|
590 |
cpu->id_mmfr0 = 0x00100103;
|
591 |
cpu->id_mmfr1 = 0x20000000;
|
592 |
cpu->id_mmfr2 = 0x01230000;
|
593 |
cpu->id_mmfr3 = 0x00002111;
|
594 |
cpu->id_isar0 = 0x00101111;
|
595 |
cpu->id_isar1 = 0x13112111;
|
596 |
cpu->id_isar2 = 0x21232041;
|
597 |
cpu->id_isar3 = 0x11112131;
|
598 |
cpu->id_isar4 = 0x00111142;
|
599 |
cpu->clidr = (1 << 27) | (1 << 24) | 3; |
600 |
cpu->ccsidr[0] = 0xe00fe015; /* 16k L1 dcache. */ |
601 |
cpu->ccsidr[1] = 0x200fe015; /* 16k L1 icache. */ |
602 |
{ |
603 |
ARMCPRegInfo cbar = { |
604 |
.name = "CBAR", .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, |
605 |
.opc2 = 0, .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
|
606 |
.fieldoffset = offsetof(CPUARMState, cp15.c15_config_base_address) |
607 |
}; |
608 |
define_one_arm_cp_reg(cpu, &cbar); |
609 |
define_arm_cp_regs(cpu, cortexa9_cp_reginfo); |
610 |
} |
611 |
} |
612 |
|
613 |
#ifndef CONFIG_USER_ONLY
|
614 |
static int a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri, |
615 |
uint64_t *value) |
616 |
{ |
617 |
/* Linux wants the number of processors from here.
|
618 |
* Might as well set the interrupt-controller bit too.
|
619 |
*/
|
620 |
*value = ((smp_cpus - 1) << 24) | (1 << 23); |
621 |
return 0; |
622 |
} |
623 |
#endif
|
624 |
|
625 |
static const ARMCPRegInfo cortexa15_cp_reginfo[] = { |
626 |
#ifndef CONFIG_USER_ONLY
|
627 |
{ .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, |
628 |
.access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
|
629 |
.writefn = arm_cp_write_ignore, }, |
630 |
#endif
|
631 |
{ .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3, |
632 |
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
|
633 |
REGINFO_SENTINEL |
634 |
}; |
635 |
|
636 |
static void cortex_a15_initfn(Object *obj) |
637 |
{ |
638 |
ARMCPU *cpu = ARM_CPU(obj); |
639 |
set_feature(&cpu->env, ARM_FEATURE_V7); |
640 |
set_feature(&cpu->env, ARM_FEATURE_VFP4); |
641 |
set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); |
642 |
set_feature(&cpu->env, ARM_FEATURE_NEON); |
643 |
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); |
644 |
set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); |
645 |
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); |
646 |
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
647 |
set_feature(&cpu->env, ARM_FEATURE_LPAE); |
648 |
cpu->midr = 0x412fc0f1;
|
649 |
cpu->reset_fpsid = 0x410430f0;
|
650 |
cpu->mvfr0 = 0x10110222;
|
651 |
cpu->mvfr1 = 0x11111111;
|
652 |
cpu->ctr = 0x8444c004;
|
653 |
cpu->reset_sctlr = 0x00c50078;
|
654 |
cpu->id_pfr0 = 0x00001131;
|
655 |
cpu->id_pfr1 = 0x00011011;
|
656 |
cpu->id_dfr0 = 0x02010555;
|
657 |
cpu->id_afr0 = 0x00000000;
|
658 |
cpu->id_mmfr0 = 0x10201105;
|
659 |
cpu->id_mmfr1 = 0x20000000;
|
660 |
cpu->id_mmfr2 = 0x01240000;
|
661 |
cpu->id_mmfr3 = 0x02102211;
|
662 |
cpu->id_isar0 = 0x02101110;
|
663 |
cpu->id_isar1 = 0x13112111;
|
664 |
cpu->id_isar2 = 0x21232041;
|
665 |
cpu->id_isar3 = 0x11112131;
|
666 |
cpu->id_isar4 = 0x10011142;
|
667 |
cpu->clidr = 0x0a200023;
|
668 |
cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ |
669 |
cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ |
670 |
cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ |
671 |
define_arm_cp_regs(cpu, cortexa15_cp_reginfo); |
672 |
} |
673 |
|
674 |
static void ti925t_initfn(Object *obj) |
675 |
{ |
676 |
ARMCPU *cpu = ARM_CPU(obj); |
677 |
set_feature(&cpu->env, ARM_FEATURE_V4T); |
678 |
set_feature(&cpu->env, ARM_FEATURE_OMAPCP); |
679 |
cpu->midr = ARM_CPUID_TI925T; |
680 |
cpu->ctr = 0x5109149;
|
681 |
cpu->reset_sctlr = 0x00000070;
|
682 |
} |
683 |
|
684 |
static void sa1100_initfn(Object *obj) |
685 |
{ |
686 |
ARMCPU *cpu = ARM_CPU(obj); |
687 |
set_feature(&cpu->env, ARM_FEATURE_STRONGARM); |
688 |
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
689 |
cpu->midr = 0x4401A11B;
|
690 |
cpu->reset_sctlr = 0x00000070;
|
691 |
} |
692 |
|
693 |
static void sa1110_initfn(Object *obj) |
694 |
{ |
695 |
ARMCPU *cpu = ARM_CPU(obj); |
696 |
set_feature(&cpu->env, ARM_FEATURE_STRONGARM); |
697 |
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
698 |
cpu->midr = 0x6901B119;
|
699 |
cpu->reset_sctlr = 0x00000070;
|
700 |
} |
701 |
|
702 |
static void pxa250_initfn(Object *obj) |
703 |
{ |
704 |
ARMCPU *cpu = ARM_CPU(obj); |
705 |
set_feature(&cpu->env, ARM_FEATURE_V5); |
706 |
set_feature(&cpu->env, ARM_FEATURE_XSCALE); |
707 |
cpu->midr = 0x69052100;
|
708 |
cpu->ctr = 0xd172172;
|
709 |
cpu->reset_sctlr = 0x00000078;
|
710 |
} |
711 |
|
712 |
static void pxa255_initfn(Object *obj) |
713 |
{ |
714 |
ARMCPU *cpu = ARM_CPU(obj); |
715 |
set_feature(&cpu->env, ARM_FEATURE_V5); |
716 |
set_feature(&cpu->env, ARM_FEATURE_XSCALE); |
717 |
cpu->midr = 0x69052d00;
|
718 |
cpu->ctr = 0xd172172;
|
719 |
cpu->reset_sctlr = 0x00000078;
|
720 |
} |
721 |
|
722 |
static void pxa260_initfn(Object *obj) |
723 |
{ |
724 |
ARMCPU *cpu = ARM_CPU(obj); |
725 |
set_feature(&cpu->env, ARM_FEATURE_V5); |
726 |
set_feature(&cpu->env, ARM_FEATURE_XSCALE); |
727 |
cpu->midr = 0x69052903;
|
728 |
cpu->ctr = 0xd172172;
|
729 |
cpu->reset_sctlr = 0x00000078;
|
730 |
} |
731 |
|
732 |
static void pxa261_initfn(Object *obj) |
733 |
{ |
734 |
ARMCPU *cpu = ARM_CPU(obj); |
735 |
set_feature(&cpu->env, ARM_FEATURE_V5); |
736 |
set_feature(&cpu->env, ARM_FEATURE_XSCALE); |
737 |
cpu->midr = 0x69052d05;
|
738 |
cpu->ctr = 0xd172172;
|
739 |
cpu->reset_sctlr = 0x00000078;
|
740 |
} |
741 |
|
742 |
static void pxa262_initfn(Object *obj) |
743 |
{ |
744 |
ARMCPU *cpu = ARM_CPU(obj); |
745 |
set_feature(&cpu->env, ARM_FEATURE_V5); |
746 |
set_feature(&cpu->env, ARM_FEATURE_XSCALE); |
747 |
cpu->midr = 0x69052d06;
|
748 |
cpu->ctr = 0xd172172;
|
749 |
cpu->reset_sctlr = 0x00000078;
|
750 |
} |
751 |
|
752 |
static void pxa270a0_initfn(Object *obj) |
753 |
{ |
754 |
ARMCPU *cpu = ARM_CPU(obj); |
755 |
set_feature(&cpu->env, ARM_FEATURE_V5); |
756 |
set_feature(&cpu->env, ARM_FEATURE_XSCALE); |
757 |
set_feature(&cpu->env, ARM_FEATURE_IWMMXT); |
758 |
cpu->midr = 0x69054110;
|
759 |
cpu->ctr = 0xd172172;
|
760 |
cpu->reset_sctlr = 0x00000078;
|
761 |
} |
762 |
|
763 |
static void pxa270a1_initfn(Object *obj) |
764 |
{ |
765 |
ARMCPU *cpu = ARM_CPU(obj); |
766 |
set_feature(&cpu->env, ARM_FEATURE_V5); |
767 |
set_feature(&cpu->env, ARM_FEATURE_XSCALE); |
768 |
set_feature(&cpu->env, ARM_FEATURE_IWMMXT); |
769 |
cpu->midr = 0x69054111;
|
770 |
cpu->ctr = 0xd172172;
|
771 |
cpu->reset_sctlr = 0x00000078;
|
772 |
} |
773 |
|
774 |
static void pxa270b0_initfn(Object *obj) |
775 |
{ |
776 |
ARMCPU *cpu = ARM_CPU(obj); |
777 |
set_feature(&cpu->env, ARM_FEATURE_V5); |
778 |
set_feature(&cpu->env, ARM_FEATURE_XSCALE); |
779 |
set_feature(&cpu->env, ARM_FEATURE_IWMMXT); |
780 |
cpu->midr = 0x69054112;
|
781 |
cpu->ctr = 0xd172172;
|
782 |
cpu->reset_sctlr = 0x00000078;
|
783 |
} |
784 |
|
785 |
static void pxa270b1_initfn(Object *obj) |
786 |
{ |
787 |
ARMCPU *cpu = ARM_CPU(obj); |
788 |
set_feature(&cpu->env, ARM_FEATURE_V5); |
789 |
set_feature(&cpu->env, ARM_FEATURE_XSCALE); |
790 |
set_feature(&cpu->env, ARM_FEATURE_IWMMXT); |
791 |
cpu->midr = 0x69054113;
|
792 |
cpu->ctr = 0xd172172;
|
793 |
cpu->reset_sctlr = 0x00000078;
|
794 |
} |
795 |
|
796 |
static void pxa270c0_initfn(Object *obj) |
797 |
{ |
798 |
ARMCPU *cpu = ARM_CPU(obj); |
799 |
set_feature(&cpu->env, ARM_FEATURE_V5); |
800 |
set_feature(&cpu->env, ARM_FEATURE_XSCALE); |
801 |
set_feature(&cpu->env, ARM_FEATURE_IWMMXT); |
802 |
cpu->midr = 0x69054114;
|
803 |
cpu->ctr = 0xd172172;
|
804 |
cpu->reset_sctlr = 0x00000078;
|
805 |
} |
806 |
|
807 |
static void pxa270c5_initfn(Object *obj) |
808 |
{ |
809 |
ARMCPU *cpu = ARM_CPU(obj); |
810 |
set_feature(&cpu->env, ARM_FEATURE_V5); |
811 |
set_feature(&cpu->env, ARM_FEATURE_XSCALE); |
812 |
set_feature(&cpu->env, ARM_FEATURE_IWMMXT); |
813 |
cpu->midr = 0x69054117;
|
814 |
cpu->ctr = 0xd172172;
|
815 |
cpu->reset_sctlr = 0x00000078;
|
816 |
} |
817 |
|
818 |
static void arm_any_initfn(Object *obj) |
819 |
{ |
820 |
ARMCPU *cpu = ARM_CPU(obj); |
821 |
set_feature(&cpu->env, ARM_FEATURE_V8); |
822 |
set_feature(&cpu->env, ARM_FEATURE_VFP4); |
823 |
set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); |
824 |
set_feature(&cpu->env, ARM_FEATURE_NEON); |
825 |
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); |
826 |
set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); |
827 |
set_feature(&cpu->env, ARM_FEATURE_V7MP); |
828 |
cpu->midr = 0xffffffff;
|
829 |
} |
830 |
|
831 |
typedef struct ARMCPUInfo { |
832 |
const char *name; |
833 |
void (*initfn)(Object *obj);
|
834 |
void (*class_init)(ObjectClass *oc, void *data); |
835 |
} ARMCPUInfo; |
836 |
|
837 |
static const ARMCPUInfo arm_cpus[] = { |
838 |
{ .name = "arm926", .initfn = arm926_initfn },
|
839 |
{ .name = "arm946", .initfn = arm946_initfn },
|
840 |
{ .name = "arm1026", .initfn = arm1026_initfn },
|
841 |
/* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
|
842 |
* older core than plain "arm1136". In particular this does not
|
843 |
* have the v6K features.
|
844 |
*/
|
845 |
{ .name = "arm1136-r2", .initfn = arm1136_r2_initfn },
|
846 |
{ .name = "arm1136", .initfn = arm1136_initfn },
|
847 |
{ .name = "arm1176", .initfn = arm1176_initfn },
|
848 |
{ .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
|
849 |
{ .name = "cortex-m3", .initfn = cortex_m3_initfn,
|
850 |
.class_init = arm_v7m_class_init }, |
851 |
{ .name = "cortex-a8", .initfn = cortex_a8_initfn },
|
852 |
{ .name = "cortex-a9", .initfn = cortex_a9_initfn },
|
853 |
{ .name = "cortex-a15", .initfn = cortex_a15_initfn },
|
854 |
{ .name = "ti925t", .initfn = ti925t_initfn },
|
855 |
{ .name = "sa1100", .initfn = sa1100_initfn },
|
856 |
{ .name = "sa1110", .initfn = sa1110_initfn },
|
857 |
{ .name = "pxa250", .initfn = pxa250_initfn },
|
858 |
{ .name = "pxa255", .initfn = pxa255_initfn },
|
859 |
{ .name = "pxa260", .initfn = pxa260_initfn },
|
860 |
{ .name = "pxa261", .initfn = pxa261_initfn },
|
861 |
{ .name = "pxa262", .initfn = pxa262_initfn },
|
862 |
/* "pxa270" is an alias for "pxa270-a0" */
|
863 |
{ .name = "pxa270", .initfn = pxa270a0_initfn },
|
864 |
{ .name = "pxa270-a0", .initfn = pxa270a0_initfn },
|
865 |
{ .name = "pxa270-a1", .initfn = pxa270a1_initfn },
|
866 |
{ .name = "pxa270-b0", .initfn = pxa270b0_initfn },
|
867 |
{ .name = "pxa270-b1", .initfn = pxa270b1_initfn },
|
868 |
{ .name = "pxa270-c0", .initfn = pxa270c0_initfn },
|
869 |
{ .name = "pxa270-c5", .initfn = pxa270c5_initfn },
|
870 |
{ .name = "any", .initfn = arm_any_initfn },
|
871 |
}; |
872 |
|
873 |
static void arm_cpu_class_init(ObjectClass *oc, void *data) |
874 |
{ |
875 |
ARMCPUClass *acc = ARM_CPU_CLASS(oc); |
876 |
CPUClass *cc = CPU_CLASS(acc); |
877 |
DeviceClass *dc = DEVICE_CLASS(oc); |
878 |
|
879 |
acc->parent_realize = dc->realize; |
880 |
dc->realize = arm_cpu_realizefn; |
881 |
|
882 |
acc->parent_reset = cc->reset; |
883 |
cc->reset = arm_cpu_reset; |
884 |
|
885 |
cc->class_by_name = arm_cpu_class_by_name; |
886 |
cc->do_interrupt = arm_cpu_do_interrupt; |
887 |
cc->dump_state = arm_cpu_dump_state; |
888 |
cc->set_pc = arm_cpu_set_pc; |
889 |
cc->gdb_read_register = arm_cpu_gdb_read_register; |
890 |
cc->gdb_write_register = arm_cpu_gdb_write_register; |
891 |
#ifndef CONFIG_USER_ONLY
|
892 |
cc->get_phys_page_debug = arm_cpu_get_phys_page_debug; |
893 |
cc->vmsd = &vmstate_arm_cpu; |
894 |
#endif
|
895 |
cc->gdb_num_core_regs = 26;
|
896 |
cc->gdb_core_xml_file = "arm-core.xml";
|
897 |
} |
898 |
|
899 |
static void cpu_register(const ARMCPUInfo *info) |
900 |
{ |
901 |
TypeInfo type_info = { |
902 |
.parent = TYPE_ARM_CPU, |
903 |
.instance_size = sizeof(ARMCPU),
|
904 |
.instance_init = info->initfn, |
905 |
.class_size = sizeof(ARMCPUClass),
|
906 |
.class_init = info->class_init, |
907 |
}; |
908 |
|
909 |
type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
|
910 |
type_register(&type_info); |
911 |
g_free((void *)type_info.name);
|
912 |
} |
913 |
|
914 |
static const TypeInfo arm_cpu_type_info = { |
915 |
.name = TYPE_ARM_CPU, |
916 |
.parent = TYPE_CPU, |
917 |
.instance_size = sizeof(ARMCPU),
|
918 |
.instance_init = arm_cpu_initfn, |
919 |
.instance_finalize = arm_cpu_finalizefn, |
920 |
.abstract = true,
|
921 |
.class_size = sizeof(ARMCPUClass),
|
922 |
.class_init = arm_cpu_class_init, |
923 |
}; |
924 |
|
925 |
static void arm_cpu_register_types(void) |
926 |
{ |
927 |
int i;
|
928 |
|
929 |
type_register_static(&arm_cpu_type_info); |
930 |
for (i = 0; i < ARRAY_SIZE(arm_cpus); i++) { |
931 |
cpu_register(&arm_cpus[i]); |
932 |
} |
933 |
} |
934 |
|
935 |
type_init(arm_cpu_register_types) |