root / hw / usb / hcd-uhci.c @ 7c2eaca4
History | View | Annotate | Download (38.2 kB)
1 |
/*
|
---|---|
2 |
* USB UHCI controller emulation
|
3 |
*
|
4 |
* Copyright (c) 2005 Fabrice Bellard
|
5 |
*
|
6 |
* Copyright (c) 2008 Max Krasnyansky
|
7 |
* Magor rewrite of the UHCI data structures parser and frame processor
|
8 |
* Support for fully async operation and multiple outstanding transactions
|
9 |
*
|
10 |
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
11 |
* of this software and associated documentation files (the "Software"), to deal
|
12 |
* in the Software without restriction, including without limitation the rights
|
13 |
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
14 |
* copies of the Software, and to permit persons to whom the Software is
|
15 |
* furnished to do so, subject to the following conditions:
|
16 |
*
|
17 |
* The above copyright notice and this permission notice shall be included in
|
18 |
* all copies or substantial portions of the Software.
|
19 |
*
|
20 |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
21 |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
22 |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
23 |
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
24 |
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
25 |
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
26 |
* THE SOFTWARE.
|
27 |
*/
|
28 |
#include "hw/hw.h" |
29 |
#include "hw/usb.h" |
30 |
#include "hw/pci.h" |
31 |
#include "qemu-timer.h" |
32 |
#include "iov.h" |
33 |
#include "dma.h" |
34 |
#include "trace.h" |
35 |
|
36 |
//#define DEBUG
|
37 |
//#define DEBUG_DUMP_DATA
|
38 |
|
39 |
#define UHCI_CMD_FGR (1 << 4) |
40 |
#define UHCI_CMD_EGSM (1 << 3) |
41 |
#define UHCI_CMD_GRESET (1 << 2) |
42 |
#define UHCI_CMD_HCRESET (1 << 1) |
43 |
#define UHCI_CMD_RS (1 << 0) |
44 |
|
45 |
#define UHCI_STS_HCHALTED (1 << 5) |
46 |
#define UHCI_STS_HCPERR (1 << 4) |
47 |
#define UHCI_STS_HSERR (1 << 3) |
48 |
#define UHCI_STS_RD (1 << 2) |
49 |
#define UHCI_STS_USBERR (1 << 1) |
50 |
#define UHCI_STS_USBINT (1 << 0) |
51 |
|
52 |
#define TD_CTRL_SPD (1 << 29) |
53 |
#define TD_CTRL_ERROR_SHIFT 27 |
54 |
#define TD_CTRL_IOS (1 << 25) |
55 |
#define TD_CTRL_IOC (1 << 24) |
56 |
#define TD_CTRL_ACTIVE (1 << 23) |
57 |
#define TD_CTRL_STALL (1 << 22) |
58 |
#define TD_CTRL_BABBLE (1 << 20) |
59 |
#define TD_CTRL_NAK (1 << 19) |
60 |
#define TD_CTRL_TIMEOUT (1 << 18) |
61 |
|
62 |
#define UHCI_PORT_SUSPEND (1 << 12) |
63 |
#define UHCI_PORT_RESET (1 << 9) |
64 |
#define UHCI_PORT_LSDA (1 << 8) |
65 |
#define UHCI_PORT_RD (1 << 6) |
66 |
#define UHCI_PORT_ENC (1 << 3) |
67 |
#define UHCI_PORT_EN (1 << 2) |
68 |
#define UHCI_PORT_CSC (1 << 1) |
69 |
#define UHCI_PORT_CCS (1 << 0) |
70 |
|
71 |
#define UHCI_PORT_READ_ONLY (0x1bb) |
72 |
#define UHCI_PORT_WRITE_CLEAR (UHCI_PORT_CSC | UHCI_PORT_ENC)
|
73 |
|
74 |
#define FRAME_TIMER_FREQ 1000 |
75 |
|
76 |
#define FRAME_MAX_LOOPS 256 |
77 |
|
78 |
#define NB_PORTS 2 |
79 |
|
80 |
enum {
|
81 |
TD_RESULT_STOP_FRAME = 10,
|
82 |
TD_RESULT_COMPLETE, |
83 |
TD_RESULT_NEXT_QH, |
84 |
TD_RESULT_ASYNC_START, |
85 |
TD_RESULT_ASYNC_CONT, |
86 |
}; |
87 |
|
88 |
typedef struct UHCIState UHCIState; |
89 |
typedef struct UHCIAsync UHCIAsync; |
90 |
typedef struct UHCIQueue UHCIQueue; |
91 |
|
92 |
/*
|
93 |
* Pending async transaction.
|
94 |
* 'packet' must be the first field because completion
|
95 |
* handler does "(UHCIAsync *) pkt" cast.
|
96 |
*/
|
97 |
|
98 |
struct UHCIAsync {
|
99 |
USBPacket packet; |
100 |
QEMUSGList sgl; |
101 |
UHCIQueue *queue; |
102 |
QTAILQ_ENTRY(UHCIAsync) next; |
103 |
uint32_t td; |
104 |
uint8_t isoc; |
105 |
uint8_t done; |
106 |
}; |
107 |
|
108 |
struct UHCIQueue {
|
109 |
uint32_t token; |
110 |
UHCIState *uhci; |
111 |
QTAILQ_ENTRY(UHCIQueue) next; |
112 |
QTAILQ_HEAD(, UHCIAsync) asyncs; |
113 |
int8_t valid; |
114 |
}; |
115 |
|
116 |
typedef struct UHCIPort { |
117 |
USBPort port; |
118 |
uint16_t ctrl; |
119 |
} UHCIPort; |
120 |
|
121 |
struct UHCIState {
|
122 |
PCIDevice dev; |
123 |
MemoryRegion io_bar; |
124 |
USBBus bus; /* Note unused when we're a companion controller */
|
125 |
uint16_t cmd; /* cmd register */
|
126 |
uint16_t status; |
127 |
uint16_t intr; /* interrupt enable register */
|
128 |
uint16_t frnum; /* frame number */
|
129 |
uint32_t fl_base_addr; /* frame list base address */
|
130 |
uint8_t sof_timing; |
131 |
uint8_t status2; /* bit 0 and 1 are used to generate UHCI_STS_USBINT */
|
132 |
int64_t expire_time; |
133 |
QEMUTimer *frame_timer; |
134 |
QEMUBH *bh; |
135 |
uint32_t frame_bytes; |
136 |
uint32_t frame_bandwidth; |
137 |
UHCIPort ports[NB_PORTS]; |
138 |
|
139 |
/* Interrupts that should be raised at the end of the current frame. */
|
140 |
uint32_t pending_int_mask; |
141 |
int irq_pin;
|
142 |
|
143 |
/* Active packets */
|
144 |
QTAILQ_HEAD(, UHCIQueue) queues; |
145 |
uint8_t num_ports_vmstate; |
146 |
|
147 |
/* Properties */
|
148 |
char *masterbus;
|
149 |
uint32_t firstport; |
150 |
}; |
151 |
|
152 |
typedef struct UHCI_TD { |
153 |
uint32_t link; |
154 |
uint32_t ctrl; /* see TD_CTRL_xxx */
|
155 |
uint32_t token; |
156 |
uint32_t buffer; |
157 |
} UHCI_TD; |
158 |
|
159 |
typedef struct UHCI_QH { |
160 |
uint32_t link; |
161 |
uint32_t el_link; |
162 |
} UHCI_QH; |
163 |
|
164 |
static inline int32_t uhci_queue_token(UHCI_TD *td) |
165 |
{ |
166 |
/* covers ep, dev, pid -> identifies the endpoint */
|
167 |
return td->token & 0x7ffff; |
168 |
} |
169 |
|
170 |
static UHCIQueue *uhci_queue_get(UHCIState *s, UHCI_TD *td)
|
171 |
{ |
172 |
uint32_t token = uhci_queue_token(td); |
173 |
UHCIQueue *queue; |
174 |
|
175 |
QTAILQ_FOREACH(queue, &s->queues, next) { |
176 |
if (queue->token == token) {
|
177 |
return queue;
|
178 |
} |
179 |
} |
180 |
|
181 |
queue = g_new0(UHCIQueue, 1);
|
182 |
queue->uhci = s; |
183 |
queue->token = token; |
184 |
QTAILQ_INIT(&queue->asyncs); |
185 |
QTAILQ_INSERT_HEAD(&s->queues, queue, next); |
186 |
trace_usb_uhci_queue_add(queue->token); |
187 |
return queue;
|
188 |
} |
189 |
|
190 |
static void uhci_queue_free(UHCIQueue *queue) |
191 |
{ |
192 |
UHCIState *s = queue->uhci; |
193 |
|
194 |
trace_usb_uhci_queue_del(queue->token); |
195 |
QTAILQ_REMOVE(&s->queues, queue, next); |
196 |
g_free(queue); |
197 |
} |
198 |
|
199 |
static UHCIAsync *uhci_async_alloc(UHCIQueue *queue, uint32_t addr)
|
200 |
{ |
201 |
UHCIAsync *async = g_new0(UHCIAsync, 1);
|
202 |
|
203 |
async->queue = queue; |
204 |
async->td = addr; |
205 |
usb_packet_init(&async->packet); |
206 |
pci_dma_sglist_init(&async->sgl, &queue->uhci->dev, 1);
|
207 |
trace_usb_uhci_packet_add(async->queue->token, async->td); |
208 |
|
209 |
return async;
|
210 |
} |
211 |
|
212 |
static void uhci_async_free(UHCIAsync *async) |
213 |
{ |
214 |
trace_usb_uhci_packet_del(async->queue->token, async->td); |
215 |
usb_packet_cleanup(&async->packet); |
216 |
qemu_sglist_destroy(&async->sgl); |
217 |
g_free(async); |
218 |
} |
219 |
|
220 |
static void uhci_async_link(UHCIAsync *async) |
221 |
{ |
222 |
UHCIQueue *queue = async->queue; |
223 |
QTAILQ_INSERT_TAIL(&queue->asyncs, async, next); |
224 |
trace_usb_uhci_packet_link_async(async->queue->token, async->td); |
225 |
} |
226 |
|
227 |
static void uhci_async_unlink(UHCIAsync *async) |
228 |
{ |
229 |
UHCIQueue *queue = async->queue; |
230 |
QTAILQ_REMOVE(&queue->asyncs, async, next); |
231 |
trace_usb_uhci_packet_unlink_async(async->queue->token, async->td); |
232 |
} |
233 |
|
234 |
static void uhci_async_cancel(UHCIAsync *async) |
235 |
{ |
236 |
trace_usb_uhci_packet_cancel(async->queue->token, async->td, async->done); |
237 |
if (!async->done)
|
238 |
usb_cancel_packet(&async->packet); |
239 |
usb_packet_unmap(&async->packet, &async->sgl); |
240 |
uhci_async_free(async); |
241 |
} |
242 |
|
243 |
/*
|
244 |
* Mark all outstanding async packets as invalid.
|
245 |
* This is used for canceling them when TDs are removed by the HCD.
|
246 |
*/
|
247 |
static void uhci_async_validate_begin(UHCIState *s) |
248 |
{ |
249 |
UHCIQueue *queue; |
250 |
|
251 |
QTAILQ_FOREACH(queue, &s->queues, next) { |
252 |
queue->valid--; |
253 |
} |
254 |
} |
255 |
|
256 |
/*
|
257 |
* Cancel async packets that are no longer valid
|
258 |
*/
|
259 |
static void uhci_async_validate_end(UHCIState *s) |
260 |
{ |
261 |
UHCIQueue *queue, *n; |
262 |
UHCIAsync *async; |
263 |
|
264 |
QTAILQ_FOREACH_SAFE(queue, &s->queues, next, n) { |
265 |
if (queue->valid > 0) { |
266 |
continue;
|
267 |
} |
268 |
while (!QTAILQ_EMPTY(&queue->asyncs)) {
|
269 |
async = QTAILQ_FIRST(&queue->asyncs); |
270 |
uhci_async_unlink(async); |
271 |
uhci_async_cancel(async); |
272 |
} |
273 |
uhci_queue_free(queue); |
274 |
} |
275 |
} |
276 |
|
277 |
static void uhci_async_cancel_device(UHCIState *s, USBDevice *dev) |
278 |
{ |
279 |
UHCIQueue *queue; |
280 |
UHCIAsync *curr, *n; |
281 |
|
282 |
QTAILQ_FOREACH(queue, &s->queues, next) { |
283 |
QTAILQ_FOREACH_SAFE(curr, &queue->asyncs, next, n) { |
284 |
if (!usb_packet_is_inflight(&curr->packet) ||
|
285 |
curr->packet.ep->dev != dev) { |
286 |
continue;
|
287 |
} |
288 |
uhci_async_unlink(curr); |
289 |
uhci_async_cancel(curr); |
290 |
} |
291 |
} |
292 |
} |
293 |
|
294 |
static void uhci_async_cancel_all(UHCIState *s) |
295 |
{ |
296 |
UHCIQueue *queue, *nq; |
297 |
UHCIAsync *curr, *n; |
298 |
|
299 |
QTAILQ_FOREACH_SAFE(queue, &s->queues, next, nq) { |
300 |
QTAILQ_FOREACH_SAFE(curr, &queue->asyncs, next, n) { |
301 |
uhci_async_unlink(curr); |
302 |
uhci_async_cancel(curr); |
303 |
} |
304 |
uhci_queue_free(queue); |
305 |
} |
306 |
} |
307 |
|
308 |
static UHCIAsync *uhci_async_find_td(UHCIState *s, uint32_t addr, UHCI_TD *td)
|
309 |
{ |
310 |
uint32_t token = uhci_queue_token(td); |
311 |
UHCIQueue *queue; |
312 |
UHCIAsync *async; |
313 |
|
314 |
QTAILQ_FOREACH(queue, &s->queues, next) { |
315 |
if (queue->token == token) {
|
316 |
break;
|
317 |
} |
318 |
} |
319 |
if (queue == NULL) { |
320 |
return NULL; |
321 |
} |
322 |
|
323 |
QTAILQ_FOREACH(async, &queue->asyncs, next) { |
324 |
if (async->td == addr) {
|
325 |
return async;
|
326 |
} |
327 |
} |
328 |
|
329 |
return NULL; |
330 |
} |
331 |
|
332 |
static void uhci_update_irq(UHCIState *s) |
333 |
{ |
334 |
int level;
|
335 |
if (((s->status2 & 1) && (s->intr & (1 << 2))) || |
336 |
((s->status2 & 2) && (s->intr & (1 << 3))) || |
337 |
((s->status & UHCI_STS_USBERR) && (s->intr & (1 << 0))) || |
338 |
((s->status & UHCI_STS_RD) && (s->intr & (1 << 1))) || |
339 |
(s->status & UHCI_STS_HSERR) || |
340 |
(s->status & UHCI_STS_HCPERR)) { |
341 |
level = 1;
|
342 |
} else {
|
343 |
level = 0;
|
344 |
} |
345 |
qemu_set_irq(s->dev.irq[s->irq_pin], level); |
346 |
} |
347 |
|
348 |
static void uhci_reset(void *opaque) |
349 |
{ |
350 |
UHCIState *s = opaque; |
351 |
uint8_t *pci_conf; |
352 |
int i;
|
353 |
UHCIPort *port; |
354 |
|
355 |
trace_usb_uhci_reset(); |
356 |
|
357 |
pci_conf = s->dev.config; |
358 |
|
359 |
pci_conf[0x6a] = 0x01; /* usb clock */ |
360 |
pci_conf[0x6b] = 0x00; |
361 |
s->cmd = 0;
|
362 |
s->status = 0;
|
363 |
s->status2 = 0;
|
364 |
s->intr = 0;
|
365 |
s->fl_base_addr = 0;
|
366 |
s->sof_timing = 64;
|
367 |
|
368 |
for(i = 0; i < NB_PORTS; i++) { |
369 |
port = &s->ports[i]; |
370 |
port->ctrl = 0x0080;
|
371 |
if (port->port.dev && port->port.dev->attached) {
|
372 |
usb_port_reset(&port->port); |
373 |
} |
374 |
} |
375 |
|
376 |
uhci_async_cancel_all(s); |
377 |
qemu_bh_cancel(s->bh); |
378 |
uhci_update_irq(s); |
379 |
} |
380 |
|
381 |
static const VMStateDescription vmstate_uhci_port = { |
382 |
.name = "uhci port",
|
383 |
.version_id = 1,
|
384 |
.minimum_version_id = 1,
|
385 |
.minimum_version_id_old = 1,
|
386 |
.fields = (VMStateField []) { |
387 |
VMSTATE_UINT16(ctrl, UHCIPort), |
388 |
VMSTATE_END_OF_LIST() |
389 |
} |
390 |
}; |
391 |
|
392 |
static int uhci_post_load(void *opaque, int version_id) |
393 |
{ |
394 |
UHCIState *s = opaque; |
395 |
|
396 |
if (version_id < 2) { |
397 |
s->expire_time = qemu_get_clock_ns(vm_clock) + |
398 |
(get_ticks_per_sec() / FRAME_TIMER_FREQ); |
399 |
} |
400 |
return 0; |
401 |
} |
402 |
|
403 |
static const VMStateDescription vmstate_uhci = { |
404 |
.name = "uhci",
|
405 |
.version_id = 2,
|
406 |
.minimum_version_id = 1,
|
407 |
.minimum_version_id_old = 1,
|
408 |
.post_load = uhci_post_load, |
409 |
.fields = (VMStateField []) { |
410 |
VMSTATE_PCI_DEVICE(dev, UHCIState), |
411 |
VMSTATE_UINT8_EQUAL(num_ports_vmstate, UHCIState), |
412 |
VMSTATE_STRUCT_ARRAY(ports, UHCIState, NB_PORTS, 1,
|
413 |
vmstate_uhci_port, UHCIPort), |
414 |
VMSTATE_UINT16(cmd, UHCIState), |
415 |
VMSTATE_UINT16(status, UHCIState), |
416 |
VMSTATE_UINT16(intr, UHCIState), |
417 |
VMSTATE_UINT16(frnum, UHCIState), |
418 |
VMSTATE_UINT32(fl_base_addr, UHCIState), |
419 |
VMSTATE_UINT8(sof_timing, UHCIState), |
420 |
VMSTATE_UINT8(status2, UHCIState), |
421 |
VMSTATE_TIMER(frame_timer, UHCIState), |
422 |
VMSTATE_INT64_V(expire_time, UHCIState, 2),
|
423 |
VMSTATE_END_OF_LIST() |
424 |
} |
425 |
}; |
426 |
|
427 |
static void uhci_ioport_writeb(void *opaque, uint32_t addr, uint32_t val) |
428 |
{ |
429 |
UHCIState *s = opaque; |
430 |
|
431 |
addr &= 0x1f;
|
432 |
switch(addr) {
|
433 |
case 0x0c: |
434 |
s->sof_timing = val; |
435 |
break;
|
436 |
} |
437 |
} |
438 |
|
439 |
static uint32_t uhci_ioport_readb(void *opaque, uint32_t addr) |
440 |
{ |
441 |
UHCIState *s = opaque; |
442 |
uint32_t val; |
443 |
|
444 |
addr &= 0x1f;
|
445 |
switch(addr) {
|
446 |
case 0x0c: |
447 |
val = s->sof_timing; |
448 |
break;
|
449 |
default:
|
450 |
val = 0xff;
|
451 |
break;
|
452 |
} |
453 |
return val;
|
454 |
} |
455 |
|
456 |
static void uhci_ioport_writew(void *opaque, uint32_t addr, uint32_t val) |
457 |
{ |
458 |
UHCIState *s = opaque; |
459 |
|
460 |
addr &= 0x1f;
|
461 |
trace_usb_uhci_mmio_writew(addr, val); |
462 |
|
463 |
switch(addr) {
|
464 |
case 0x00: |
465 |
if ((val & UHCI_CMD_RS) && !(s->cmd & UHCI_CMD_RS)) {
|
466 |
/* start frame processing */
|
467 |
trace_usb_uhci_schedule_start(); |
468 |
s->expire_time = qemu_get_clock_ns(vm_clock) + |
469 |
(get_ticks_per_sec() / FRAME_TIMER_FREQ); |
470 |
qemu_mod_timer(s->frame_timer, qemu_get_clock_ns(vm_clock)); |
471 |
s->status &= ~UHCI_STS_HCHALTED; |
472 |
} else if (!(val & UHCI_CMD_RS)) { |
473 |
s->status |= UHCI_STS_HCHALTED; |
474 |
} |
475 |
if (val & UHCI_CMD_GRESET) {
|
476 |
UHCIPort *port; |
477 |
int i;
|
478 |
|
479 |
/* send reset on the USB bus */
|
480 |
for(i = 0; i < NB_PORTS; i++) { |
481 |
port = &s->ports[i]; |
482 |
usb_device_reset(port->port.dev); |
483 |
} |
484 |
uhci_reset(s); |
485 |
return;
|
486 |
} |
487 |
if (val & UHCI_CMD_HCRESET) {
|
488 |
uhci_reset(s); |
489 |
return;
|
490 |
} |
491 |
s->cmd = val; |
492 |
break;
|
493 |
case 0x02: |
494 |
s->status &= ~val; |
495 |
/* XXX: the chip spec is not coherent, so we add a hidden
|
496 |
register to distinguish between IOC and SPD */
|
497 |
if (val & UHCI_STS_USBINT)
|
498 |
s->status2 = 0;
|
499 |
uhci_update_irq(s); |
500 |
break;
|
501 |
case 0x04: |
502 |
s->intr = val; |
503 |
uhci_update_irq(s); |
504 |
break;
|
505 |
case 0x06: |
506 |
if (s->status & UHCI_STS_HCHALTED)
|
507 |
s->frnum = val & 0x7ff;
|
508 |
break;
|
509 |
case 0x10 ... 0x1f: |
510 |
{ |
511 |
UHCIPort *port; |
512 |
USBDevice *dev; |
513 |
int n;
|
514 |
|
515 |
n = (addr >> 1) & 7; |
516 |
if (n >= NB_PORTS)
|
517 |
return;
|
518 |
port = &s->ports[n]; |
519 |
dev = port->port.dev; |
520 |
if (dev && dev->attached) {
|
521 |
/* port reset */
|
522 |
if ( (val & UHCI_PORT_RESET) &&
|
523 |
!(port->ctrl & UHCI_PORT_RESET) ) { |
524 |
usb_device_reset(dev); |
525 |
} |
526 |
} |
527 |
port->ctrl &= UHCI_PORT_READ_ONLY; |
528 |
port->ctrl |= (val & ~UHCI_PORT_READ_ONLY); |
529 |
/* some bits are reset when a '1' is written to them */
|
530 |
port->ctrl &= ~(val & UHCI_PORT_WRITE_CLEAR); |
531 |
} |
532 |
break;
|
533 |
} |
534 |
} |
535 |
|
536 |
static uint32_t uhci_ioport_readw(void *opaque, uint32_t addr) |
537 |
{ |
538 |
UHCIState *s = opaque; |
539 |
uint32_t val; |
540 |
|
541 |
addr &= 0x1f;
|
542 |
switch(addr) {
|
543 |
case 0x00: |
544 |
val = s->cmd; |
545 |
break;
|
546 |
case 0x02: |
547 |
val = s->status; |
548 |
break;
|
549 |
case 0x04: |
550 |
val = s->intr; |
551 |
break;
|
552 |
case 0x06: |
553 |
val = s->frnum; |
554 |
break;
|
555 |
case 0x10 ... 0x1f: |
556 |
{ |
557 |
UHCIPort *port; |
558 |
int n;
|
559 |
n = (addr >> 1) & 7; |
560 |
if (n >= NB_PORTS)
|
561 |
goto read_default;
|
562 |
port = &s->ports[n]; |
563 |
val = port->ctrl; |
564 |
} |
565 |
break;
|
566 |
default:
|
567 |
read_default:
|
568 |
val = 0xff7f; /* disabled port */ |
569 |
break;
|
570 |
} |
571 |
|
572 |
trace_usb_uhci_mmio_readw(addr, val); |
573 |
|
574 |
return val;
|
575 |
} |
576 |
|
577 |
static void uhci_ioport_writel(void *opaque, uint32_t addr, uint32_t val) |
578 |
{ |
579 |
UHCIState *s = opaque; |
580 |
|
581 |
addr &= 0x1f;
|
582 |
trace_usb_uhci_mmio_writel(addr, val); |
583 |
|
584 |
switch(addr) {
|
585 |
case 0x08: |
586 |
s->fl_base_addr = val & ~0xfff;
|
587 |
break;
|
588 |
} |
589 |
} |
590 |
|
591 |
static uint32_t uhci_ioport_readl(void *opaque, uint32_t addr) |
592 |
{ |
593 |
UHCIState *s = opaque; |
594 |
uint32_t val; |
595 |
|
596 |
addr &= 0x1f;
|
597 |
switch(addr) {
|
598 |
case 0x08: |
599 |
val = s->fl_base_addr; |
600 |
break;
|
601 |
default:
|
602 |
val = 0xffffffff;
|
603 |
break;
|
604 |
} |
605 |
trace_usb_uhci_mmio_readl(addr, val); |
606 |
return val;
|
607 |
} |
608 |
|
609 |
/* signal resume if controller suspended */
|
610 |
static void uhci_resume (void *opaque) |
611 |
{ |
612 |
UHCIState *s = (UHCIState *)opaque; |
613 |
|
614 |
if (!s)
|
615 |
return;
|
616 |
|
617 |
if (s->cmd & UHCI_CMD_EGSM) {
|
618 |
s->cmd |= UHCI_CMD_FGR; |
619 |
s->status |= UHCI_STS_RD; |
620 |
uhci_update_irq(s); |
621 |
} |
622 |
} |
623 |
|
624 |
static void uhci_attach(USBPort *port1) |
625 |
{ |
626 |
UHCIState *s = port1->opaque; |
627 |
UHCIPort *port = &s->ports[port1->index]; |
628 |
|
629 |
/* set connect status */
|
630 |
port->ctrl |= UHCI_PORT_CCS | UHCI_PORT_CSC; |
631 |
|
632 |
/* update speed */
|
633 |
if (port->port.dev->speed == USB_SPEED_LOW) {
|
634 |
port->ctrl |= UHCI_PORT_LSDA; |
635 |
} else {
|
636 |
port->ctrl &= ~UHCI_PORT_LSDA; |
637 |
} |
638 |
|
639 |
uhci_resume(s); |
640 |
} |
641 |
|
642 |
static void uhci_detach(USBPort *port1) |
643 |
{ |
644 |
UHCIState *s = port1->opaque; |
645 |
UHCIPort *port = &s->ports[port1->index]; |
646 |
|
647 |
uhci_async_cancel_device(s, port1->dev); |
648 |
|
649 |
/* set connect status */
|
650 |
if (port->ctrl & UHCI_PORT_CCS) {
|
651 |
port->ctrl &= ~UHCI_PORT_CCS; |
652 |
port->ctrl |= UHCI_PORT_CSC; |
653 |
} |
654 |
/* disable port */
|
655 |
if (port->ctrl & UHCI_PORT_EN) {
|
656 |
port->ctrl &= ~UHCI_PORT_EN; |
657 |
port->ctrl |= UHCI_PORT_ENC; |
658 |
} |
659 |
|
660 |
uhci_resume(s); |
661 |
} |
662 |
|
663 |
static void uhci_child_detach(USBPort *port1, USBDevice *child) |
664 |
{ |
665 |
UHCIState *s = port1->opaque; |
666 |
|
667 |
uhci_async_cancel_device(s, child); |
668 |
} |
669 |
|
670 |
static void uhci_wakeup(USBPort *port1) |
671 |
{ |
672 |
UHCIState *s = port1->opaque; |
673 |
UHCIPort *port = &s->ports[port1->index]; |
674 |
|
675 |
if (port->ctrl & UHCI_PORT_SUSPEND && !(port->ctrl & UHCI_PORT_RD)) {
|
676 |
port->ctrl |= UHCI_PORT_RD; |
677 |
uhci_resume(s); |
678 |
} |
679 |
} |
680 |
|
681 |
static USBDevice *uhci_find_device(UHCIState *s, uint8_t addr)
|
682 |
{ |
683 |
USBDevice *dev; |
684 |
int i;
|
685 |
|
686 |
for (i = 0; i < NB_PORTS; i++) { |
687 |
UHCIPort *port = &s->ports[i]; |
688 |
if (!(port->ctrl & UHCI_PORT_EN)) {
|
689 |
continue;
|
690 |
} |
691 |
dev = usb_find_device(&port->port, addr); |
692 |
if (dev != NULL) { |
693 |
return dev;
|
694 |
} |
695 |
} |
696 |
return NULL; |
697 |
} |
698 |
|
699 |
static void uhci_async_complete(USBPort *port, USBPacket *packet); |
700 |
static void uhci_process_frame(UHCIState *s); |
701 |
|
702 |
/* return -1 if fatal error (frame must be stopped)
|
703 |
0 if TD successful
|
704 |
1 if TD unsuccessful or inactive
|
705 |
*/
|
706 |
static int uhci_complete_td(UHCIState *s, UHCI_TD *td, UHCIAsync *async, uint32_t *int_mask) |
707 |
{ |
708 |
int len = 0, max_len, err, ret; |
709 |
uint8_t pid; |
710 |
|
711 |
max_len = ((td->token >> 21) + 1) & 0x7ff; |
712 |
pid = td->token & 0xff;
|
713 |
|
714 |
ret = async->packet.result; |
715 |
|
716 |
if (td->ctrl & TD_CTRL_IOS)
|
717 |
td->ctrl &= ~TD_CTRL_ACTIVE; |
718 |
|
719 |
if (ret < 0) |
720 |
goto out;
|
721 |
|
722 |
len = async->packet.result; |
723 |
td->ctrl = (td->ctrl & ~0x7ff) | ((len - 1) & 0x7ff); |
724 |
|
725 |
/* The NAK bit may have been set by a previous frame, so clear it
|
726 |
here. The docs are somewhat unclear, but win2k relies on this
|
727 |
behavior. */
|
728 |
td->ctrl &= ~(TD_CTRL_ACTIVE | TD_CTRL_NAK); |
729 |
if (td->ctrl & TD_CTRL_IOC)
|
730 |
*int_mask |= 0x01;
|
731 |
|
732 |
if (pid == USB_TOKEN_IN) {
|
733 |
if ((td->ctrl & TD_CTRL_SPD) && len < max_len) {
|
734 |
*int_mask |= 0x02;
|
735 |
/* short packet: do not update QH */
|
736 |
trace_usb_uhci_packet_complete_shortxfer(async->queue->token, |
737 |
async->td); |
738 |
return TD_RESULT_NEXT_QH;
|
739 |
} |
740 |
} |
741 |
|
742 |
/* success */
|
743 |
trace_usb_uhci_packet_complete_success(async->queue->token, async->td); |
744 |
return TD_RESULT_COMPLETE;
|
745 |
|
746 |
out:
|
747 |
/*
|
748 |
* We should not do any further processing on a queue with errors!
|
749 |
* This is esp. important for bulk endpoints with pipelining enabled
|
750 |
* (redirection to a real USB device), where we must cancel all the
|
751 |
* transfers after this one so that:
|
752 |
* 1) If they've completed already, they are not processed further
|
753 |
* causing more stalls, originating from the same failed transfer
|
754 |
* 2) If still in flight, they are cancelled before the guest does
|
755 |
* a clear stall, otherwise the guest and device can loose sync!
|
756 |
*/
|
757 |
while (!QTAILQ_EMPTY(&async->queue->asyncs)) {
|
758 |
UHCIAsync *as = QTAILQ_FIRST(&async->queue->asyncs); |
759 |
uhci_async_unlink(as); |
760 |
uhci_async_cancel(as); |
761 |
} |
762 |
|
763 |
switch(ret) {
|
764 |
case USB_RET_STALL:
|
765 |
td->ctrl |= TD_CTRL_STALL; |
766 |
td->ctrl &= ~TD_CTRL_ACTIVE; |
767 |
s->status |= UHCI_STS_USBERR; |
768 |
if (td->ctrl & TD_CTRL_IOC) {
|
769 |
*int_mask |= 0x01;
|
770 |
} |
771 |
uhci_update_irq(s); |
772 |
trace_usb_uhci_packet_complete_stall(async->queue->token, async->td); |
773 |
return TD_RESULT_NEXT_QH;
|
774 |
|
775 |
case USB_RET_BABBLE:
|
776 |
td->ctrl |= TD_CTRL_BABBLE | TD_CTRL_STALL; |
777 |
td->ctrl &= ~TD_CTRL_ACTIVE; |
778 |
s->status |= UHCI_STS_USBERR; |
779 |
if (td->ctrl & TD_CTRL_IOC) {
|
780 |
*int_mask |= 0x01;
|
781 |
} |
782 |
uhci_update_irq(s); |
783 |
/* frame interrupted */
|
784 |
trace_usb_uhci_packet_complete_babble(async->queue->token, async->td); |
785 |
return TD_RESULT_STOP_FRAME;
|
786 |
|
787 |
case USB_RET_NAK:
|
788 |
td->ctrl |= TD_CTRL_NAK; |
789 |
if (pid == USB_TOKEN_SETUP)
|
790 |
break;
|
791 |
return TD_RESULT_NEXT_QH;
|
792 |
|
793 |
case USB_RET_IOERROR:
|
794 |
case USB_RET_NODEV:
|
795 |
default:
|
796 |
break;
|
797 |
} |
798 |
|
799 |
/* Retry the TD if error count is not zero */
|
800 |
|
801 |
td->ctrl |= TD_CTRL_TIMEOUT; |
802 |
err = (td->ctrl >> TD_CTRL_ERROR_SHIFT) & 3;
|
803 |
if (err != 0) { |
804 |
err--; |
805 |
if (err == 0) { |
806 |
td->ctrl &= ~TD_CTRL_ACTIVE; |
807 |
s->status |= UHCI_STS_USBERR; |
808 |
if (td->ctrl & TD_CTRL_IOC)
|
809 |
*int_mask |= 0x01;
|
810 |
uhci_update_irq(s); |
811 |
trace_usb_uhci_packet_complete_error(async->queue->token, |
812 |
async->td); |
813 |
} |
814 |
} |
815 |
td->ctrl = (td->ctrl & ~(3 << TD_CTRL_ERROR_SHIFT)) |
|
816 |
(err << TD_CTRL_ERROR_SHIFT); |
817 |
return TD_RESULT_NEXT_QH;
|
818 |
} |
819 |
|
820 |
static int uhci_handle_td(UHCIState *s, uint32_t addr, UHCI_TD *td, |
821 |
uint32_t *int_mask, bool queuing)
|
822 |
{ |
823 |
UHCIAsync *async; |
824 |
int len = 0, max_len; |
825 |
uint8_t pid; |
826 |
USBDevice *dev; |
827 |
USBEndpoint *ep; |
828 |
|
829 |
/* Is active ? */
|
830 |
if (!(td->ctrl & TD_CTRL_ACTIVE)) {
|
831 |
/*
|
832 |
* ehci11d spec page 22: "Even if the Active bit in the TD is already
|
833 |
* cleared when the TD is fetched ... an IOC interrupt is generated"
|
834 |
*/
|
835 |
if (td->ctrl & TD_CTRL_IOC) {
|
836 |
*int_mask |= 0x01;
|
837 |
} |
838 |
return TD_RESULT_NEXT_QH;
|
839 |
} |
840 |
|
841 |
async = uhci_async_find_td(s, addr, td); |
842 |
if (async) {
|
843 |
/* Already submitted */
|
844 |
async->queue->valid = 32;
|
845 |
|
846 |
if (!async->done)
|
847 |
return TD_RESULT_ASYNC_CONT;
|
848 |
if (queuing) {
|
849 |
/* we are busy filling the queue, we are not prepared
|
850 |
to consume completed packages then, just leave them
|
851 |
in async state */
|
852 |
return TD_RESULT_ASYNC_CONT;
|
853 |
} |
854 |
|
855 |
uhci_async_unlink(async); |
856 |
goto done;
|
857 |
} |
858 |
|
859 |
/* Allocate new packet */
|
860 |
async = uhci_async_alloc(uhci_queue_get(s, td), addr); |
861 |
|
862 |
/* valid needs to be large enough to handle 10 frame delay
|
863 |
* for initial isochronous requests
|
864 |
*/
|
865 |
async->queue->valid = 32;
|
866 |
async->isoc = td->ctrl & TD_CTRL_IOS; |
867 |
|
868 |
max_len = ((td->token >> 21) + 1) & 0x7ff; |
869 |
pid = td->token & 0xff;
|
870 |
|
871 |
dev = uhci_find_device(s, (td->token >> 8) & 0x7f); |
872 |
ep = usb_ep_get(dev, pid, (td->token >> 15) & 0xf); |
873 |
usb_packet_setup(&async->packet, pid, ep, addr); |
874 |
qemu_sglist_add(&async->sgl, td->buffer, max_len); |
875 |
usb_packet_map(&async->packet, &async->sgl); |
876 |
|
877 |
switch(pid) {
|
878 |
case USB_TOKEN_OUT:
|
879 |
case USB_TOKEN_SETUP:
|
880 |
len = usb_handle_packet(dev, &async->packet); |
881 |
if (len >= 0) |
882 |
len = max_len; |
883 |
break;
|
884 |
|
885 |
case USB_TOKEN_IN:
|
886 |
len = usb_handle_packet(dev, &async->packet); |
887 |
break;
|
888 |
|
889 |
default:
|
890 |
/* invalid pid : frame interrupted */
|
891 |
usb_packet_unmap(&async->packet, &async->sgl); |
892 |
uhci_async_free(async); |
893 |
s->status |= UHCI_STS_HCPERR; |
894 |
uhci_update_irq(s); |
895 |
return TD_RESULT_STOP_FRAME;
|
896 |
} |
897 |
|
898 |
if (len == USB_RET_ASYNC) {
|
899 |
uhci_async_link(async); |
900 |
return TD_RESULT_ASYNC_START;
|
901 |
} |
902 |
|
903 |
async->packet.result = len; |
904 |
|
905 |
done:
|
906 |
len = uhci_complete_td(s, td, async, int_mask); |
907 |
usb_packet_unmap(&async->packet, &async->sgl); |
908 |
uhci_async_free(async); |
909 |
return len;
|
910 |
} |
911 |
|
912 |
static void uhci_async_complete(USBPort *port, USBPacket *packet) |
913 |
{ |
914 |
UHCIAsync *async = container_of(packet, UHCIAsync, packet); |
915 |
UHCIState *s = async->queue->uhci; |
916 |
|
917 |
if (async->isoc) {
|
918 |
UHCI_TD td; |
919 |
uint32_t link = async->td; |
920 |
uint32_t int_mask = 0, val;
|
921 |
|
922 |
pci_dma_read(&s->dev, link & ~0xf, &td, sizeof(td)); |
923 |
le32_to_cpus(&td.link); |
924 |
le32_to_cpus(&td.ctrl); |
925 |
le32_to_cpus(&td.token); |
926 |
le32_to_cpus(&td.buffer); |
927 |
|
928 |
uhci_async_unlink(async); |
929 |
uhci_complete_td(s, &td, async, &int_mask); |
930 |
s->pending_int_mask |= int_mask; |
931 |
|
932 |
/* update the status bits of the TD */
|
933 |
val = cpu_to_le32(td.ctrl); |
934 |
pci_dma_write(&s->dev, (link & ~0xf) + 4, &val, sizeof(val)); |
935 |
uhci_async_free(async); |
936 |
} else {
|
937 |
async->done = 1;
|
938 |
if (s->frame_bytes < s->frame_bandwidth) {
|
939 |
qemu_bh_schedule(s->bh); |
940 |
} |
941 |
} |
942 |
} |
943 |
|
944 |
static int is_valid(uint32_t link) |
945 |
{ |
946 |
return (link & 1) == 0; |
947 |
} |
948 |
|
949 |
static int is_qh(uint32_t link) |
950 |
{ |
951 |
return (link & 2) != 0; |
952 |
} |
953 |
|
954 |
static int depth_first(uint32_t link) |
955 |
{ |
956 |
return (link & 4) != 0; |
957 |
} |
958 |
|
959 |
/* QH DB used for detecting QH loops */
|
960 |
#define UHCI_MAX_QUEUES 128 |
961 |
typedef struct { |
962 |
uint32_t addr[UHCI_MAX_QUEUES]; |
963 |
int count;
|
964 |
} QhDb; |
965 |
|
966 |
static void qhdb_reset(QhDb *db) |
967 |
{ |
968 |
db->count = 0;
|
969 |
} |
970 |
|
971 |
/* Add QH to DB. Returns 1 if already present or DB is full. */
|
972 |
static int qhdb_insert(QhDb *db, uint32_t addr) |
973 |
{ |
974 |
int i;
|
975 |
for (i = 0; i < db->count; i++) |
976 |
if (db->addr[i] == addr)
|
977 |
return 1; |
978 |
|
979 |
if (db->count >= UHCI_MAX_QUEUES)
|
980 |
return 1; |
981 |
|
982 |
db->addr[db->count++] = addr; |
983 |
return 0; |
984 |
} |
985 |
|
986 |
static void uhci_fill_queue(UHCIState *s, UHCI_TD *td) |
987 |
{ |
988 |
uint32_t int_mask = 0;
|
989 |
uint32_t plink = td->link; |
990 |
uint32_t token = uhci_queue_token(td); |
991 |
UHCI_TD ptd; |
992 |
int ret;
|
993 |
|
994 |
ptd.ctrl = td->ctrl; |
995 |
while (is_valid(plink) && !(ptd.ctrl & TD_CTRL_SPD)) {
|
996 |
pci_dma_read(&s->dev, plink & ~0xf, &ptd, sizeof(ptd)); |
997 |
le32_to_cpus(&ptd.link); |
998 |
le32_to_cpus(&ptd.ctrl); |
999 |
le32_to_cpus(&ptd.token); |
1000 |
le32_to_cpus(&ptd.buffer); |
1001 |
if (!(ptd.ctrl & TD_CTRL_ACTIVE)) {
|
1002 |
break;
|
1003 |
} |
1004 |
if (uhci_queue_token(&ptd) != token) {
|
1005 |
break;
|
1006 |
} |
1007 |
trace_usb_uhci_td_queue(plink & ~0xf, ptd.ctrl, ptd.token);
|
1008 |
ret = uhci_handle_td(s, plink, &ptd, &int_mask, true);
|
1009 |
if (ret == TD_RESULT_ASYNC_CONT) {
|
1010 |
break;
|
1011 |
} |
1012 |
assert(ret == TD_RESULT_ASYNC_START); |
1013 |
assert(int_mask == 0);
|
1014 |
plink = ptd.link; |
1015 |
} |
1016 |
} |
1017 |
|
1018 |
static void uhci_process_frame(UHCIState *s) |
1019 |
{ |
1020 |
uint32_t frame_addr, link, old_td_ctrl, val, int_mask; |
1021 |
uint32_t curr_qh, td_count = 0;
|
1022 |
int cnt, ret;
|
1023 |
UHCI_TD td; |
1024 |
UHCI_QH qh; |
1025 |
QhDb qhdb; |
1026 |
|
1027 |
frame_addr = s->fl_base_addr + ((s->frnum & 0x3ff) << 2); |
1028 |
|
1029 |
pci_dma_read(&s->dev, frame_addr, &link, 4);
|
1030 |
le32_to_cpus(&link); |
1031 |
|
1032 |
int_mask = 0;
|
1033 |
curr_qh = 0;
|
1034 |
|
1035 |
qhdb_reset(&qhdb); |
1036 |
|
1037 |
for (cnt = FRAME_MAX_LOOPS; is_valid(link) && cnt; cnt--) {
|
1038 |
if (s->frame_bytes >= s->frame_bandwidth) {
|
1039 |
/* We've reached the usb 1.1 bandwidth, which is
|
1040 |
1280 bytes/frame, stop processing */
|
1041 |
trace_usb_uhci_frame_stop_bandwidth(); |
1042 |
break;
|
1043 |
} |
1044 |
if (is_qh(link)) {
|
1045 |
/* QH */
|
1046 |
trace_usb_uhci_qh_load(link & ~0xf);
|
1047 |
|
1048 |
if (qhdb_insert(&qhdb, link)) {
|
1049 |
/*
|
1050 |
* We're going in circles. Which is not a bug because
|
1051 |
* HCD is allowed to do that as part of the BW management.
|
1052 |
*
|
1053 |
* Stop processing here if no transaction has been done
|
1054 |
* since we've been here last time.
|
1055 |
*/
|
1056 |
if (td_count == 0) { |
1057 |
trace_usb_uhci_frame_loop_stop_idle(); |
1058 |
break;
|
1059 |
} else {
|
1060 |
trace_usb_uhci_frame_loop_continue(); |
1061 |
td_count = 0;
|
1062 |
qhdb_reset(&qhdb); |
1063 |
qhdb_insert(&qhdb, link); |
1064 |
} |
1065 |
} |
1066 |
|
1067 |
pci_dma_read(&s->dev, link & ~0xf, &qh, sizeof(qh)); |
1068 |
le32_to_cpus(&qh.link); |
1069 |
le32_to_cpus(&qh.el_link); |
1070 |
|
1071 |
if (!is_valid(qh.el_link)) {
|
1072 |
/* QH w/o elements */
|
1073 |
curr_qh = 0;
|
1074 |
link = qh.link; |
1075 |
} else {
|
1076 |
/* QH with elements */
|
1077 |
curr_qh = link; |
1078 |
link = qh.el_link; |
1079 |
} |
1080 |
continue;
|
1081 |
} |
1082 |
|
1083 |
/* TD */
|
1084 |
pci_dma_read(&s->dev, link & ~0xf, &td, sizeof(td)); |
1085 |
le32_to_cpus(&td.link); |
1086 |
le32_to_cpus(&td.ctrl); |
1087 |
le32_to_cpus(&td.token); |
1088 |
le32_to_cpus(&td.buffer); |
1089 |
trace_usb_uhci_td_load(curr_qh & ~0xf, link & ~0xf, td.ctrl, td.token); |
1090 |
|
1091 |
old_td_ctrl = td.ctrl; |
1092 |
ret = uhci_handle_td(s, link, &td, &int_mask, false);
|
1093 |
if (old_td_ctrl != td.ctrl) {
|
1094 |
/* update the status bits of the TD */
|
1095 |
val = cpu_to_le32(td.ctrl); |
1096 |
pci_dma_write(&s->dev, (link & ~0xf) + 4, &val, sizeof(val)); |
1097 |
} |
1098 |
|
1099 |
switch (ret) {
|
1100 |
case TD_RESULT_STOP_FRAME: /* interrupted frame */ |
1101 |
goto out;
|
1102 |
|
1103 |
case TD_RESULT_NEXT_QH:
|
1104 |
case TD_RESULT_ASYNC_CONT:
|
1105 |
trace_usb_uhci_td_nextqh(curr_qh & ~0xf, link & ~0xf); |
1106 |
link = curr_qh ? qh.link : td.link; |
1107 |
continue;
|
1108 |
|
1109 |
case TD_RESULT_ASYNC_START:
|
1110 |
trace_usb_uhci_td_async(curr_qh & ~0xf, link & ~0xf); |
1111 |
uhci_fill_queue(s, &td); |
1112 |
link = curr_qh ? qh.link : td.link; |
1113 |
continue;
|
1114 |
|
1115 |
case TD_RESULT_COMPLETE:
|
1116 |
trace_usb_uhci_td_complete(curr_qh & ~0xf, link & ~0xf); |
1117 |
link = td.link; |
1118 |
td_count++; |
1119 |
s->frame_bytes += (td.ctrl & 0x7ff) + 1; |
1120 |
|
1121 |
if (curr_qh) {
|
1122 |
/* update QH element link */
|
1123 |
qh.el_link = link; |
1124 |
val = cpu_to_le32(qh.el_link); |
1125 |
pci_dma_write(&s->dev, (curr_qh & ~0xf) + 4, &val, sizeof(val)); |
1126 |
|
1127 |
if (!depth_first(link)) {
|
1128 |
/* done with this QH */
|
1129 |
curr_qh = 0;
|
1130 |
link = qh.link; |
1131 |
} |
1132 |
} |
1133 |
break;
|
1134 |
|
1135 |
default:
|
1136 |
assert(!"unknown return code");
|
1137 |
} |
1138 |
|
1139 |
/* go to the next entry */
|
1140 |
} |
1141 |
|
1142 |
out:
|
1143 |
s->pending_int_mask |= int_mask; |
1144 |
} |
1145 |
|
1146 |
static void uhci_bh(void *opaque) |
1147 |
{ |
1148 |
UHCIState *s = opaque; |
1149 |
uhci_process_frame(s); |
1150 |
} |
1151 |
|
1152 |
static void uhci_frame_timer(void *opaque) |
1153 |
{ |
1154 |
UHCIState *s = opaque; |
1155 |
|
1156 |
/* prepare the timer for the next frame */
|
1157 |
s->expire_time += (get_ticks_per_sec() / FRAME_TIMER_FREQ); |
1158 |
s->frame_bytes = 0;
|
1159 |
qemu_bh_cancel(s->bh); |
1160 |
|
1161 |
if (!(s->cmd & UHCI_CMD_RS)) {
|
1162 |
/* Full stop */
|
1163 |
trace_usb_uhci_schedule_stop(); |
1164 |
qemu_del_timer(s->frame_timer); |
1165 |
uhci_async_cancel_all(s); |
1166 |
/* set hchalted bit in status - UHCI11D 2.1.2 */
|
1167 |
s->status |= UHCI_STS_HCHALTED; |
1168 |
return;
|
1169 |
} |
1170 |
|
1171 |
/* Complete the previous frame */
|
1172 |
if (s->pending_int_mask) {
|
1173 |
s->status2 |= s->pending_int_mask; |
1174 |
s->status |= UHCI_STS_USBINT; |
1175 |
uhci_update_irq(s); |
1176 |
} |
1177 |
s->pending_int_mask = 0;
|
1178 |
|
1179 |
/* Start new frame */
|
1180 |
s->frnum = (s->frnum + 1) & 0x7ff; |
1181 |
|
1182 |
trace_usb_uhci_frame_start(s->frnum); |
1183 |
|
1184 |
uhci_async_validate_begin(s); |
1185 |
|
1186 |
uhci_process_frame(s); |
1187 |
|
1188 |
uhci_async_validate_end(s); |
1189 |
|
1190 |
qemu_mod_timer(s->frame_timer, s->expire_time); |
1191 |
} |
1192 |
|
1193 |
static const MemoryRegionPortio uhci_portio[] = { |
1194 |
{ 0, 32, 2, .write = uhci_ioport_writew, }, |
1195 |
{ 0, 32, 2, .read = uhci_ioport_readw, }, |
1196 |
{ 0, 32, 4, .write = uhci_ioport_writel, }, |
1197 |
{ 0, 32, 4, .read = uhci_ioport_readl, }, |
1198 |
{ 0, 32, 1, .write = uhci_ioport_writeb, }, |
1199 |
{ 0, 32, 1, .read = uhci_ioport_readb, }, |
1200 |
PORTIO_END_OF_LIST() |
1201 |
}; |
1202 |
|
1203 |
static const MemoryRegionOps uhci_ioport_ops = { |
1204 |
.old_portio = uhci_portio, |
1205 |
}; |
1206 |
|
1207 |
static USBPortOps uhci_port_ops = {
|
1208 |
.attach = uhci_attach, |
1209 |
.detach = uhci_detach, |
1210 |
.child_detach = uhci_child_detach, |
1211 |
.wakeup = uhci_wakeup, |
1212 |
.complete = uhci_async_complete, |
1213 |
}; |
1214 |
|
1215 |
static USBBusOps uhci_bus_ops = {
|
1216 |
}; |
1217 |
|
1218 |
static int usb_uhci_common_initfn(PCIDevice *dev) |
1219 |
{ |
1220 |
PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); |
1221 |
UHCIState *s = DO_UPCAST(UHCIState, dev, dev); |
1222 |
uint8_t *pci_conf = s->dev.config; |
1223 |
int i;
|
1224 |
|
1225 |
pci_conf[PCI_CLASS_PROG] = 0x00;
|
1226 |
/* TODO: reset value should be 0. */
|
1227 |
pci_conf[USB_SBRN] = USB_RELEASE_1; // release number
|
1228 |
|
1229 |
switch (pc->device_id) {
|
1230 |
case PCI_DEVICE_ID_INTEL_82801I_UHCI1:
|
1231 |
s->irq_pin = 0; /* A */ |
1232 |
break;
|
1233 |
case PCI_DEVICE_ID_INTEL_82801I_UHCI2:
|
1234 |
s->irq_pin = 1; /* B */ |
1235 |
break;
|
1236 |
case PCI_DEVICE_ID_INTEL_82801I_UHCI3:
|
1237 |
s->irq_pin = 2; /* C */ |
1238 |
break;
|
1239 |
default:
|
1240 |
s->irq_pin = 3; /* D */ |
1241 |
break;
|
1242 |
} |
1243 |
pci_config_set_interrupt_pin(pci_conf, s->irq_pin + 1);
|
1244 |
|
1245 |
if (s->masterbus) {
|
1246 |
USBPort *ports[NB_PORTS]; |
1247 |
for(i = 0; i < NB_PORTS; i++) { |
1248 |
ports[i] = &s->ports[i].port; |
1249 |
} |
1250 |
if (usb_register_companion(s->masterbus, ports, NB_PORTS,
|
1251 |
s->firstport, s, &uhci_port_ops, |
1252 |
USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL) != 0) {
|
1253 |
return -1; |
1254 |
} |
1255 |
} else {
|
1256 |
usb_bus_new(&s->bus, &uhci_bus_ops, &s->dev.qdev); |
1257 |
for (i = 0; i < NB_PORTS; i++) { |
1258 |
usb_register_port(&s->bus, &s->ports[i].port, s, i, &uhci_port_ops, |
1259 |
USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL); |
1260 |
} |
1261 |
} |
1262 |
s->bh = qemu_bh_new(uhci_bh, s); |
1263 |
s->frame_timer = qemu_new_timer_ns(vm_clock, uhci_frame_timer, s); |
1264 |
s->num_ports_vmstate = NB_PORTS; |
1265 |
QTAILQ_INIT(&s->queues); |
1266 |
|
1267 |
qemu_register_reset(uhci_reset, s); |
1268 |
|
1269 |
memory_region_init_io(&s->io_bar, &uhci_ioport_ops, s, "uhci", 0x20); |
1270 |
/* Use region 4 for consistency with real hardware. BSD guests seem
|
1271 |
to rely on this. */
|
1272 |
pci_register_bar(&s->dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar);
|
1273 |
|
1274 |
return 0; |
1275 |
} |
1276 |
|
1277 |
static int usb_uhci_vt82c686b_initfn(PCIDevice *dev) |
1278 |
{ |
1279 |
UHCIState *s = DO_UPCAST(UHCIState, dev, dev); |
1280 |
uint8_t *pci_conf = s->dev.config; |
1281 |
|
1282 |
/* USB misc control 1/2 */
|
1283 |
pci_set_long(pci_conf + 0x40,0x00001000); |
1284 |
/* PM capability */
|
1285 |
pci_set_long(pci_conf + 0x80,0x00020001); |
1286 |
/* USB legacy support */
|
1287 |
pci_set_long(pci_conf + 0xc0,0x00002000); |
1288 |
|
1289 |
return usb_uhci_common_initfn(dev);
|
1290 |
} |
1291 |
|
1292 |
static void usb_uhci_exit(PCIDevice *dev) |
1293 |
{ |
1294 |
UHCIState *s = DO_UPCAST(UHCIState, dev, dev); |
1295 |
|
1296 |
memory_region_destroy(&s->io_bar); |
1297 |
} |
1298 |
|
1299 |
static Property uhci_properties[] = {
|
1300 |
DEFINE_PROP_STRING("masterbus", UHCIState, masterbus),
|
1301 |
DEFINE_PROP_UINT32("firstport", UHCIState, firstport, 0), |
1302 |
DEFINE_PROP_UINT32("bandwidth", UHCIState, frame_bandwidth, 1280), |
1303 |
DEFINE_PROP_END_OF_LIST(), |
1304 |
}; |
1305 |
|
1306 |
static void piix3_uhci_class_init(ObjectClass *klass, void *data) |
1307 |
{ |
1308 |
DeviceClass *dc = DEVICE_CLASS(klass); |
1309 |
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
1310 |
|
1311 |
k->init = usb_uhci_common_initfn; |
1312 |
k->exit = usb_uhci_exit; |
1313 |
k->vendor_id = PCI_VENDOR_ID_INTEL; |
1314 |
k->device_id = PCI_DEVICE_ID_INTEL_82371SB_2; |
1315 |
k->revision = 0x01;
|
1316 |
k->class_id = PCI_CLASS_SERIAL_USB; |
1317 |
dc->vmsd = &vmstate_uhci; |
1318 |
dc->props = uhci_properties; |
1319 |
} |
1320 |
|
1321 |
static TypeInfo piix3_uhci_info = {
|
1322 |
.name = "piix3-usb-uhci",
|
1323 |
.parent = TYPE_PCI_DEVICE, |
1324 |
.instance_size = sizeof(UHCIState),
|
1325 |
.class_init = piix3_uhci_class_init, |
1326 |
}; |
1327 |
|
1328 |
static void piix4_uhci_class_init(ObjectClass *klass, void *data) |
1329 |
{ |
1330 |
DeviceClass *dc = DEVICE_CLASS(klass); |
1331 |
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
1332 |
|
1333 |
k->init = usb_uhci_common_initfn; |
1334 |
k->exit = usb_uhci_exit; |
1335 |
k->vendor_id = PCI_VENDOR_ID_INTEL; |
1336 |
k->device_id = PCI_DEVICE_ID_INTEL_82371AB_2; |
1337 |
k->revision = 0x01;
|
1338 |
k->class_id = PCI_CLASS_SERIAL_USB; |
1339 |
dc->vmsd = &vmstate_uhci; |
1340 |
dc->props = uhci_properties; |
1341 |
} |
1342 |
|
1343 |
static TypeInfo piix4_uhci_info = {
|
1344 |
.name = "piix4-usb-uhci",
|
1345 |
.parent = TYPE_PCI_DEVICE, |
1346 |
.instance_size = sizeof(UHCIState),
|
1347 |
.class_init = piix4_uhci_class_init, |
1348 |
}; |
1349 |
|
1350 |
static void vt82c686b_uhci_class_init(ObjectClass *klass, void *data) |
1351 |
{ |
1352 |
DeviceClass *dc = DEVICE_CLASS(klass); |
1353 |
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
1354 |
|
1355 |
k->init = usb_uhci_vt82c686b_initfn; |
1356 |
k->exit = usb_uhci_exit; |
1357 |
k->vendor_id = PCI_VENDOR_ID_VIA; |
1358 |
k->device_id = PCI_DEVICE_ID_VIA_UHCI; |
1359 |
k->revision = 0x01;
|
1360 |
k->class_id = PCI_CLASS_SERIAL_USB; |
1361 |
dc->vmsd = &vmstate_uhci; |
1362 |
dc->props = uhci_properties; |
1363 |
} |
1364 |
|
1365 |
static TypeInfo vt82c686b_uhci_info = {
|
1366 |
.name = "vt82c686b-usb-uhci",
|
1367 |
.parent = TYPE_PCI_DEVICE, |
1368 |
.instance_size = sizeof(UHCIState),
|
1369 |
.class_init = vt82c686b_uhci_class_init, |
1370 |
}; |
1371 |
|
1372 |
static void ich9_uhci1_class_init(ObjectClass *klass, void *data) |
1373 |
{ |
1374 |
DeviceClass *dc = DEVICE_CLASS(klass); |
1375 |
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
1376 |
|
1377 |
k->init = usb_uhci_common_initfn; |
1378 |
k->vendor_id = PCI_VENDOR_ID_INTEL; |
1379 |
k->device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI1; |
1380 |
k->revision = 0x03;
|
1381 |
k->class_id = PCI_CLASS_SERIAL_USB; |
1382 |
dc->vmsd = &vmstate_uhci; |
1383 |
dc->props = uhci_properties; |
1384 |
} |
1385 |
|
1386 |
static TypeInfo ich9_uhci1_info = {
|
1387 |
.name = "ich9-usb-uhci1",
|
1388 |
.parent = TYPE_PCI_DEVICE, |
1389 |
.instance_size = sizeof(UHCIState),
|
1390 |
.class_init = ich9_uhci1_class_init, |
1391 |
}; |
1392 |
|
1393 |
static void ich9_uhci2_class_init(ObjectClass *klass, void *data) |
1394 |
{ |
1395 |
DeviceClass *dc = DEVICE_CLASS(klass); |
1396 |
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
1397 |
|
1398 |
k->init = usb_uhci_common_initfn; |
1399 |
k->vendor_id = PCI_VENDOR_ID_INTEL; |
1400 |
k->device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI2; |
1401 |
k->revision = 0x03;
|
1402 |
k->class_id = PCI_CLASS_SERIAL_USB; |
1403 |
dc->vmsd = &vmstate_uhci; |
1404 |
dc->props = uhci_properties; |
1405 |
} |
1406 |
|
1407 |
static TypeInfo ich9_uhci2_info = {
|
1408 |
.name = "ich9-usb-uhci2",
|
1409 |
.parent = TYPE_PCI_DEVICE, |
1410 |
.instance_size = sizeof(UHCIState),
|
1411 |
.class_init = ich9_uhci2_class_init, |
1412 |
}; |
1413 |
|
1414 |
static void ich9_uhci3_class_init(ObjectClass *klass, void *data) |
1415 |
{ |
1416 |
DeviceClass *dc = DEVICE_CLASS(klass); |
1417 |
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
1418 |
|
1419 |
k->init = usb_uhci_common_initfn; |
1420 |
k->vendor_id = PCI_VENDOR_ID_INTEL; |
1421 |
k->device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI3; |
1422 |
k->revision = 0x03;
|
1423 |
k->class_id = PCI_CLASS_SERIAL_USB; |
1424 |
dc->vmsd = &vmstate_uhci; |
1425 |
dc->props = uhci_properties; |
1426 |
} |
1427 |
|
1428 |
static TypeInfo ich9_uhci3_info = {
|
1429 |
.name = "ich9-usb-uhci3",
|
1430 |
.parent = TYPE_PCI_DEVICE, |
1431 |
.instance_size = sizeof(UHCIState),
|
1432 |
.class_init = ich9_uhci3_class_init, |
1433 |
}; |
1434 |
|
1435 |
static void uhci_register_types(void) |
1436 |
{ |
1437 |
type_register_static(&piix3_uhci_info); |
1438 |
type_register_static(&piix4_uhci_info); |
1439 |
type_register_static(&vt82c686b_uhci_info); |
1440 |
type_register_static(&ich9_uhci1_info); |
1441 |
type_register_static(&ich9_uhci2_info); |
1442 |
type_register_static(&ich9_uhci3_info); |
1443 |
} |
1444 |
|
1445 |
type_init(uhci_register_types) |