950 |
950 |
/* neg neg. nego nego. */
|
951 |
951 |
GEN_INT_ARITH1_64 (neg, 0x1F, 0x08, 0x03, PPC_INTEGER);
|
952 |
952 |
/* subf subf. subfo subfo. */
|
|
953 |
static always_inline void gen_op_subf (void)
|
|
954 |
{
|
|
955 |
tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
|
|
956 |
}
|
953 |
957 |
static always_inline void gen_op_subfo (void)
|
954 |
958 |
{
|
955 |
959 |
tcg_gen_not_tl(cpu_T[2], cpu_T[0]);
|
956 |
|
gen_op_subf();
|
|
960 |
tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
|
957 |
961 |
gen_op_check_addo();
|
958 |
962 |
}
|
959 |
963 |
#if defined(TARGET_PPC64)
|
... | ... | |
961 |
965 |
static always_inline void gen_op_subfo_64 (void)
|
962 |
966 |
{
|
963 |
967 |
tcg_gen_not_i64(cpu_T[2], cpu_T[0]);
|
964 |
|
gen_op_subf();
|
|
968 |
tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
|
965 |
969 |
gen_op_check_addo_64();
|
966 |
970 |
}
|
967 |
971 |
#endif
|
... | ... | |
969 |
973 |
/* subfc subfc. subfco subfco. */
|
970 |
974 |
static always_inline void gen_op_subfc (void)
|
971 |
975 |
{
|
972 |
|
gen_op_subf();
|
|
976 |
tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
|
973 |
977 |
gen_op_check_subfc();
|
974 |
978 |
}
|
975 |
979 |
static always_inline void gen_op_subfco (void)
|
976 |
980 |
{
|
977 |
981 |
tcg_gen_not_tl(cpu_T[2], cpu_T[0]);
|
978 |
|
gen_op_subf();
|
|
982 |
tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
|
979 |
983 |
gen_op_check_subfc();
|
980 |
984 |
gen_op_check_addo();
|
981 |
985 |
}
|
982 |
986 |
#if defined(TARGET_PPC64)
|
983 |
987 |
static always_inline void gen_op_subfc_64 (void)
|
984 |
988 |
{
|
985 |
|
gen_op_subf();
|
|
989 |
tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
|
986 |
990 |
gen_op_check_subfc_64();
|
987 |
991 |
}
|
988 |
992 |
static always_inline void gen_op_subfco_64 (void)
|
989 |
993 |
{
|
990 |
994 |
tcg_gen_not_i64(cpu_T[2], cpu_T[0]);
|
991 |
|
gen_op_subf();
|
|
995 |
tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
|
992 |
996 |
gen_op_check_subfc_64();
|
993 |
997 |
gen_op_check_addo_64();
|
994 |
998 |
}
|