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         uint32_t regs[ECC_NREGS];
     } ECCState;
     static void ecc_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
+    {
         printf("ECC: Unsupported write 0x" TARGET_FMT_plx " %02x\n",
                addr, val & 0xff);
+    }
     static uint32_t ecc_mem_readb(void *opaque, target_phys_addr_t addr)
+    {
         printf("ECC: Unsupported read 0x" TARGET_FMT_plx " 00\n", addr);
         return 0;
+    }
     static void ecc_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
+    {
         printf("ECC: Unsupported write 0x" TARGET_FMT_plx " %04x\n",
                addr, val & 0xffff);
+    }
     static uint32_t ecc_mem_readw(void *opaque, target_phys_addr_t addr)
+    {
         printf("ECC: Unsupported read 0x" TARGET_FMT_plx " 0000\n", addr);
         return 0;
+    }
     static void ecc_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
+    {
         ECCState *s = opaque;
-...
+    }
     static CPUReadMemoryFunc *ecc_mem_read[3] = {
         ecc_mem_readb,
         ecc_mem_readw,
         NULL,
         NULL,
         ecc_mem_readl,
     };
     static CPUWriteMemoryFunc *ecc_mem_write[3] = {
         ecc_mem_writeb,
         ecc_mem_writew,
         NULL,
         NULL,
         ecc_mem_writel,
     };

     static CPUReadMemoryFunc *esp_mem_read[3] = {
         esp_mem_readb,
         esp_mem_readb,
         esp_mem_readb,
         NULL,
         NULL,
     };
     static CPUWriteMemoryFunc *esp_mem_write[3] = {
         esp_mem_writeb,
         esp_mem_writeb,
         esp_mem_writeb,
         NULL,
         NULL,
     };
     static void esp_save(QEMUFile *f, void *opaque)

         fdctrl_write_mem,
     };
     static CPUReadMemoryFunc *fdctrl_mem_read_strict[3] = {
         fdctrl_read_mem,
         NULL,
         NULL,
     };
     static CPUWriteMemoryFunc *fdctrl_mem_write_strict[3] = {
         fdctrl_write_mem,
         NULL,
         NULL,
     };
     static void fd_save (QEMUFile *f, fdrive_t *fd)
+    {
         uint8_t tmp;
-...
         fdctrl_reset(s, 0);
+    }
     fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped,
                            target_phys_addr_t io_base,
                            BlockDriverState **fds)
     static fdctrl_t *fdctrl_init_common (qemu_irq irq, int dma_chann,
                                          target_phys_addr_t io_base,
                                          BlockDriverState **fds)
+    {
         fdctrl_t *fdctrl;
         int io_mem;
         int i;
         FLOPPY_DPRINTF("init controller\n");
-...
         fdctrl->dma_chann = dma_chann;
         fdctrl->io_base = io_base;
         fdctrl->config = 0x60; /* Implicit seek, polling & FIFO enabled */
         fdctrl->sun4m = 0;
         if (fdctrl->dma_chann != -1) {
             fdctrl->dma_en = 1;
             DMA_register_channel(dma_chann, &fdctrl_transfer_handler, fdctrl);
-...
+        }
         fdctrl_reset(fdctrl, 0);
         fdctrl->state = FD_CTRL_ACTIVE;
         register_savevm("fdc", io_base, 1, fdc_save, fdc_load, fdctrl);
         qemu_register_reset(fdctrl_external_reset, fdctrl);
         for (i = 0; i < 2; i++) {
             fd_revalidate(&fdctrl->drives[i]);
+        }
         return fdctrl;
+    }
     fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped,
                            target_phys_addr_t io_base,
                            BlockDriverState **fds)
+    {
         fdctrl_t *fdctrl;
         int io_mem;
         fdctrl = fdctrl_init_common(irq, dma_chann, io_base, fds);
         fdctrl->sun4m = 0;
         if (mem_mapped) {
             io_mem = cpu_register_io_memory(0, fdctrl_mem_read, fdctrl_mem_write,
                                             fdctrl);
-...
             register_ioport_write((uint32_t)io_base + 0x07, 1, 1, &fdctrl_write,
                                   fdctrl);
+        }
         register_savevm("fdc", io_base, 1, fdc_save, fdc_load, fdctrl);
         qemu_register_reset(fdctrl_external_reset, fdctrl);
         for (i = 0; i < 2; i++) {
             fd_revalidate(&fdctrl->drives[i]);
+        }
         return fdctrl;
+    }
-...
                                  BlockDriverState **fds)
+    {
         fdctrl_t *fdctrl;
         int io_mem;
         fdctrl = fdctrl_init(irq, 0, 1, io_base, fds);
         fdctrl = fdctrl_init_common(irq, 0, io_base, fds);
         fdctrl->sun4m = 1;
         io_mem = cpu_register_io_memory(0, fdctrl_mem_read_strict,
                                         fdctrl_mem_write_strict,
                                         fdctrl);
         cpu_register_physical_memory(io_base, 0x08, io_mem);
         return fdctrl;
+    }

         qemu_irq irq;
     } IOMMUState;
     static uint32_t iommu_mem_readw(void *opaque, target_phys_addr_t addr)
     static uint32_t iommu_mem_readl(void *opaque, target_phys_addr_t addr)
+    {
         IOMMUState *s = opaque;
         target_phys_addr_t saddr;
-...
         return ret;
+    }
     static void iommu_mem_writew(void *opaque, target_phys_addr_t addr,
     static void iommu_mem_writel(void *opaque, target_phys_addr_t addr,
                                  uint32_t val)
+    {
         IOMMUState *s = opaque;
-...
+    }
     static CPUReadMemoryFunc *iommu_mem_read[3] = {
         iommu_mem_readw,
         iommu_mem_readw,
         iommu_mem_readw,
         NULL,
         NULL,
         iommu_mem_readl,
     };
     static CPUWriteMemoryFunc *iommu_mem_write[3] = {
         iommu_mem_writew,
         iommu_mem_writew,
         iommu_mem_writew,
         NULL,
         NULL,
         iommu_mem_writel,
     };
     static uint32_t iommu_page_get_flags(IOMMUState *s, target_phys_addr_t addr)

+    }
     static CPUReadMemoryFunc *lance_mem_read[3] = {
         NULL,
         lance_mem_readw,
         lance_mem_readw,
         lance_mem_readw,
         NULL,
     };
     static CPUWriteMemoryFunc *lance_mem_write[3] = {
         NULL,
         lance_mem_writew,
         lance_mem_writew,
         lance_mem_writew,
         NULL,
     };
     void lance_init(NICInfo *nd, target_phys_addr_t leaddr, void *dma_opaque,

+    }
     static CPUReadMemoryFunc *sbi_mem_read[3] = {
         sbi_mem_readl,
         sbi_mem_readl,
         NULL,
         NULL,
         sbi_mem_readl,
     };
     static CPUWriteMemoryFunc *sbi_mem_write[3] = {
         sbi_mem_writel,
         sbi_mem_writel,
         NULL,
         NULL,
         sbi_mem_writel,
     };

+    }
     static CPUReadMemoryFunc *slavio_intctl_mem_read[3] = {
         slavio_intctl_mem_readl,
         slavio_intctl_mem_readl,
         NULL,
         NULL,
         slavio_intctl_mem_readl,
     };
     static CPUWriteMemoryFunc *slavio_intctl_mem_write[3] = {
         slavio_intctl_mem_writel,
         slavio_intctl_mem_writel,
         NULL,
         NULL,
         slavio_intctl_mem_writel,
     };
-...
+    }
     static CPUReadMemoryFunc *slavio_intctlm_mem_read[3] = {
         slavio_intctlm_mem_readl,
         slavio_intctlm_mem_readl,
         NULL,
         NULL,
         slavio_intctlm_mem_readl,
     };
     static CPUWriteMemoryFunc *slavio_intctlm_mem_write[3] = {
         slavio_intctlm_mem_writel,
         slavio_intctlm_mem_writel,
         NULL,
         NULL,
         slavio_intctlm_mem_writel,
     };

     static CPUReadMemoryFunc *slavio_misc_mem_read[3] = {
         slavio_misc_mem_readb,
         slavio_misc_mem_readb,
         slavio_misc_mem_readb,
         NULL,
         NULL,
     };
     static CPUWriteMemoryFunc *slavio_misc_mem_write[3] = {
         slavio_misc_mem_writeb,
         slavio_misc_mem_writeb,
         slavio_misc_mem_writeb,
         NULL,
         NULL,
     };
     static uint32_t slavio_sysctrl_mem_readl(void *opaque, target_phys_addr_t addr)
-...
+    }
     static CPUReadMemoryFunc *slavio_sysctrl_mem_read[3] = {
         slavio_sysctrl_mem_readl,
         slavio_sysctrl_mem_readl,
         NULL,
         NULL,
         slavio_sysctrl_mem_readl,
     };
     static CPUWriteMemoryFunc *slavio_sysctrl_mem_write[3] = {
         slavio_sysctrl_mem_writel,
         slavio_sysctrl_mem_writel,
         NULL,
         NULL,
         slavio_sysctrl_mem_writel,
     };
     static uint32_t slavio_led_mem_reads(void *opaque, target_phys_addr_t addr)
     static uint32_t slavio_led_mem_readw(void *opaque, target_phys_addr_t addr)
+    {
         MiscState *s = opaque;
         uint32_t ret = 0, saddr;
-...
         return ret;
+    }
     static void slavio_led_mem_writes(void *opaque, target_phys_addr_t addr,
     static void slavio_led_mem_writew(void *opaque, target_phys_addr_t addr,
                                       uint32_t val)
+    {
         MiscState *s = opaque;
-...
+    }
     static CPUReadMemoryFunc *slavio_led_mem_read[3] = {
         slavio_led_mem_reads,
         slavio_led_mem_reads,
         slavio_led_mem_reads,
         NULL,
         slavio_led_mem_readw,
         NULL,
     };
     static CPUWriteMemoryFunc *slavio_led_mem_write[3] = {
         slavio_led_mem_writes,
         slavio_led_mem_writes,
         slavio_led_mem_writes,
         NULL,
         slavio_led_mem_writew,
         NULL,
     };
     static void slavio_misc_save(QEMUFile *f, void *opaque)

     static CPUReadMemoryFunc *slavio_serial_mem_read[3] = {
         slavio_serial_mem_readb,
         slavio_serial_mem_readb,
         slavio_serial_mem_readb,
         NULL,
         NULL,
     };
     static CPUWriteMemoryFunc *slavio_serial_mem_write[3] = {
         slavio_serial_mem_writeb,
         slavio_serial_mem_writeb,
         slavio_serial_mem_writeb,
         NULL,
         NULL,
     };
     static void slavio_serial_save_chn(QEMUFile *f, ChannelState *s)

+    }
     static CPUReadMemoryFunc *slavio_timer_mem_read[3] = {
         slavio_timer_mem_readl,
         slavio_timer_mem_readl,
         NULL,
         NULL,
         slavio_timer_mem_readl,
     };
     static CPUWriteMemoryFunc *slavio_timer_mem_write[3] = {
         slavio_timer_mem_writel,
         slavio_timer_mem_writel,
         NULL,
         NULL,
         slavio_timer_mem_writel,
     };

+    }
     static CPUReadMemoryFunc *dma_mem_read[3] = {
         dma_mem_readl,
         dma_mem_readl,
         NULL,
         NULL,
         dma_mem_readl,
     };
     static CPUWriteMemoryFunc *dma_mem_write[3] = {
         dma_mem_writel,
         dma_mem_writel,
         NULL,
         NULL,
         dma_mem_writel,
     };

     static CPUReadMemoryFunc *sun4c_intctl_mem_read[3] = {
         sun4c_intctl_mem_readb,
         sun4c_intctl_mem_readb,
         sun4c_intctl_mem_readb,
         NULL,
         NULL,
     };
     static CPUWriteMemoryFunc *sun4c_intctl_mem_write[3] = {
         sun4c_intctl_mem_writeb,
         sun4c_intctl_mem_writeb,
         sun4c_intctl_mem_writeb,
         NULL,
         NULL,
     };
     void sun4c_pic_info(void *opaque)

+    }
     static CPUReadMemoryFunc *tcx_dac_read[3] = {
         tcx_dac_readl,
         tcx_dac_readl,
         NULL,
         NULL,
         tcx_dac_readl,
     };
     static CPUWriteMemoryFunc *tcx_dac_write[3] = {
         tcx_dac_writel,
         tcx_dac_writel,
         NULL,
         NULL,
         tcx_dac_writel,
     };
-...
+    }
     static CPUReadMemoryFunc *tcx_dummy_read[3] = {
         tcx_dummy_readl,
         tcx_dummy_readl,
         NULL,
         NULL,
         tcx_dummy_readl,
     };
     static CPUWriteMemoryFunc *tcx_dummy_write[3] = {
         tcx_dummy_writel,
         tcx_dummy_writel,
         NULL,
         NULL,
         tcx_dummy_writel,
     };

Archipelago » qemu

Revision 7c560456