root / hw / sun4m.c @ 7c7b829e
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1 | 420557e8 | bellard | /*
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2 | ee76f82e | blueswir1 | * QEMU Sun4m & Sun4d & Sun4c System Emulator
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3 | 5fafdf24 | ths | *
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4 | b81b3b10 | bellard | * Copyright (c) 2003-2005 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 420557e8 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 420557e8 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 420557e8 | bellard | * in the Software without restriction, including without limitation the rights
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9 | 420557e8 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 420557e8 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 420557e8 | bellard | * furnished to do so, subject to the following conditions:
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12 | 420557e8 | bellard | *
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13 | 420557e8 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 420557e8 | bellard | * all copies or substantial portions of the Software.
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15 | 420557e8 | bellard | *
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16 | 420557e8 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 420557e8 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 420557e8 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 420557e8 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 420557e8 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 420557e8 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 420557e8 | bellard | * THE SOFTWARE.
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23 | 420557e8 | bellard | */
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24 | 9d07d757 | Paul Brook | #include "sysbus.h" |
25 | 87ecb68b | pbrook | #include "qemu-timer.h" |
26 | 87ecb68b | pbrook | #include "sun4m.h" |
27 | 87ecb68b | pbrook | #include "nvram.h" |
28 | 87ecb68b | pbrook | #include "sparc32_dma.h" |
29 | 87ecb68b | pbrook | #include "fdc.h" |
30 | 87ecb68b | pbrook | #include "sysemu.h" |
31 | 87ecb68b | pbrook | #include "net.h" |
32 | 87ecb68b | pbrook | #include "boards.h" |
33 | d2c63fc1 | blueswir1 | #include "firmware_abi.h" |
34 | 1cd3af54 | Gerd Hoffmann | #include "esp.h" |
35 | 22548760 | blueswir1 | #include "pc.h" |
36 | 22548760 | blueswir1 | #include "isa.h" |
37 | 3cce6243 | blueswir1 | #include "fw_cfg.h" |
38 | b4ed08e0 | blueswir1 | #include "escc.h" |
39 | 676d9b9b | Artyom Tarasenko | #include "empty_slot.h" |
40 | 4b48bf05 | Blue Swirl | #include "qdev-addr.h" |
41 | ca20cf32 | Blue Swirl | #include "loader.h" |
42 | ca20cf32 | Blue Swirl | #include "elf.h" |
43 | d2c63fc1 | blueswir1 | |
44 | b3a23197 | blueswir1 | //#define DEBUG_IRQ
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45 | 420557e8 | bellard | |
46 | 36cd9210 | blueswir1 | /*
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47 | 36cd9210 | blueswir1 | * Sun4m architecture was used in the following machines:
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48 | 36cd9210 | blueswir1 | *
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49 | 36cd9210 | blueswir1 | * SPARCserver 6xxMP/xx
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50 | 77f193da | blueswir1 | * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
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51 | 77f193da | blueswir1 | * SPARCclassic X (4/10)
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52 | 36cd9210 | blueswir1 | * SPARCstation LX/ZX (4/30)
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53 | 36cd9210 | blueswir1 | * SPARCstation Voyager
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54 | 36cd9210 | blueswir1 | * SPARCstation 10/xx, SPARCserver 10/xx
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55 | 36cd9210 | blueswir1 | * SPARCstation 5, SPARCserver 5
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56 | 36cd9210 | blueswir1 | * SPARCstation 20/xx, SPARCserver 20
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57 | 36cd9210 | blueswir1 | * SPARCstation 4
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58 | 36cd9210 | blueswir1 | *
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59 | 7d85892b | blueswir1 | * Sun4d architecture was used in the following machines:
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60 | 7d85892b | blueswir1 | *
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61 | 7d85892b | blueswir1 | * SPARCcenter 2000
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62 | 7d85892b | blueswir1 | * SPARCserver 1000
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63 | 7d85892b | blueswir1 | *
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64 | ee76f82e | blueswir1 | * Sun4c architecture was used in the following machines:
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65 | ee76f82e | blueswir1 | * SPARCstation 1/1+, SPARCserver 1/1+
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66 | ee76f82e | blueswir1 | * SPARCstation SLC
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67 | ee76f82e | blueswir1 | * SPARCstation IPC
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68 | ee76f82e | blueswir1 | * SPARCstation ELC
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69 | ee76f82e | blueswir1 | * SPARCstation IPX
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70 | ee76f82e | blueswir1 | *
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71 | 36cd9210 | blueswir1 | * See for example: http://www.sunhelp.org/faq/sunref1.html
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72 | 36cd9210 | blueswir1 | */
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73 | 36cd9210 | blueswir1 | |
74 | b3a23197 | blueswir1 | #ifdef DEBUG_IRQ
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75 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...) \
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76 | 001faf32 | Blue Swirl | do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) |
77 | b3a23197 | blueswir1 | #else
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78 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...)
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79 | b3a23197 | blueswir1 | #endif
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80 | b3a23197 | blueswir1 | |
81 | 420557e8 | bellard | #define KERNEL_LOAD_ADDR 0x00004000 |
82 | b6f479d3 | bellard | #define CMDLINE_ADDR 0x007ff000 |
83 | 713c45fa | bellard | #define INITRD_LOAD_ADDR 0x00800000 |
84 | a7227727 | blueswir1 | #define PROM_SIZE_MAX (1024 * 1024) |
85 | 40ce0a9a | blueswir1 | #define PROM_VADDR 0xffd00000 |
86 | f930d07e | blueswir1 | #define PROM_FILENAME "openbios-sparc32" |
87 | 3cce6243 | blueswir1 | #define CFG_ADDR 0xd00000510ULL |
88 | fbfcf955 | blueswir1 | #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00) |
89 | b8174937 | bellard | |
90 | ba3c64fb | bellard | #define MAX_CPUS 16 |
91 | b3a23197 | blueswir1 | #define MAX_PILS 16 |
92 | 420557e8 | bellard | |
93 | b4ed08e0 | blueswir1 | #define ESCC_CLOCK 4915200 |
94 | b4ed08e0 | blueswir1 | |
95 | 8137cde8 | blueswir1 | struct sun4m_hwdef {
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96 | 3386376c | Artyom Tarasenko | target_phys_addr_t iommu_base, iommu_pad_base, iommu_pad_len, slavio_base; |
97 | c227f099 | Anthony Liguori | target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base; |
98 | c227f099 | Anthony Liguori | target_phys_addr_t serial_base, fd_base; |
99 | c5de386a | Artyom Tarasenko | target_phys_addr_t afx_base, idreg_base, dma_base, esp_base, le_base; |
100 | c227f099 | Anthony Liguori | target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base; |
101 | c227f099 | Anthony Liguori | target_phys_addr_t ecc_base; |
102 | 7eb0c8e8 | blueswir1 | uint32_t ecc_version; |
103 | 905fdcb5 | blueswir1 | uint8_t nvram_machine_id; |
104 | 905fdcb5 | blueswir1 | uint16_t machine_id; |
105 | 7fbfb139 | blueswir1 | uint32_t iommu_version; |
106 | 3ebf5aaf | blueswir1 | uint64_t max_mem; |
107 | 3ebf5aaf | blueswir1 | const char * const default_cpu_model; |
108 | 36cd9210 | blueswir1 | }; |
109 | 36cd9210 | blueswir1 | |
110 | 7d85892b | blueswir1 | #define MAX_IOUNITS 5 |
111 | 7d85892b | blueswir1 | |
112 | 7d85892b | blueswir1 | struct sun4d_hwdef {
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113 | c227f099 | Anthony Liguori | target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base; |
114 | c227f099 | Anthony Liguori | target_phys_addr_t counter_base, nvram_base, ms_kb_base; |
115 | c227f099 | Anthony Liguori | target_phys_addr_t serial_base; |
116 | c227f099 | Anthony Liguori | target_phys_addr_t espdma_base, esp_base; |
117 | c227f099 | Anthony Liguori | target_phys_addr_t ledma_base, le_base; |
118 | c227f099 | Anthony Liguori | target_phys_addr_t tcx_base; |
119 | c227f099 | Anthony Liguori | target_phys_addr_t sbi_base; |
120 | 905fdcb5 | blueswir1 | uint8_t nvram_machine_id; |
121 | 905fdcb5 | blueswir1 | uint16_t machine_id; |
122 | 7d85892b | blueswir1 | uint32_t iounit_version; |
123 | 7d85892b | blueswir1 | uint64_t max_mem; |
124 | 7d85892b | blueswir1 | const char * const default_cpu_model; |
125 | 7d85892b | blueswir1 | }; |
126 | 7d85892b | blueswir1 | |
127 | 8137cde8 | blueswir1 | struct sun4c_hwdef {
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128 | c227f099 | Anthony Liguori | target_phys_addr_t iommu_base, slavio_base; |
129 | c227f099 | Anthony Liguori | target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base; |
130 | c227f099 | Anthony Liguori | target_phys_addr_t serial_base, fd_base; |
131 | c227f099 | Anthony Liguori | target_phys_addr_t idreg_base, dma_base, esp_base, le_base; |
132 | c227f099 | Anthony Liguori | target_phys_addr_t tcx_base, aux1_base; |
133 | 8137cde8 | blueswir1 | uint8_t nvram_machine_id; |
134 | 8137cde8 | blueswir1 | uint16_t machine_id; |
135 | 8137cde8 | blueswir1 | uint32_t iommu_version; |
136 | 8137cde8 | blueswir1 | uint64_t max_mem; |
137 | 8137cde8 | blueswir1 | const char * const default_cpu_model; |
138 | 8137cde8 | blueswir1 | }; |
139 | 8137cde8 | blueswir1 | |
140 | 6f7e9aec | bellard | int DMA_get_channel_mode (int nchan) |
141 | 6f7e9aec | bellard | { |
142 | 6f7e9aec | bellard | return 0; |
143 | 6f7e9aec | bellard | } |
144 | 6f7e9aec | bellard | int DMA_read_memory (int nchan, void *buf, int pos, int size) |
145 | 6f7e9aec | bellard | { |
146 | 6f7e9aec | bellard | return 0; |
147 | 6f7e9aec | bellard | } |
148 | 6f7e9aec | bellard | int DMA_write_memory (int nchan, void *buf, int pos, int size) |
149 | 6f7e9aec | bellard | { |
150 | 6f7e9aec | bellard | return 0; |
151 | 6f7e9aec | bellard | } |
152 | 6f7e9aec | bellard | void DMA_hold_DREQ (int nchan) {} |
153 | 6f7e9aec | bellard | void DMA_release_DREQ (int nchan) {} |
154 | 6f7e9aec | bellard | void DMA_schedule(int nchan) {} |
155 | 4556bd8b | Blue Swirl | |
156 | 4556bd8b | Blue Swirl | void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit) |
157 | 4556bd8b | Blue Swirl | { |
158 | 4556bd8b | Blue Swirl | } |
159 | 4556bd8b | Blue Swirl | |
160 | 6f7e9aec | bellard | void DMA_register_channel (int nchan, |
161 | 6f7e9aec | bellard | DMA_transfer_handler transfer_handler, |
162 | 6f7e9aec | bellard | void *opaque)
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163 | 6f7e9aec | bellard | { |
164 | 6f7e9aec | bellard | } |
165 | 6f7e9aec | bellard | |
166 | 513f789f | blueswir1 | static int fw_cfg_boot_set(void *opaque, const char *boot_device) |
167 | 81864572 | blueswir1 | { |
168 | 513f789f | blueswir1 | fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
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169 | 81864572 | blueswir1 | return 0; |
170 | 81864572 | blueswir1 | } |
171 | 81864572 | blueswir1 | |
172 | 43a34704 | Blue Swirl | static void nvram_init(M48t59State *nvram, uint8_t *macaddr, |
173 | 43a34704 | Blue Swirl | const char *cmdline, const char *boot_devices, |
174 | 43a34704 | Blue Swirl | ram_addr_t RAM_size, uint32_t kernel_size, |
175 | f930d07e | blueswir1 | int width, int height, int depth, |
176 | 905fdcb5 | blueswir1 | int nvram_machine_id, const char *arch) |
177 | e80cfcfc | bellard | { |
178 | d2c63fc1 | blueswir1 | unsigned int i; |
179 | 66508601 | blueswir1 | uint32_t start, end; |
180 | d2c63fc1 | blueswir1 | uint8_t image[0x1ff0];
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181 | d2c63fc1 | blueswir1 | struct OpenBIOS_nvpart_v1 *part_header;
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182 | d2c63fc1 | blueswir1 | |
183 | d2c63fc1 | blueswir1 | memset(image, '\0', sizeof(image)); |
184 | e80cfcfc | bellard | |
185 | 513f789f | blueswir1 | start = 0;
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186 | b6f479d3 | bellard | |
187 | 66508601 | blueswir1 | // OpenBIOS nvram variables
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188 | 66508601 | blueswir1 | // Variable partition
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189 | d2c63fc1 | blueswir1 | part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
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190 | d2c63fc1 | blueswir1 | part_header->signature = OPENBIOS_PART_SYSTEM; |
191 | 363a37d5 | blueswir1 | pstrcpy(part_header->name, sizeof(part_header->name), "system"); |
192 | 66508601 | blueswir1 | |
193 | d2c63fc1 | blueswir1 | end = start + sizeof(struct OpenBIOS_nvpart_v1); |
194 | 66508601 | blueswir1 | for (i = 0; i < nb_prom_envs; i++) |
195 | d2c63fc1 | blueswir1 | end = OpenBIOS_set_var(image, end, prom_envs[i]); |
196 | d2c63fc1 | blueswir1 | |
197 | d2c63fc1 | blueswir1 | // End marker
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198 | d2c63fc1 | blueswir1 | image[end++] = '\0';
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199 | 66508601 | blueswir1 | |
200 | 66508601 | blueswir1 | end = start + ((end - start + 15) & ~15); |
201 | d2c63fc1 | blueswir1 | OpenBIOS_finish_partition(part_header, end - start); |
202 | 66508601 | blueswir1 | |
203 | 66508601 | blueswir1 | // free partition
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204 | 66508601 | blueswir1 | start = end; |
205 | d2c63fc1 | blueswir1 | part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
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206 | d2c63fc1 | blueswir1 | part_header->signature = OPENBIOS_PART_FREE; |
207 | 363a37d5 | blueswir1 | pstrcpy(part_header->name, sizeof(part_header->name), "free"); |
208 | 66508601 | blueswir1 | |
209 | 66508601 | blueswir1 | end = 0x1fd0;
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210 | d2c63fc1 | blueswir1 | OpenBIOS_finish_partition(part_header, end - start); |
211 | d2c63fc1 | blueswir1 | |
212 | 905fdcb5 | blueswir1 | Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, |
213 | 905fdcb5 | blueswir1 | nvram_machine_id); |
214 | d2c63fc1 | blueswir1 | |
215 | d2c63fc1 | blueswir1 | for (i = 0; i < sizeof(image); i++) |
216 | d2c63fc1 | blueswir1 | m48t59_write(nvram, i, image[i]); |
217 | e80cfcfc | bellard | } |
218 | e80cfcfc | bellard | |
219 | d453c2c3 | Blue Swirl | static DeviceState *slavio_intctl;
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220 | e80cfcfc | bellard | |
221 | 376253ec | aliguori | void pic_info(Monitor *mon)
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222 | e80cfcfc | bellard | { |
223 | 7d85892b | blueswir1 | if (slavio_intctl)
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224 | 376253ec | aliguori | slavio_pic_info(mon, slavio_intctl); |
225 | e80cfcfc | bellard | } |
226 | e80cfcfc | bellard | |
227 | 376253ec | aliguori | void irq_info(Monitor *mon)
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228 | e80cfcfc | bellard | { |
229 | 7d85892b | blueswir1 | if (slavio_intctl)
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230 | 376253ec | aliguori | slavio_irq_info(mon, slavio_intctl); |
231 | e80cfcfc | bellard | } |
232 | e80cfcfc | bellard | |
233 | 327ac2e7 | blueswir1 | void cpu_check_irqs(CPUState *env)
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234 | 327ac2e7 | blueswir1 | { |
235 | 327ac2e7 | blueswir1 | if (env->pil_in && (env->interrupt_index == 0 || |
236 | 327ac2e7 | blueswir1 | (env->interrupt_index & ~15) == TT_EXTINT)) {
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237 | 327ac2e7 | blueswir1 | unsigned int i; |
238 | 327ac2e7 | blueswir1 | |
239 | 327ac2e7 | blueswir1 | for (i = 15; i > 0; i--) { |
240 | 327ac2e7 | blueswir1 | if (env->pil_in & (1 << i)) { |
241 | 327ac2e7 | blueswir1 | int old_interrupt = env->interrupt_index;
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242 | 327ac2e7 | blueswir1 | |
243 | 327ac2e7 | blueswir1 | env->interrupt_index = TT_EXTINT | i; |
244 | f32d7ec5 | blueswir1 | if (old_interrupt != env->interrupt_index) {
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245 | f32d7ec5 | blueswir1 | DPRINTF("Set CPU IRQ %d\n", i);
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246 | 327ac2e7 | blueswir1 | cpu_interrupt(env, CPU_INTERRUPT_HARD); |
247 | f32d7ec5 | blueswir1 | } |
248 | 327ac2e7 | blueswir1 | break;
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249 | 327ac2e7 | blueswir1 | } |
250 | 327ac2e7 | blueswir1 | } |
251 | 327ac2e7 | blueswir1 | } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) { |
252 | f32d7ec5 | blueswir1 | DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15); |
253 | 327ac2e7 | blueswir1 | env->interrupt_index = 0;
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254 | 327ac2e7 | blueswir1 | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
255 | 327ac2e7 | blueswir1 | } |
256 | 327ac2e7 | blueswir1 | } |
257 | 327ac2e7 | blueswir1 | |
258 | b3a23197 | blueswir1 | static void cpu_set_irq(void *opaque, int irq, int level) |
259 | b3a23197 | blueswir1 | { |
260 | b3a23197 | blueswir1 | CPUState *env = opaque; |
261 | b3a23197 | blueswir1 | |
262 | b3a23197 | blueswir1 | if (level) {
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263 | b3a23197 | blueswir1 | DPRINTF("Raise CPU IRQ %d\n", irq);
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264 | b3a23197 | blueswir1 | env->halted = 0;
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265 | 327ac2e7 | blueswir1 | env->pil_in |= 1 << irq;
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266 | 327ac2e7 | blueswir1 | cpu_check_irqs(env); |
267 | b3a23197 | blueswir1 | } else {
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268 | b3a23197 | blueswir1 | DPRINTF("Lower CPU IRQ %d\n", irq);
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269 | 327ac2e7 | blueswir1 | env->pil_in &= ~(1 << irq);
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270 | 327ac2e7 | blueswir1 | cpu_check_irqs(env); |
271 | b3a23197 | blueswir1 | } |
272 | b3a23197 | blueswir1 | } |
273 | b3a23197 | blueswir1 | |
274 | b3a23197 | blueswir1 | static void dummy_cpu_set_irq(void *opaque, int irq, int level) |
275 | b3a23197 | blueswir1 | { |
276 | b3a23197 | blueswir1 | } |
277 | b3a23197 | blueswir1 | |
278 | c68ea704 | bellard | static void main_cpu_reset(void *opaque) |
279 | c68ea704 | bellard | { |
280 | c68ea704 | bellard | CPUState *env = opaque; |
281 | 3d29fbef | blueswir1 | |
282 | 3d29fbef | blueswir1 | cpu_reset(env); |
283 | 3d29fbef | blueswir1 | env->halted = 0;
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284 | 3d29fbef | blueswir1 | } |
285 | 3d29fbef | blueswir1 | |
286 | 3d29fbef | blueswir1 | static void secondary_cpu_reset(void *opaque) |
287 | 3d29fbef | blueswir1 | { |
288 | 3d29fbef | blueswir1 | CPUState *env = opaque; |
289 | 3d29fbef | blueswir1 | |
290 | c68ea704 | bellard | cpu_reset(env); |
291 | 3d29fbef | blueswir1 | env->halted = 1;
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292 | c68ea704 | bellard | } |
293 | c68ea704 | bellard | |
294 | 6d0c293d | blueswir1 | static void cpu_halt_signal(void *opaque, int irq, int level) |
295 | 6d0c293d | blueswir1 | { |
296 | 6d0c293d | blueswir1 | if (level && cpu_single_env)
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297 | 6d0c293d | blueswir1 | cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT); |
298 | 6d0c293d | blueswir1 | } |
299 | 6d0c293d | blueswir1 | |
300 | 409dbce5 | Aurelien Jarno | static uint64_t translate_kernel_address(void *opaque, uint64_t addr) |
301 | 409dbce5 | Aurelien Jarno | { |
302 | 409dbce5 | Aurelien Jarno | return addr - 0xf0000000ULL; |
303 | 409dbce5 | Aurelien Jarno | } |
304 | 409dbce5 | Aurelien Jarno | |
305 | 3ebf5aaf | blueswir1 | static unsigned long sun4m_load_kernel(const char *kernel_filename, |
306 | 293f78bc | blueswir1 | const char *initrd_filename, |
307 | c227f099 | Anthony Liguori | ram_addr_t RAM_size) |
308 | 3ebf5aaf | blueswir1 | { |
309 | 3ebf5aaf | blueswir1 | int linux_boot;
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310 | 3ebf5aaf | blueswir1 | unsigned int i; |
311 | 3ebf5aaf | blueswir1 | long initrd_size, kernel_size;
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312 | 3c178e72 | Gerd Hoffmann | uint8_t *ptr; |
313 | 3ebf5aaf | blueswir1 | |
314 | 3ebf5aaf | blueswir1 | linux_boot = (kernel_filename != NULL);
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315 | 3ebf5aaf | blueswir1 | |
316 | 3ebf5aaf | blueswir1 | kernel_size = 0;
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317 | 3ebf5aaf | blueswir1 | if (linux_boot) {
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318 | ca20cf32 | Blue Swirl | int bswap_needed;
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319 | ca20cf32 | Blue Swirl | |
320 | ca20cf32 | Blue Swirl | #ifdef BSWAP_NEEDED
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321 | ca20cf32 | Blue Swirl | bswap_needed = 1;
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322 | ca20cf32 | Blue Swirl | #else
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323 | ca20cf32 | Blue Swirl | bswap_needed = 0;
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324 | ca20cf32 | Blue Swirl | #endif
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325 | 409dbce5 | Aurelien Jarno | kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
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326 | 409dbce5 | Aurelien Jarno | NULL, NULL, NULL, 1, ELF_MACHINE, 0); |
327 | 3ebf5aaf | blueswir1 | if (kernel_size < 0) |
328 | 293f78bc | blueswir1 | kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, |
329 | ca20cf32 | Blue Swirl | RAM_size - KERNEL_LOAD_ADDR, bswap_needed, |
330 | ca20cf32 | Blue Swirl | TARGET_PAGE_SIZE); |
331 | 3ebf5aaf | blueswir1 | if (kernel_size < 0) |
332 | 293f78bc | blueswir1 | kernel_size = load_image_targphys(kernel_filename, |
333 | 293f78bc | blueswir1 | KERNEL_LOAD_ADDR, |
334 | 293f78bc | blueswir1 | RAM_size - KERNEL_LOAD_ADDR); |
335 | 3ebf5aaf | blueswir1 | if (kernel_size < 0) { |
336 | 3ebf5aaf | blueswir1 | fprintf(stderr, "qemu: could not load kernel '%s'\n",
|
337 | 3ebf5aaf | blueswir1 | kernel_filename); |
338 | 3ebf5aaf | blueswir1 | exit(1);
|
339 | 3ebf5aaf | blueswir1 | } |
340 | 3ebf5aaf | blueswir1 | |
341 | 3ebf5aaf | blueswir1 | /* load initrd */
|
342 | 3ebf5aaf | blueswir1 | initrd_size = 0;
|
343 | 3ebf5aaf | blueswir1 | if (initrd_filename) {
|
344 | 293f78bc | blueswir1 | initrd_size = load_image_targphys(initrd_filename, |
345 | 293f78bc | blueswir1 | INITRD_LOAD_ADDR, |
346 | 293f78bc | blueswir1 | RAM_size - INITRD_LOAD_ADDR); |
347 | 3ebf5aaf | blueswir1 | if (initrd_size < 0) { |
348 | 3ebf5aaf | blueswir1 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
|
349 | 3ebf5aaf | blueswir1 | initrd_filename); |
350 | 3ebf5aaf | blueswir1 | exit(1);
|
351 | 3ebf5aaf | blueswir1 | } |
352 | 3ebf5aaf | blueswir1 | } |
353 | 3ebf5aaf | blueswir1 | if (initrd_size > 0) { |
354 | 3ebf5aaf | blueswir1 | for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { |
355 | 3c178e72 | Gerd Hoffmann | ptr = rom_ptr(KERNEL_LOAD_ADDR + i); |
356 | 3c178e72 | Gerd Hoffmann | if (ldl_p(ptr) == 0x48647253) { // HdrS |
357 | 3c178e72 | Gerd Hoffmann | stl_p(ptr + 16, INITRD_LOAD_ADDR);
|
358 | 3c178e72 | Gerd Hoffmann | stl_p(ptr + 20, initrd_size);
|
359 | 3ebf5aaf | blueswir1 | break;
|
360 | 3ebf5aaf | blueswir1 | } |
361 | 3ebf5aaf | blueswir1 | } |
362 | 3ebf5aaf | blueswir1 | } |
363 | 3ebf5aaf | blueswir1 | } |
364 | 3ebf5aaf | blueswir1 | return kernel_size;
|
365 | 3ebf5aaf | blueswir1 | } |
366 | 3ebf5aaf | blueswir1 | |
367 | c227f099 | Anthony Liguori | static void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq) |
368 | 4b48bf05 | Blue Swirl | { |
369 | 4b48bf05 | Blue Swirl | DeviceState *dev; |
370 | 4b48bf05 | Blue Swirl | SysBusDevice *s; |
371 | 4b48bf05 | Blue Swirl | |
372 | 4b48bf05 | Blue Swirl | dev = qdev_create(NULL, "iommu"); |
373 | 4b48bf05 | Blue Swirl | qdev_prop_set_uint32(dev, "version", version);
|
374 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
375 | 4b48bf05 | Blue Swirl | s = sysbus_from_qdev(dev); |
376 | 4b48bf05 | Blue Swirl | sysbus_connect_irq(s, 0, irq);
|
377 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 0, addr);
|
378 | 4b48bf05 | Blue Swirl | |
379 | 4b48bf05 | Blue Swirl | return s;
|
380 | 4b48bf05 | Blue Swirl | } |
381 | 4b48bf05 | Blue Swirl | |
382 | c227f099 | Anthony Liguori | static void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq, |
383 | 74ff8d90 | Blue Swirl | void *iommu, qemu_irq *dev_irq)
|
384 | 74ff8d90 | Blue Swirl | { |
385 | 74ff8d90 | Blue Swirl | DeviceState *dev; |
386 | 74ff8d90 | Blue Swirl | SysBusDevice *s; |
387 | 74ff8d90 | Blue Swirl | |
388 | 74ff8d90 | Blue Swirl | dev = qdev_create(NULL, "sparc32_dma"); |
389 | 74ff8d90 | Blue Swirl | qdev_prop_set_ptr(dev, "iommu_opaque", iommu);
|
390 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
391 | 74ff8d90 | Blue Swirl | s = sysbus_from_qdev(dev); |
392 | 74ff8d90 | Blue Swirl | sysbus_connect_irq(s, 0, parent_irq);
|
393 | 74ff8d90 | Blue Swirl | *dev_irq = qdev_get_gpio_in(dev, 0);
|
394 | 74ff8d90 | Blue Swirl | sysbus_mmio_map(s, 0, daddr);
|
395 | 74ff8d90 | Blue Swirl | |
396 | 74ff8d90 | Blue Swirl | return s;
|
397 | 74ff8d90 | Blue Swirl | } |
398 | 74ff8d90 | Blue Swirl | |
399 | c227f099 | Anthony Liguori | static void lance_init(NICInfo *nd, target_phys_addr_t leaddr, |
400 | 74ff8d90 | Blue Swirl | void *dma_opaque, qemu_irq irq)
|
401 | 9d07d757 | Paul Brook | { |
402 | 9d07d757 | Paul Brook | DeviceState *dev; |
403 | 9d07d757 | Paul Brook | SysBusDevice *s; |
404 | 74ff8d90 | Blue Swirl | qemu_irq reset; |
405 | 9d07d757 | Paul Brook | |
406 | 9d07d757 | Paul Brook | qemu_check_nic_model(&nd_table[0], "lance"); |
407 | 9d07d757 | Paul Brook | |
408 | 9d07d757 | Paul Brook | dev = qdev_create(NULL, "lance"); |
409 | 76224833 | Gerd Hoffmann | qdev_set_nic_properties(dev, nd); |
410 | daa65491 | Blue Swirl | qdev_prop_set_ptr(dev, "dma", dma_opaque);
|
411 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
412 | 9d07d757 | Paul Brook | s = sysbus_from_qdev(dev); |
413 | 9d07d757 | Paul Brook | sysbus_mmio_map(s, 0, leaddr);
|
414 | 9d07d757 | Paul Brook | sysbus_connect_irq(s, 0, irq);
|
415 | 74ff8d90 | Blue Swirl | reset = qdev_get_gpio_in(dev, 0);
|
416 | 74ff8d90 | Blue Swirl | qdev_connect_gpio_out(dma_opaque, 0, reset);
|
417 | 9d07d757 | Paul Brook | } |
418 | 9d07d757 | Paul Brook | |
419 | c227f099 | Anthony Liguori | static DeviceState *slavio_intctl_init(target_phys_addr_t addr,
|
420 | c227f099 | Anthony Liguori | target_phys_addr_t addrg, |
421 | 462eda24 | Blue Swirl | qemu_irq **parent_irq) |
422 | 4b48bf05 | Blue Swirl | { |
423 | 4b48bf05 | Blue Swirl | DeviceState *dev; |
424 | 4b48bf05 | Blue Swirl | SysBusDevice *s; |
425 | 4b48bf05 | Blue Swirl | unsigned int i, j; |
426 | 4b48bf05 | Blue Swirl | |
427 | 4b48bf05 | Blue Swirl | dev = qdev_create(NULL, "slavio_intctl"); |
428 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
429 | 4b48bf05 | Blue Swirl | |
430 | 4b48bf05 | Blue Swirl | s = sysbus_from_qdev(dev); |
431 | 4b48bf05 | Blue Swirl | |
432 | 4b48bf05 | Blue Swirl | for (i = 0; i < MAX_CPUS; i++) { |
433 | 4b48bf05 | Blue Swirl | for (j = 0; j < MAX_PILS; j++) { |
434 | 4b48bf05 | Blue Swirl | sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]); |
435 | 4b48bf05 | Blue Swirl | } |
436 | 4b48bf05 | Blue Swirl | } |
437 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 0, addrg);
|
438 | 4b48bf05 | Blue Swirl | for (i = 0; i < MAX_CPUS; i++) { |
439 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
|
440 | 4b48bf05 | Blue Swirl | } |
441 | 4b48bf05 | Blue Swirl | |
442 | 4b48bf05 | Blue Swirl | return dev;
|
443 | 4b48bf05 | Blue Swirl | } |
444 | 4b48bf05 | Blue Swirl | |
445 | 4b48bf05 | Blue Swirl | #define SYS_TIMER_OFFSET 0x10000ULL |
446 | 4b48bf05 | Blue Swirl | #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu) |
447 | 4b48bf05 | Blue Swirl | |
448 | c227f099 | Anthony Liguori | static void slavio_timer_init_all(target_phys_addr_t addr, qemu_irq master_irq, |
449 | 4b48bf05 | Blue Swirl | qemu_irq *cpu_irqs, unsigned int num_cpus) |
450 | 4b48bf05 | Blue Swirl | { |
451 | 4b48bf05 | Blue Swirl | DeviceState *dev; |
452 | 4b48bf05 | Blue Swirl | SysBusDevice *s; |
453 | 4b48bf05 | Blue Swirl | unsigned int i; |
454 | 4b48bf05 | Blue Swirl | |
455 | 4b48bf05 | Blue Swirl | dev = qdev_create(NULL, "slavio_timer"); |
456 | 4b48bf05 | Blue Swirl | qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
|
457 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
458 | 4b48bf05 | Blue Swirl | s = sysbus_from_qdev(dev); |
459 | 4b48bf05 | Blue Swirl | sysbus_connect_irq(s, 0, master_irq);
|
460 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
|
461 | 4b48bf05 | Blue Swirl | |
462 | 4b48bf05 | Blue Swirl | for (i = 0; i < MAX_CPUS; i++) { |
463 | c227f099 | Anthony Liguori | sysbus_mmio_map(s, i + 1, addr + (target_phys_addr_t)CPU_TIMER_OFFSET(i));
|
464 | 4b48bf05 | Blue Swirl | sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
|
465 | 4b48bf05 | Blue Swirl | } |
466 | 4b48bf05 | Blue Swirl | } |
467 | 4b48bf05 | Blue Swirl | |
468 | 4b48bf05 | Blue Swirl | #define MISC_LEDS 0x01600000 |
469 | 4b48bf05 | Blue Swirl | #define MISC_CFG 0x01800000 |
470 | 4b48bf05 | Blue Swirl | #define MISC_DIAG 0x01a00000 |
471 | 4b48bf05 | Blue Swirl | #define MISC_MDM 0x01b00000 |
472 | 4b48bf05 | Blue Swirl | #define MISC_SYS 0x01f00000 |
473 | 4b48bf05 | Blue Swirl | |
474 | c227f099 | Anthony Liguori | static void slavio_misc_init(target_phys_addr_t base, |
475 | c227f099 | Anthony Liguori | target_phys_addr_t aux1_base, |
476 | c227f099 | Anthony Liguori | target_phys_addr_t aux2_base, qemu_irq irq, |
477 | b2b6f6ec | Blue Swirl | qemu_irq fdc_tc) |
478 | 4b48bf05 | Blue Swirl | { |
479 | 4b48bf05 | Blue Swirl | DeviceState *dev; |
480 | 4b48bf05 | Blue Swirl | SysBusDevice *s; |
481 | 4b48bf05 | Blue Swirl | |
482 | 4b48bf05 | Blue Swirl | dev = qdev_create(NULL, "slavio_misc"); |
483 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
484 | 4b48bf05 | Blue Swirl | s = sysbus_from_qdev(dev); |
485 | 4b48bf05 | Blue Swirl | if (base) {
|
486 | 4b48bf05 | Blue Swirl | /* 8 bit registers */
|
487 | 4b48bf05 | Blue Swirl | /* Slavio control */
|
488 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 0, base + MISC_CFG);
|
489 | 4b48bf05 | Blue Swirl | /* Diagnostics */
|
490 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 1, base + MISC_DIAG);
|
491 | 4b48bf05 | Blue Swirl | /* Modem control */
|
492 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 2, base + MISC_MDM);
|
493 | 4b48bf05 | Blue Swirl | /* 16 bit registers */
|
494 | 4b48bf05 | Blue Swirl | /* ss600mp diag LEDs */
|
495 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 3, base + MISC_LEDS);
|
496 | 4b48bf05 | Blue Swirl | /* 32 bit registers */
|
497 | 4b48bf05 | Blue Swirl | /* System control */
|
498 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 4, base + MISC_SYS);
|
499 | 4b48bf05 | Blue Swirl | } |
500 | 4b48bf05 | Blue Swirl | if (aux1_base) {
|
501 | 4b48bf05 | Blue Swirl | /* AUX 1 (Misc System Functions) */
|
502 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 5, aux1_base);
|
503 | 4b48bf05 | Blue Swirl | } |
504 | 4b48bf05 | Blue Swirl | if (aux2_base) {
|
505 | 4b48bf05 | Blue Swirl | /* AUX 2 (Software Powerdown Control) */
|
506 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 6, aux2_base);
|
507 | 4b48bf05 | Blue Swirl | } |
508 | 4b48bf05 | Blue Swirl | sysbus_connect_irq(s, 0, irq);
|
509 | 4b48bf05 | Blue Swirl | sysbus_connect_irq(s, 1, fdc_tc);
|
510 | d9c32310 | Blue Swirl | qemu_system_powerdown = qdev_get_gpio_in(dev, 0);
|
511 | 4b48bf05 | Blue Swirl | } |
512 | 4b48bf05 | Blue Swirl | |
513 | c227f099 | Anthony Liguori | static void ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version) |
514 | 4b48bf05 | Blue Swirl | { |
515 | 4b48bf05 | Blue Swirl | DeviceState *dev; |
516 | 4b48bf05 | Blue Swirl | SysBusDevice *s; |
517 | 4b48bf05 | Blue Swirl | |
518 | 4b48bf05 | Blue Swirl | dev = qdev_create(NULL, "eccmemctl"); |
519 | 4b48bf05 | Blue Swirl | qdev_prop_set_uint32(dev, "version", version);
|
520 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
521 | 4b48bf05 | Blue Swirl | s = sysbus_from_qdev(dev); |
522 | 4b48bf05 | Blue Swirl | sysbus_connect_irq(s, 0, irq);
|
523 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 0, base);
|
524 | 4b48bf05 | Blue Swirl | if (version == 0) { // SS-600MP only |
525 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 1, base + 0x1000); |
526 | 4b48bf05 | Blue Swirl | } |
527 | 4b48bf05 | Blue Swirl | } |
528 | 4b48bf05 | Blue Swirl | |
529 | c227f099 | Anthony Liguori | static void apc_init(target_phys_addr_t power_base, qemu_irq cpu_halt) |
530 | 4b48bf05 | Blue Swirl | { |
531 | 4b48bf05 | Blue Swirl | DeviceState *dev; |
532 | 4b48bf05 | Blue Swirl | SysBusDevice *s; |
533 | 4b48bf05 | Blue Swirl | |
534 | 4b48bf05 | Blue Swirl | dev = qdev_create(NULL, "apc"); |
535 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
536 | 4b48bf05 | Blue Swirl | s = sysbus_from_qdev(dev); |
537 | 4b48bf05 | Blue Swirl | /* Power management (APC) XXX: not a Slavio device */
|
538 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 0, power_base);
|
539 | 4b48bf05 | Blue Swirl | sysbus_connect_irq(s, 0, cpu_halt);
|
540 | 4b48bf05 | Blue Swirl | } |
541 | 4b48bf05 | Blue Swirl | |
542 | c227f099 | Anthony Liguori | static void tcx_init(target_phys_addr_t addr, int vram_size, int width, |
543 | 4b48bf05 | Blue Swirl | int height, int depth) |
544 | 4b48bf05 | Blue Swirl | { |
545 | 4b48bf05 | Blue Swirl | DeviceState *dev; |
546 | 4b48bf05 | Blue Swirl | SysBusDevice *s; |
547 | 4b48bf05 | Blue Swirl | |
548 | 4b48bf05 | Blue Swirl | dev = qdev_create(NULL, "SUNW,tcx"); |
549 | 4b48bf05 | Blue Swirl | qdev_prop_set_taddr(dev, "addr", addr);
|
550 | 4b48bf05 | Blue Swirl | qdev_prop_set_uint32(dev, "vram_size", vram_size);
|
551 | 4b48bf05 | Blue Swirl | qdev_prop_set_uint16(dev, "width", width);
|
552 | 4b48bf05 | Blue Swirl | qdev_prop_set_uint16(dev, "height", height);
|
553 | 4b48bf05 | Blue Swirl | qdev_prop_set_uint16(dev, "depth", depth);
|
554 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
555 | 4b48bf05 | Blue Swirl | s = sysbus_from_qdev(dev); |
556 | 4b48bf05 | Blue Swirl | /* 8-bit plane */
|
557 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 0, addr + 0x00800000ULL); |
558 | 4b48bf05 | Blue Swirl | /* DAC */
|
559 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 1, addr + 0x00200000ULL); |
560 | 4b48bf05 | Blue Swirl | /* TEC (dummy) */
|
561 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 2, addr + 0x00700000ULL); |
562 | 4b48bf05 | Blue Swirl | /* THC 24 bit: NetBSD writes here even with 8-bit display: dummy */
|
563 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 3, addr + 0x00301000ULL); |
564 | 4b48bf05 | Blue Swirl | if (depth == 24) { |
565 | 4b48bf05 | Blue Swirl | /* 24-bit plane */
|
566 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 4, addr + 0x02000000ULL); |
567 | 4b48bf05 | Blue Swirl | /* Control plane */
|
568 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 5, addr + 0x0a000000ULL); |
569 | 4b48bf05 | Blue Swirl | } else {
|
570 | 4b48bf05 | Blue Swirl | /* THC 8 bit (dummy) */
|
571 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 4, addr + 0x00300000ULL); |
572 | 4b48bf05 | Blue Swirl | } |
573 | 4b48bf05 | Blue Swirl | } |
574 | 4b48bf05 | Blue Swirl | |
575 | 325f2747 | Blue Swirl | /* NCR89C100/MACIO Internal ID register */
|
576 | 325f2747 | Blue Swirl | static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 }; |
577 | 325f2747 | Blue Swirl | |
578 | c227f099 | Anthony Liguori | static void idreg_init(target_phys_addr_t addr) |
579 | 325f2747 | Blue Swirl | { |
580 | 325f2747 | Blue Swirl | DeviceState *dev; |
581 | 325f2747 | Blue Swirl | SysBusDevice *s; |
582 | 325f2747 | Blue Swirl | |
583 | 325f2747 | Blue Swirl | dev = qdev_create(NULL, "macio_idreg"); |
584 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
585 | 325f2747 | Blue Swirl | s = sysbus_from_qdev(dev); |
586 | 325f2747 | Blue Swirl | |
587 | 325f2747 | Blue Swirl | sysbus_mmio_map(s, 0, addr);
|
588 | 325f2747 | Blue Swirl | cpu_physical_memory_write_rom(addr, idreg_data, sizeof(idreg_data));
|
589 | 325f2747 | Blue Swirl | } |
590 | 325f2747 | Blue Swirl | |
591 | 81a322d4 | Gerd Hoffmann | static int idreg_init1(SysBusDevice *dev) |
592 | 325f2747 | Blue Swirl | { |
593 | c227f099 | Anthony Liguori | ram_addr_t idreg_offset; |
594 | 325f2747 | Blue Swirl | |
595 | 1724f049 | Alex Williamson | idreg_offset = qemu_ram_alloc(NULL, "sun4m.idreg", sizeof(idreg_data)); |
596 | 325f2747 | Blue Swirl | sysbus_init_mmio(dev, sizeof(idreg_data), idreg_offset | IO_MEM_ROM);
|
597 | 81a322d4 | Gerd Hoffmann | return 0; |
598 | 325f2747 | Blue Swirl | } |
599 | 325f2747 | Blue Swirl | |
600 | 325f2747 | Blue Swirl | static SysBusDeviceInfo idreg_info = {
|
601 | 325f2747 | Blue Swirl | .init = idreg_init1, |
602 | 325f2747 | Blue Swirl | .qdev.name = "macio_idreg",
|
603 | 325f2747 | Blue Swirl | .qdev.size = sizeof(SysBusDevice),
|
604 | 325f2747 | Blue Swirl | }; |
605 | 325f2747 | Blue Swirl | |
606 | 325f2747 | Blue Swirl | static void idreg_register_devices(void) |
607 | 325f2747 | Blue Swirl | { |
608 | 325f2747 | Blue Swirl | sysbus_register_withprop(&idreg_info); |
609 | 325f2747 | Blue Swirl | } |
610 | 325f2747 | Blue Swirl | |
611 | 325f2747 | Blue Swirl | device_init(idreg_register_devices); |
612 | 325f2747 | Blue Swirl | |
613 | c5de386a | Artyom Tarasenko | /* SS-5 TCX AFX register */
|
614 | c5de386a | Artyom Tarasenko | static void afx_init(target_phys_addr_t addr) |
615 | c5de386a | Artyom Tarasenko | { |
616 | c5de386a | Artyom Tarasenko | DeviceState *dev; |
617 | c5de386a | Artyom Tarasenko | SysBusDevice *s; |
618 | c5de386a | Artyom Tarasenko | |
619 | c5de386a | Artyom Tarasenko | dev = qdev_create(NULL, "tcx_afx"); |
620 | c5de386a | Artyom Tarasenko | qdev_init_nofail(dev); |
621 | c5de386a | Artyom Tarasenko | s = sysbus_from_qdev(dev); |
622 | c5de386a | Artyom Tarasenko | |
623 | c5de386a | Artyom Tarasenko | sysbus_mmio_map(s, 0, addr);
|
624 | c5de386a | Artyom Tarasenko | } |
625 | c5de386a | Artyom Tarasenko | |
626 | c5de386a | Artyom Tarasenko | static int afx_init1(SysBusDevice *dev) |
627 | c5de386a | Artyom Tarasenko | { |
628 | c5de386a | Artyom Tarasenko | ram_addr_t afx_offset; |
629 | c5de386a | Artyom Tarasenko | |
630 | 1724f049 | Alex Williamson | afx_offset = qemu_ram_alloc(NULL, "sun4m.afx", 4); |
631 | c5de386a | Artyom Tarasenko | sysbus_init_mmio(dev, 4, afx_offset | IO_MEM_RAM);
|
632 | c5de386a | Artyom Tarasenko | return 0; |
633 | c5de386a | Artyom Tarasenko | } |
634 | c5de386a | Artyom Tarasenko | |
635 | c5de386a | Artyom Tarasenko | static SysBusDeviceInfo afx_info = {
|
636 | c5de386a | Artyom Tarasenko | .init = afx_init1, |
637 | c5de386a | Artyom Tarasenko | .qdev.name = "tcx_afx",
|
638 | c5de386a | Artyom Tarasenko | .qdev.size = sizeof(SysBusDevice),
|
639 | c5de386a | Artyom Tarasenko | }; |
640 | c5de386a | Artyom Tarasenko | |
641 | c5de386a | Artyom Tarasenko | static void afx_register_devices(void) |
642 | c5de386a | Artyom Tarasenko | { |
643 | c5de386a | Artyom Tarasenko | sysbus_register_withprop(&afx_info); |
644 | c5de386a | Artyom Tarasenko | } |
645 | c5de386a | Artyom Tarasenko | |
646 | c5de386a | Artyom Tarasenko | device_init(afx_register_devices); |
647 | c5de386a | Artyom Tarasenko | |
648 | f48f6569 | Blue Swirl | /* Boot PROM (OpenBIOS) */
|
649 | 409dbce5 | Aurelien Jarno | static uint64_t translate_prom_address(void *opaque, uint64_t addr) |
650 | 409dbce5 | Aurelien Jarno | { |
651 | 409dbce5 | Aurelien Jarno | target_phys_addr_t *base_addr = (target_phys_addr_t *)opaque; |
652 | 409dbce5 | Aurelien Jarno | return addr + *base_addr - PROM_VADDR;
|
653 | 409dbce5 | Aurelien Jarno | } |
654 | 409dbce5 | Aurelien Jarno | |
655 | c227f099 | Anthony Liguori | static void prom_init(target_phys_addr_t addr, const char *bios_name) |
656 | f48f6569 | Blue Swirl | { |
657 | f48f6569 | Blue Swirl | DeviceState *dev; |
658 | f48f6569 | Blue Swirl | SysBusDevice *s; |
659 | f48f6569 | Blue Swirl | char *filename;
|
660 | f48f6569 | Blue Swirl | int ret;
|
661 | f48f6569 | Blue Swirl | |
662 | f48f6569 | Blue Swirl | dev = qdev_create(NULL, "openprom"); |
663 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
664 | f48f6569 | Blue Swirl | s = sysbus_from_qdev(dev); |
665 | f48f6569 | Blue Swirl | |
666 | f48f6569 | Blue Swirl | sysbus_mmio_map(s, 0, addr);
|
667 | f48f6569 | Blue Swirl | |
668 | f48f6569 | Blue Swirl | /* load boot prom */
|
669 | f48f6569 | Blue Swirl | if (bios_name == NULL) { |
670 | f48f6569 | Blue Swirl | bios_name = PROM_FILENAME; |
671 | f48f6569 | Blue Swirl | } |
672 | f48f6569 | Blue Swirl | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
673 | f48f6569 | Blue Swirl | if (filename) {
|
674 | 409dbce5 | Aurelien Jarno | ret = load_elf(filename, translate_prom_address, &addr, NULL,
|
675 | 409dbce5 | Aurelien Jarno | NULL, NULL, 1, ELF_MACHINE, 0); |
676 | f48f6569 | Blue Swirl | if (ret < 0 || ret > PROM_SIZE_MAX) { |
677 | f48f6569 | Blue Swirl | ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); |
678 | f48f6569 | Blue Swirl | } |
679 | f48f6569 | Blue Swirl | qemu_free(filename); |
680 | f48f6569 | Blue Swirl | } else {
|
681 | f48f6569 | Blue Swirl | ret = -1;
|
682 | f48f6569 | Blue Swirl | } |
683 | f48f6569 | Blue Swirl | if (ret < 0 || ret > PROM_SIZE_MAX) { |
684 | f48f6569 | Blue Swirl | fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
|
685 | f48f6569 | Blue Swirl | exit(1);
|
686 | f48f6569 | Blue Swirl | } |
687 | f48f6569 | Blue Swirl | } |
688 | f48f6569 | Blue Swirl | |
689 | 81a322d4 | Gerd Hoffmann | static int prom_init1(SysBusDevice *dev) |
690 | f48f6569 | Blue Swirl | { |
691 | c227f099 | Anthony Liguori | ram_addr_t prom_offset; |
692 | f48f6569 | Blue Swirl | |
693 | 1724f049 | Alex Williamson | prom_offset = qemu_ram_alloc(NULL, "sun4m.prom", PROM_SIZE_MAX); |
694 | f48f6569 | Blue Swirl | sysbus_init_mmio(dev, PROM_SIZE_MAX, prom_offset | IO_MEM_ROM); |
695 | 81a322d4 | Gerd Hoffmann | return 0; |
696 | f48f6569 | Blue Swirl | } |
697 | f48f6569 | Blue Swirl | |
698 | f48f6569 | Blue Swirl | static SysBusDeviceInfo prom_info = {
|
699 | f48f6569 | Blue Swirl | .init = prom_init1, |
700 | f48f6569 | Blue Swirl | .qdev.name = "openprom",
|
701 | f48f6569 | Blue Swirl | .qdev.size = sizeof(SysBusDevice),
|
702 | ee6847d1 | Gerd Hoffmann | .qdev.props = (Property[]) { |
703 | ee6847d1 | Gerd Hoffmann | {/* end of property list */}
|
704 | f48f6569 | Blue Swirl | } |
705 | f48f6569 | Blue Swirl | }; |
706 | f48f6569 | Blue Swirl | |
707 | f48f6569 | Blue Swirl | static void prom_register_devices(void) |
708 | f48f6569 | Blue Swirl | { |
709 | f48f6569 | Blue Swirl | sysbus_register_withprop(&prom_info); |
710 | f48f6569 | Blue Swirl | } |
711 | f48f6569 | Blue Swirl | |
712 | f48f6569 | Blue Swirl | device_init(prom_register_devices); |
713 | f48f6569 | Blue Swirl | |
714 | ee6847d1 | Gerd Hoffmann | typedef struct RamDevice |
715 | ee6847d1 | Gerd Hoffmann | { |
716 | ee6847d1 | Gerd Hoffmann | SysBusDevice busdev; |
717 | 04843626 | Blue Swirl | uint64_t size; |
718 | ee6847d1 | Gerd Hoffmann | } RamDevice; |
719 | ee6847d1 | Gerd Hoffmann | |
720 | a350db85 | Blue Swirl | /* System RAM */
|
721 | 81a322d4 | Gerd Hoffmann | static int ram_init1(SysBusDevice *dev) |
722 | a350db85 | Blue Swirl | { |
723 | c227f099 | Anthony Liguori | ram_addr_t RAM_size, ram_offset; |
724 | ee6847d1 | Gerd Hoffmann | RamDevice *d = FROM_SYSBUS(RamDevice, dev); |
725 | a350db85 | Blue Swirl | |
726 | ee6847d1 | Gerd Hoffmann | RAM_size = d->size; |
727 | a350db85 | Blue Swirl | |
728 | 1724f049 | Alex Williamson | ram_offset = qemu_ram_alloc(NULL, "sun4m.ram", RAM_size); |
729 | a350db85 | Blue Swirl | sysbus_init_mmio(dev, RAM_size, ram_offset); |
730 | 81a322d4 | Gerd Hoffmann | return 0; |
731 | a350db85 | Blue Swirl | } |
732 | a350db85 | Blue Swirl | |
733 | c227f099 | Anthony Liguori | static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size, |
734 | a350db85 | Blue Swirl | uint64_t max_mem) |
735 | a350db85 | Blue Swirl | { |
736 | a350db85 | Blue Swirl | DeviceState *dev; |
737 | a350db85 | Blue Swirl | SysBusDevice *s; |
738 | ee6847d1 | Gerd Hoffmann | RamDevice *d; |
739 | a350db85 | Blue Swirl | |
740 | a350db85 | Blue Swirl | /* allocate RAM */
|
741 | a350db85 | Blue Swirl | if ((uint64_t)RAM_size > max_mem) {
|
742 | a350db85 | Blue Swirl | fprintf(stderr, |
743 | a350db85 | Blue Swirl | "qemu: Too much memory for this machine: %d, maximum %d\n",
|
744 | a350db85 | Blue Swirl | (unsigned int)(RAM_size / (1024 * 1024)), |
745 | a350db85 | Blue Swirl | (unsigned int)(max_mem / (1024 * 1024))); |
746 | a350db85 | Blue Swirl | exit(1);
|
747 | a350db85 | Blue Swirl | } |
748 | a350db85 | Blue Swirl | dev = qdev_create(NULL, "memory"); |
749 | a350db85 | Blue Swirl | s = sysbus_from_qdev(dev); |
750 | a350db85 | Blue Swirl | |
751 | ee6847d1 | Gerd Hoffmann | d = FROM_SYSBUS(RamDevice, s); |
752 | ee6847d1 | Gerd Hoffmann | d->size = RAM_size; |
753 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
754 | ee6847d1 | Gerd Hoffmann | |
755 | a350db85 | Blue Swirl | sysbus_mmio_map(s, 0, addr);
|
756 | a350db85 | Blue Swirl | } |
757 | a350db85 | Blue Swirl | |
758 | a350db85 | Blue Swirl | static SysBusDeviceInfo ram_info = {
|
759 | a350db85 | Blue Swirl | .init = ram_init1, |
760 | a350db85 | Blue Swirl | .qdev.name = "memory",
|
761 | ee6847d1 | Gerd Hoffmann | .qdev.size = sizeof(RamDevice),
|
762 | ee6847d1 | Gerd Hoffmann | .qdev.props = (Property[]) { |
763 | c885159a | Gerd Hoffmann | DEFINE_PROP_UINT64("size", RamDevice, size, 0), |
764 | c885159a | Gerd Hoffmann | DEFINE_PROP_END_OF_LIST(), |
765 | a350db85 | Blue Swirl | } |
766 | a350db85 | Blue Swirl | }; |
767 | a350db85 | Blue Swirl | |
768 | a350db85 | Blue Swirl | static void ram_register_devices(void) |
769 | a350db85 | Blue Swirl | { |
770 | a350db85 | Blue Swirl | sysbus_register_withprop(&ram_info); |
771 | a350db85 | Blue Swirl | } |
772 | a350db85 | Blue Swirl | |
773 | a350db85 | Blue Swirl | device_init(ram_register_devices); |
774 | a350db85 | Blue Swirl | |
775 | 89835363 | Blue Swirl | static void cpu_devinit(const char *cpu_model, unsigned int id, |
776 | 89835363 | Blue Swirl | uint64_t prom_addr, qemu_irq **cpu_irqs) |
777 | 666713c0 | Blue Swirl | { |
778 | 666713c0 | Blue Swirl | CPUState *env; |
779 | 666713c0 | Blue Swirl | |
780 | 666713c0 | Blue Swirl | env = cpu_init(cpu_model); |
781 | 666713c0 | Blue Swirl | if (!env) {
|
782 | 666713c0 | Blue Swirl | fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
|
783 | 666713c0 | Blue Swirl | exit(1);
|
784 | 666713c0 | Blue Swirl | } |
785 | 666713c0 | Blue Swirl | |
786 | 666713c0 | Blue Swirl | cpu_sparc_set_id(env, id); |
787 | 666713c0 | Blue Swirl | if (id == 0) { |
788 | 666713c0 | Blue Swirl | qemu_register_reset(main_cpu_reset, env); |
789 | 666713c0 | Blue Swirl | } else {
|
790 | 666713c0 | Blue Swirl | qemu_register_reset(secondary_cpu_reset, env); |
791 | 666713c0 | Blue Swirl | env->halted = 1;
|
792 | 666713c0 | Blue Swirl | } |
793 | 666713c0 | Blue Swirl | *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS); |
794 | 666713c0 | Blue Swirl | env->prom_addr = prom_addr; |
795 | 666713c0 | Blue Swirl | } |
796 | 666713c0 | Blue Swirl | |
797 | c227f099 | Anthony Liguori | static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size, |
798 | 3ebf5aaf | blueswir1 | const char *boot_device, |
799 | 3023f332 | aliguori | const char *kernel_filename, |
800 | 3ebf5aaf | blueswir1 | const char *kernel_cmdline, |
801 | 3ebf5aaf | blueswir1 | const char *initrd_filename, const char *cpu_model) |
802 | 420557e8 | bellard | { |
803 | 713c45fa | bellard | unsigned int i; |
804 | cfb9de9c | Paul Brook | void *iommu, *espdma, *ledma, *nvram;
|
805 | a1961a4b | Blue Swirl | qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS],
|
806 | 6f6260c7 | Blue Swirl | espdma_irq, ledma_irq; |
807 | 74ff8d90 | Blue Swirl | qemu_irq esp_reset; |
808 | 2582cfa0 | Blue Swirl | qemu_irq fdc_tc; |
809 | 6d0c293d | blueswir1 | qemu_irq *cpu_halt; |
810 | 5c6602c5 | blueswir1 | unsigned long kernel_size; |
811 | fd8014e1 | Gerd Hoffmann | DriveInfo *fd[MAX_FD]; |
812 | 3cce6243 | blueswir1 | void *fw_cfg;
|
813 | 420557e8 | bellard | |
814 | ba3c64fb | bellard | /* init CPUs */
|
815 | 3ebf5aaf | blueswir1 | if (!cpu_model)
|
816 | 3ebf5aaf | blueswir1 | cpu_model = hwdef->default_cpu_model; |
817 | b3a23197 | blueswir1 | |
818 | ba3c64fb | bellard | for(i = 0; i < smp_cpus; i++) { |
819 | 89835363 | Blue Swirl | cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]); |
820 | ba3c64fb | bellard | } |
821 | b3a23197 | blueswir1 | |
822 | b3a23197 | blueswir1 | for (i = smp_cpus; i < MAX_CPUS; i++)
|
823 | b3a23197 | blueswir1 | cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
|
824 | b3a23197 | blueswir1 | |
825 | 3ebf5aaf | blueswir1 | |
826 | 3ebf5aaf | blueswir1 | /* set up devices */
|
827 | a350db85 | Blue Swirl | ram_init(0, RAM_size, hwdef->max_mem);
|
828 | 676d9b9b | Artyom Tarasenko | /* models without ECC don't trap when missing ram is accessed */
|
829 | 676d9b9b | Artyom Tarasenko | if (!hwdef->ecc_base) {
|
830 | 676d9b9b | Artyom Tarasenko | empty_slot_init(RAM_size, hwdef->max_mem - RAM_size); |
831 | 676d9b9b | Artyom Tarasenko | } |
832 | a350db85 | Blue Swirl | |
833 | f48f6569 | Blue Swirl | prom_init(hwdef->slavio_base, bios_name); |
834 | f48f6569 | Blue Swirl | |
835 | d453c2c3 | Blue Swirl | slavio_intctl = slavio_intctl_init(hwdef->intctl_base, |
836 | d453c2c3 | Blue Swirl | hwdef->intctl_base + 0x10000ULL,
|
837 | 462eda24 | Blue Swirl | cpu_irqs); |
838 | a1961a4b | Blue Swirl | |
839 | a1961a4b | Blue Swirl | for (i = 0; i < 32; i++) { |
840 | d453c2c3 | Blue Swirl | slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i); |
841 | a1961a4b | Blue Swirl | } |
842 | a1961a4b | Blue Swirl | for (i = 0; i < MAX_CPUS; i++) { |
843 | d453c2c3 | Blue Swirl | slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
|
844 | a1961a4b | Blue Swirl | } |
845 | b3a23197 | blueswir1 | |
846 | fe096129 | blueswir1 | if (hwdef->idreg_base) {
|
847 | 325f2747 | Blue Swirl | idreg_init(hwdef->idreg_base); |
848 | 4c2485de | blueswir1 | } |
849 | 4c2485de | blueswir1 | |
850 | c5de386a | Artyom Tarasenko | if (hwdef->afx_base) {
|
851 | c5de386a | Artyom Tarasenko | afx_init(hwdef->afx_base); |
852 | c5de386a | Artyom Tarasenko | } |
853 | c5de386a | Artyom Tarasenko | |
854 | ff403da6 | blueswir1 | iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version, |
855 | c533e0b3 | Blue Swirl | slavio_irq[30]);
|
856 | ff403da6 | blueswir1 | |
857 | 3386376c | Artyom Tarasenko | if (hwdef->iommu_pad_base) {
|
858 | 3386376c | Artyom Tarasenko | /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased.
|
859 | 3386376c | Artyom Tarasenko | Software shouldn't use aliased addresses, neither should it crash
|
860 | 3386376c | Artyom Tarasenko | when does. Using empty_slot instead of aliasing can help with
|
861 | 3386376c | Artyom Tarasenko | debugging such accesses */
|
862 | 3386376c | Artyom Tarasenko | empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len); |
863 | 3386376c | Artyom Tarasenko | } |
864 | 3386376c | Artyom Tarasenko | |
865 | c533e0b3 | Blue Swirl | espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[18],
|
866 | 74ff8d90 | Blue Swirl | iommu, &espdma_irq); |
867 | 2d069bab | blueswir1 | |
868 | 5aca8c3b | blueswir1 | ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
|
869 | 74ff8d90 | Blue Swirl | slavio_irq[16], iommu, &ledma_irq);
|
870 | ba3c64fb | bellard | |
871 | eee0b836 | blueswir1 | if (graphic_depth != 8 && graphic_depth != 24) { |
872 | eee0b836 | blueswir1 | fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
|
873 | eee0b836 | blueswir1 | exit (1);
|
874 | eee0b836 | blueswir1 | } |
875 | d95d8f1c | Blue Swirl | tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
|
876 | dc828ca1 | pbrook | graphic_depth); |
877 | dbe06e18 | blueswir1 | |
878 | 74ff8d90 | Blue Swirl | lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
|
879 | dbe06e18 | blueswir1 | |
880 | d95d8f1c | Blue Swirl | nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 8); |
881 | 81732d19 | blueswir1 | |
882 | c533e0b3 | Blue Swirl | slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
|
883 | 81732d19 | blueswir1 | |
884 | c533e0b3 | Blue Swirl | slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14],
|
885 | 993fbfdb | Anthony Liguori | display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
|
886 | b81b3b10 | bellard | // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
|
887 | b81b3b10 | bellard | // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
|
888 | c533e0b3 | Blue Swirl | escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15], |
889 | aeeb69c7 | aurel32 | serial_hds[0], serial_hds[1], ESCC_CLOCK, 1); |
890 | 741402f9 | blueswir1 | |
891 | 6d0c293d | blueswir1 | cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1); |
892 | b2b6f6ec | Blue Swirl | slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base, |
893 | b2b6f6ec | Blue Swirl | slavio_irq[30], fdc_tc);
|
894 | b2b6f6ec | Blue Swirl | |
895 | 2582cfa0 | Blue Swirl | if (hwdef->apc_base) {
|
896 | 2582cfa0 | Blue Swirl | apc_init(hwdef->apc_base, cpu_halt[0]);
|
897 | 2582cfa0 | Blue Swirl | } |
898 | 2be17ebd | blueswir1 | |
899 | fe096129 | blueswir1 | if (hwdef->fd_base) {
|
900 | e4bcb14c | ths | /* there is zero or one floppy drive */
|
901 | 309e60bd | blueswir1 | memset(fd, 0, sizeof(fd)); |
902 | fd8014e1 | Gerd Hoffmann | fd[0] = drive_get(IF_FLOPPY, 0, 0); |
903 | c533e0b3 | Blue Swirl | sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
|
904 | 2582cfa0 | Blue Swirl | &fdc_tc); |
905 | e4bcb14c | ths | } |
906 | e4bcb14c | ths | |
907 | e4bcb14c | ths | if (drive_get_max_bus(IF_SCSI) > 0) { |
908 | e4bcb14c | ths | fprintf(stderr, "qemu: too many SCSI bus\n");
|
909 | e4bcb14c | ths | exit(1);
|
910 | e4bcb14c | ths | } |
911 | e4bcb14c | ths | |
912 | 74ff8d90 | Blue Swirl | esp_reset = qdev_get_gpio_in(espdma, 0);
|
913 | cfb9de9c | Paul Brook | esp_init(hwdef->esp_base, 2,
|
914 | cfb9de9c | Paul Brook | espdma_memory_read, espdma_memory_write, |
915 | 74ff8d90 | Blue Swirl | espdma, espdma_irq, &esp_reset); |
916 | 74ff8d90 | Blue Swirl | |
917 | f1587550 | ths | |
918 | fa28ec52 | Blue Swirl | if (hwdef->cs_base) {
|
919 | fa28ec52 | Blue Swirl | sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
|
920 | c533e0b3 | Blue Swirl | slavio_irq[5]);
|
921 | fa28ec52 | Blue Swirl | } |
922 | b3ceef24 | blueswir1 | |
923 | 293f78bc | blueswir1 | kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename, |
924 | 293f78bc | blueswir1 | RAM_size); |
925 | 36cd9210 | blueswir1 | |
926 | 36cd9210 | blueswir1 | nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
|
927 | b3ceef24 | blueswir1 | boot_device, RAM_size, kernel_size, graphic_width, |
928 | 905fdcb5 | blueswir1 | graphic_height, graphic_depth, hwdef->nvram_machine_id, |
929 | 905fdcb5 | blueswir1 | "Sun4m");
|
930 | 7eb0c8e8 | blueswir1 | |
931 | fe096129 | blueswir1 | if (hwdef->ecc_base)
|
932 | c533e0b3 | Blue Swirl | ecc_init(hwdef->ecc_base, slavio_irq[28],
|
933 | e42c20b4 | blueswir1 | hwdef->ecc_version); |
934 | 3cce6243 | blueswir1 | |
935 | 3cce6243 | blueswir1 | fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2); |
936 | 3cce6243 | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
|
937 | 905fdcb5 | blueswir1 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
938 | 905fdcb5 | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); |
939 | fbfcf955 | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); |
940 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); |
941 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); |
942 | 513f789f | blueswir1 | if (kernel_cmdline) {
|
943 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); |
944 | 3c178e72 | Gerd Hoffmann | pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
|
945 | 6bb4ca57 | Blue Swirl | fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA, |
946 | 6bb4ca57 | Blue Swirl | (uint8_t*)strdup(kernel_cmdline), |
947 | 6bb4ca57 | Blue Swirl | strlen(kernel_cmdline) + 1);
|
948 | 513f789f | blueswir1 | } else {
|
949 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
|
950 | 513f789f | blueswir1 | } |
951 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); |
952 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used |
953 | 513f789f | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
|
954 | 513f789f | blueswir1 | qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); |
955 | 36cd9210 | blueswir1 | } |
956 | 36cd9210 | blueswir1 | |
957 | 905fdcb5 | blueswir1 | enum {
|
958 | 905fdcb5 | blueswir1 | ss2_id = 0,
|
959 | 905fdcb5 | blueswir1 | ss5_id = 32,
|
960 | 905fdcb5 | blueswir1 | vger_id, |
961 | 905fdcb5 | blueswir1 | lx_id, |
962 | 905fdcb5 | blueswir1 | ss4_id, |
963 | 905fdcb5 | blueswir1 | scls_id, |
964 | 905fdcb5 | blueswir1 | sbook_id, |
965 | 905fdcb5 | blueswir1 | ss10_id = 64,
|
966 | 905fdcb5 | blueswir1 | ss20_id, |
967 | 905fdcb5 | blueswir1 | ss600mp_id, |
968 | 905fdcb5 | blueswir1 | ss1000_id = 96,
|
969 | 905fdcb5 | blueswir1 | ss2000_id, |
970 | 905fdcb5 | blueswir1 | }; |
971 | 905fdcb5 | blueswir1 | |
972 | 8137cde8 | blueswir1 | static const struct sun4m_hwdef sun4m_hwdefs[] = { |
973 | 36cd9210 | blueswir1 | /* SS-5 */
|
974 | 36cd9210 | blueswir1 | { |
975 | 36cd9210 | blueswir1 | .iommu_base = 0x10000000,
|
976 | 3386376c | Artyom Tarasenko | .iommu_pad_base = 0x10004000,
|
977 | 3386376c | Artyom Tarasenko | .iommu_pad_len = 0x0fffb000,
|
978 | 36cd9210 | blueswir1 | .tcx_base = 0x50000000,
|
979 | 36cd9210 | blueswir1 | .cs_base = 0x6c000000,
|
980 | 384ccb5d | blueswir1 | .slavio_base = 0x70000000,
|
981 | 36cd9210 | blueswir1 | .ms_kb_base = 0x71000000,
|
982 | 36cd9210 | blueswir1 | .serial_base = 0x71100000,
|
983 | 36cd9210 | blueswir1 | .nvram_base = 0x71200000,
|
984 | 36cd9210 | blueswir1 | .fd_base = 0x71400000,
|
985 | 36cd9210 | blueswir1 | .counter_base = 0x71d00000,
|
986 | 36cd9210 | blueswir1 | .intctl_base = 0x71e00000,
|
987 | 4c2485de | blueswir1 | .idreg_base = 0x78000000,
|
988 | 36cd9210 | blueswir1 | .dma_base = 0x78400000,
|
989 | 36cd9210 | blueswir1 | .esp_base = 0x78800000,
|
990 | 36cd9210 | blueswir1 | .le_base = 0x78c00000,
|
991 | 127fc407 | blueswir1 | .apc_base = 0x6a000000,
|
992 | c5de386a | Artyom Tarasenko | .afx_base = 0x6e000000,
|
993 | 0019ad53 | blueswir1 | .aux1_base = 0x71900000,
|
994 | 0019ad53 | blueswir1 | .aux2_base = 0x71910000,
|
995 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x80,
|
996 | 905fdcb5 | blueswir1 | .machine_id = ss5_id, |
997 | cf3102ac | blueswir1 | .iommu_version = 0x05000000,
|
998 | 3ebf5aaf | blueswir1 | .max_mem = 0x10000000,
|
999 | 3ebf5aaf | blueswir1 | .default_cpu_model = "Fujitsu MB86904",
|
1000 | e0353fe2 | blueswir1 | }, |
1001 | e0353fe2 | blueswir1 | /* SS-10 */
|
1002 | e0353fe2 | blueswir1 | { |
1003 | 5dcb6b91 | blueswir1 | .iommu_base = 0xfe0000000ULL,
|
1004 | 5dcb6b91 | blueswir1 | .tcx_base = 0xe20000000ULL,
|
1005 | 5dcb6b91 | blueswir1 | .slavio_base = 0xff0000000ULL,
|
1006 | 5dcb6b91 | blueswir1 | .ms_kb_base = 0xff1000000ULL,
|
1007 | 5dcb6b91 | blueswir1 | .serial_base = 0xff1100000ULL,
|
1008 | 5dcb6b91 | blueswir1 | .nvram_base = 0xff1200000ULL,
|
1009 | 5dcb6b91 | blueswir1 | .fd_base = 0xff1700000ULL,
|
1010 | 5dcb6b91 | blueswir1 | .counter_base = 0xff1300000ULL,
|
1011 | 5dcb6b91 | blueswir1 | .intctl_base = 0xff1400000ULL,
|
1012 | 4c2485de | blueswir1 | .idreg_base = 0xef0000000ULL,
|
1013 | 5dcb6b91 | blueswir1 | .dma_base = 0xef0400000ULL,
|
1014 | 5dcb6b91 | blueswir1 | .esp_base = 0xef0800000ULL,
|
1015 | 5dcb6b91 | blueswir1 | .le_base = 0xef0c00000ULL,
|
1016 | 0019ad53 | blueswir1 | .apc_base = 0xefa000000ULL, // XXX should not exist |
1017 | 127fc407 | blueswir1 | .aux1_base = 0xff1800000ULL,
|
1018 | 127fc407 | blueswir1 | .aux2_base = 0xff1a01000ULL,
|
1019 | 7eb0c8e8 | blueswir1 | .ecc_base = 0xf00000000ULL,
|
1020 | 7eb0c8e8 | blueswir1 | .ecc_version = 0x10000000, // version 0, implementation 1 |
1021 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x72,
|
1022 | 905fdcb5 | blueswir1 | .machine_id = ss10_id, |
1023 | 7fbfb139 | blueswir1 | .iommu_version = 0x03000000,
|
1024 | 6ef05b95 | blueswir1 | .max_mem = 0xf00000000ULL,
|
1025 | 3ebf5aaf | blueswir1 | .default_cpu_model = "TI SuperSparc II",
|
1026 | 36cd9210 | blueswir1 | }, |
1027 | 6a3b9cc9 | blueswir1 | /* SS-600MP */
|
1028 | 6a3b9cc9 | blueswir1 | { |
1029 | 6a3b9cc9 | blueswir1 | .iommu_base = 0xfe0000000ULL,
|
1030 | 6a3b9cc9 | blueswir1 | .tcx_base = 0xe20000000ULL,
|
1031 | 6a3b9cc9 | blueswir1 | .slavio_base = 0xff0000000ULL,
|
1032 | 6a3b9cc9 | blueswir1 | .ms_kb_base = 0xff1000000ULL,
|
1033 | 6a3b9cc9 | blueswir1 | .serial_base = 0xff1100000ULL,
|
1034 | 6a3b9cc9 | blueswir1 | .nvram_base = 0xff1200000ULL,
|
1035 | 6a3b9cc9 | blueswir1 | .counter_base = 0xff1300000ULL,
|
1036 | 6a3b9cc9 | blueswir1 | .intctl_base = 0xff1400000ULL,
|
1037 | 6a3b9cc9 | blueswir1 | .dma_base = 0xef0081000ULL,
|
1038 | 6a3b9cc9 | blueswir1 | .esp_base = 0xef0080000ULL,
|
1039 | 6a3b9cc9 | blueswir1 | .le_base = 0xef0060000ULL,
|
1040 | 0019ad53 | blueswir1 | .apc_base = 0xefa000000ULL, // XXX should not exist |
1041 | 127fc407 | blueswir1 | .aux1_base = 0xff1800000ULL,
|
1042 | 127fc407 | blueswir1 | .aux2_base = 0xff1a01000ULL, // XXX should not exist |
1043 | 7eb0c8e8 | blueswir1 | .ecc_base = 0xf00000000ULL,
|
1044 | 7eb0c8e8 | blueswir1 | .ecc_version = 0x00000000, // version 0, implementation 0 |
1045 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x71,
|
1046 | 905fdcb5 | blueswir1 | .machine_id = ss600mp_id, |
1047 | 7fbfb139 | blueswir1 | .iommu_version = 0x01000000,
|
1048 | 6ef05b95 | blueswir1 | .max_mem = 0xf00000000ULL,
|
1049 | 3ebf5aaf | blueswir1 | .default_cpu_model = "TI SuperSparc II",
|
1050 | 6a3b9cc9 | blueswir1 | }, |
1051 | ae40972f | blueswir1 | /* SS-20 */
|
1052 | ae40972f | blueswir1 | { |
1053 | ae40972f | blueswir1 | .iommu_base = 0xfe0000000ULL,
|
1054 | ae40972f | blueswir1 | .tcx_base = 0xe20000000ULL,
|
1055 | ae40972f | blueswir1 | .slavio_base = 0xff0000000ULL,
|
1056 | ae40972f | blueswir1 | .ms_kb_base = 0xff1000000ULL,
|
1057 | ae40972f | blueswir1 | .serial_base = 0xff1100000ULL,
|
1058 | ae40972f | blueswir1 | .nvram_base = 0xff1200000ULL,
|
1059 | ae40972f | blueswir1 | .fd_base = 0xff1700000ULL,
|
1060 | ae40972f | blueswir1 | .counter_base = 0xff1300000ULL,
|
1061 | ae40972f | blueswir1 | .intctl_base = 0xff1400000ULL,
|
1062 | 4c2485de | blueswir1 | .idreg_base = 0xef0000000ULL,
|
1063 | ae40972f | blueswir1 | .dma_base = 0xef0400000ULL,
|
1064 | ae40972f | blueswir1 | .esp_base = 0xef0800000ULL,
|
1065 | ae40972f | blueswir1 | .le_base = 0xef0c00000ULL,
|
1066 | 0019ad53 | blueswir1 | .apc_base = 0xefa000000ULL, // XXX should not exist |
1067 | 577d8dd4 | blueswir1 | .aux1_base = 0xff1800000ULL,
|
1068 | 577d8dd4 | blueswir1 | .aux2_base = 0xff1a01000ULL,
|
1069 | ae40972f | blueswir1 | .ecc_base = 0xf00000000ULL,
|
1070 | ae40972f | blueswir1 | .ecc_version = 0x20000000, // version 0, implementation 2 |
1071 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x72,
|
1072 | 905fdcb5 | blueswir1 | .machine_id = ss20_id, |
1073 | ae40972f | blueswir1 | .iommu_version = 0x13000000,
|
1074 | 6ef05b95 | blueswir1 | .max_mem = 0xf00000000ULL,
|
1075 | ae40972f | blueswir1 | .default_cpu_model = "TI SuperSparc II",
|
1076 | ae40972f | blueswir1 | }, |
1077 | a526a31c | blueswir1 | /* Voyager */
|
1078 | a526a31c | blueswir1 | { |
1079 | a526a31c | blueswir1 | .iommu_base = 0x10000000,
|
1080 | a526a31c | blueswir1 | .tcx_base = 0x50000000,
|
1081 | a526a31c | blueswir1 | .slavio_base = 0x70000000,
|
1082 | a526a31c | blueswir1 | .ms_kb_base = 0x71000000,
|
1083 | a526a31c | blueswir1 | .serial_base = 0x71100000,
|
1084 | a526a31c | blueswir1 | .nvram_base = 0x71200000,
|
1085 | a526a31c | blueswir1 | .fd_base = 0x71400000,
|
1086 | a526a31c | blueswir1 | .counter_base = 0x71d00000,
|
1087 | a526a31c | blueswir1 | .intctl_base = 0x71e00000,
|
1088 | a526a31c | blueswir1 | .idreg_base = 0x78000000,
|
1089 | a526a31c | blueswir1 | .dma_base = 0x78400000,
|
1090 | a526a31c | blueswir1 | .esp_base = 0x78800000,
|
1091 | a526a31c | blueswir1 | .le_base = 0x78c00000,
|
1092 | a526a31c | blueswir1 | .apc_base = 0x71300000, // pmc |
1093 | a526a31c | blueswir1 | .aux1_base = 0x71900000,
|
1094 | a526a31c | blueswir1 | .aux2_base = 0x71910000,
|
1095 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x80,
|
1096 | 905fdcb5 | blueswir1 | .machine_id = vger_id, |
1097 | a526a31c | blueswir1 | .iommu_version = 0x05000000,
|
1098 | a526a31c | blueswir1 | .max_mem = 0x10000000,
|
1099 | a526a31c | blueswir1 | .default_cpu_model = "Fujitsu MB86904",
|
1100 | a526a31c | blueswir1 | }, |
1101 | a526a31c | blueswir1 | /* LX */
|
1102 | a526a31c | blueswir1 | { |
1103 | a526a31c | blueswir1 | .iommu_base = 0x10000000,
|
1104 | 3386376c | Artyom Tarasenko | .iommu_pad_base = 0x10004000,
|
1105 | 3386376c | Artyom Tarasenko | .iommu_pad_len = 0x0fffb000,
|
1106 | a526a31c | blueswir1 | .tcx_base = 0x50000000,
|
1107 | a526a31c | blueswir1 | .slavio_base = 0x70000000,
|
1108 | a526a31c | blueswir1 | .ms_kb_base = 0x71000000,
|
1109 | a526a31c | blueswir1 | .serial_base = 0x71100000,
|
1110 | a526a31c | blueswir1 | .nvram_base = 0x71200000,
|
1111 | a526a31c | blueswir1 | .fd_base = 0x71400000,
|
1112 | a526a31c | blueswir1 | .counter_base = 0x71d00000,
|
1113 | a526a31c | blueswir1 | .intctl_base = 0x71e00000,
|
1114 | a526a31c | blueswir1 | .idreg_base = 0x78000000,
|
1115 | a526a31c | blueswir1 | .dma_base = 0x78400000,
|
1116 | a526a31c | blueswir1 | .esp_base = 0x78800000,
|
1117 | a526a31c | blueswir1 | .le_base = 0x78c00000,
|
1118 | a526a31c | blueswir1 | .aux1_base = 0x71900000,
|
1119 | a526a31c | blueswir1 | .aux2_base = 0x71910000,
|
1120 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x80,
|
1121 | 905fdcb5 | blueswir1 | .machine_id = lx_id, |
1122 | a526a31c | blueswir1 | .iommu_version = 0x04000000,
|
1123 | a526a31c | blueswir1 | .max_mem = 0x10000000,
|
1124 | a526a31c | blueswir1 | .default_cpu_model = "TI MicroSparc I",
|
1125 | a526a31c | blueswir1 | }, |
1126 | a526a31c | blueswir1 | /* SS-4 */
|
1127 | a526a31c | blueswir1 | { |
1128 | a526a31c | blueswir1 | .iommu_base = 0x10000000,
|
1129 | a526a31c | blueswir1 | .tcx_base = 0x50000000,
|
1130 | a526a31c | blueswir1 | .cs_base = 0x6c000000,
|
1131 | a526a31c | blueswir1 | .slavio_base = 0x70000000,
|
1132 | a526a31c | blueswir1 | .ms_kb_base = 0x71000000,
|
1133 | a526a31c | blueswir1 | .serial_base = 0x71100000,
|
1134 | a526a31c | blueswir1 | .nvram_base = 0x71200000,
|
1135 | a526a31c | blueswir1 | .fd_base = 0x71400000,
|
1136 | a526a31c | blueswir1 | .counter_base = 0x71d00000,
|
1137 | a526a31c | blueswir1 | .intctl_base = 0x71e00000,
|
1138 | a526a31c | blueswir1 | .idreg_base = 0x78000000,
|
1139 | a526a31c | blueswir1 | .dma_base = 0x78400000,
|
1140 | a526a31c | blueswir1 | .esp_base = 0x78800000,
|
1141 | a526a31c | blueswir1 | .le_base = 0x78c00000,
|
1142 | a526a31c | blueswir1 | .apc_base = 0x6a000000,
|
1143 | a526a31c | blueswir1 | .aux1_base = 0x71900000,
|
1144 | a526a31c | blueswir1 | .aux2_base = 0x71910000,
|
1145 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x80,
|
1146 | 905fdcb5 | blueswir1 | .machine_id = ss4_id, |
1147 | a526a31c | blueswir1 | .iommu_version = 0x05000000,
|
1148 | a526a31c | blueswir1 | .max_mem = 0x10000000,
|
1149 | a526a31c | blueswir1 | .default_cpu_model = "Fujitsu MB86904",
|
1150 | a526a31c | blueswir1 | }, |
1151 | a526a31c | blueswir1 | /* SPARCClassic */
|
1152 | a526a31c | blueswir1 | { |
1153 | a526a31c | blueswir1 | .iommu_base = 0x10000000,
|
1154 | a526a31c | blueswir1 | .tcx_base = 0x50000000,
|
1155 | a526a31c | blueswir1 | .slavio_base = 0x70000000,
|
1156 | a526a31c | blueswir1 | .ms_kb_base = 0x71000000,
|
1157 | a526a31c | blueswir1 | .serial_base = 0x71100000,
|
1158 | a526a31c | blueswir1 | .nvram_base = 0x71200000,
|
1159 | a526a31c | blueswir1 | .fd_base = 0x71400000,
|
1160 | a526a31c | blueswir1 | .counter_base = 0x71d00000,
|
1161 | a526a31c | blueswir1 | .intctl_base = 0x71e00000,
|
1162 | a526a31c | blueswir1 | .idreg_base = 0x78000000,
|
1163 | a526a31c | blueswir1 | .dma_base = 0x78400000,
|
1164 | a526a31c | blueswir1 | .esp_base = 0x78800000,
|
1165 | a526a31c | blueswir1 | .le_base = 0x78c00000,
|
1166 | a526a31c | blueswir1 | .apc_base = 0x6a000000,
|
1167 | a526a31c | blueswir1 | .aux1_base = 0x71900000,
|
1168 | a526a31c | blueswir1 | .aux2_base = 0x71910000,
|
1169 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x80,
|
1170 | 905fdcb5 | blueswir1 | .machine_id = scls_id, |
1171 | a526a31c | blueswir1 | .iommu_version = 0x05000000,
|
1172 | a526a31c | blueswir1 | .max_mem = 0x10000000,
|
1173 | a526a31c | blueswir1 | .default_cpu_model = "TI MicroSparc I",
|
1174 | a526a31c | blueswir1 | }, |
1175 | a526a31c | blueswir1 | /* SPARCbook */
|
1176 | a526a31c | blueswir1 | { |
1177 | a526a31c | blueswir1 | .iommu_base = 0x10000000,
|
1178 | a526a31c | blueswir1 | .tcx_base = 0x50000000, // XXX |
1179 | a526a31c | blueswir1 | .slavio_base = 0x70000000,
|
1180 | a526a31c | blueswir1 | .ms_kb_base = 0x71000000,
|
1181 | a526a31c | blueswir1 | .serial_base = 0x71100000,
|
1182 | a526a31c | blueswir1 | .nvram_base = 0x71200000,
|
1183 | a526a31c | blueswir1 | .fd_base = 0x71400000,
|
1184 | a526a31c | blueswir1 | .counter_base = 0x71d00000,
|
1185 | a526a31c | blueswir1 | .intctl_base = 0x71e00000,
|
1186 | a526a31c | blueswir1 | .idreg_base = 0x78000000,
|
1187 | a526a31c | blueswir1 | .dma_base = 0x78400000,
|
1188 | a526a31c | blueswir1 | .esp_base = 0x78800000,
|
1189 | a526a31c | blueswir1 | .le_base = 0x78c00000,
|
1190 | a526a31c | blueswir1 | .apc_base = 0x6a000000,
|
1191 | a526a31c | blueswir1 | .aux1_base = 0x71900000,
|
1192 | a526a31c | blueswir1 | .aux2_base = 0x71910000,
|
1193 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x80,
|
1194 | 905fdcb5 | blueswir1 | .machine_id = sbook_id, |
1195 | a526a31c | blueswir1 | .iommu_version = 0x05000000,
|
1196 | a526a31c | blueswir1 | .max_mem = 0x10000000,
|
1197 | a526a31c | blueswir1 | .default_cpu_model = "TI MicroSparc I",
|
1198 | a526a31c | blueswir1 | }, |
1199 | 36cd9210 | blueswir1 | }; |
1200 | 36cd9210 | blueswir1 | |
1201 | 36cd9210 | blueswir1 | /* SPARCstation 5 hardware initialisation */
|
1202 | c227f099 | Anthony Liguori | static void ss5_init(ram_addr_t RAM_size, |
1203 | 3023f332 | aliguori | const char *boot_device, |
1204 | b881c2c6 | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1205 | b881c2c6 | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1206 | 36cd9210 | blueswir1 | { |
1207 | 3023f332 | aliguori | sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, kernel_filename,
|
1208 | 3ebf5aaf | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1209 | 420557e8 | bellard | } |
1210 | c0e564d5 | bellard | |
1211 | e0353fe2 | blueswir1 | /* SPARCstation 10 hardware initialisation */
|
1212 | c227f099 | Anthony Liguori | static void ss10_init(ram_addr_t RAM_size, |
1213 | 3023f332 | aliguori | const char *boot_device, |
1214 | b881c2c6 | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1215 | b881c2c6 | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1216 | e0353fe2 | blueswir1 | { |
1217 | 3023f332 | aliguori | sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, kernel_filename,
|
1218 | 3ebf5aaf | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1219 | e0353fe2 | blueswir1 | } |
1220 | e0353fe2 | blueswir1 | |
1221 | 6a3b9cc9 | blueswir1 | /* SPARCserver 600MP hardware initialisation */
|
1222 | c227f099 | Anthony Liguori | static void ss600mp_init(ram_addr_t RAM_size, |
1223 | 3023f332 | aliguori | const char *boot_device, |
1224 | 77f193da | blueswir1 | const char *kernel_filename, |
1225 | 77f193da | blueswir1 | const char *kernel_cmdline, |
1226 | 6a3b9cc9 | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1227 | 6a3b9cc9 | blueswir1 | { |
1228 | 3023f332 | aliguori | sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, kernel_filename,
|
1229 | 3ebf5aaf | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1230 | 6a3b9cc9 | blueswir1 | } |
1231 | 6a3b9cc9 | blueswir1 | |
1232 | ae40972f | blueswir1 | /* SPARCstation 20 hardware initialisation */
|
1233 | c227f099 | Anthony Liguori | static void ss20_init(ram_addr_t RAM_size, |
1234 | 3023f332 | aliguori | const char *boot_device, |
1235 | ae40972f | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1236 | ae40972f | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1237 | ae40972f | blueswir1 | { |
1238 | 3023f332 | aliguori | sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, kernel_filename,
|
1239 | ee76f82e | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1240 | ee76f82e | blueswir1 | } |
1241 | ee76f82e | blueswir1 | |
1242 | a526a31c | blueswir1 | /* SPARCstation Voyager hardware initialisation */
|
1243 | c227f099 | Anthony Liguori | static void vger_init(ram_addr_t RAM_size, |
1244 | 3023f332 | aliguori | const char *boot_device, |
1245 | a526a31c | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1246 | a526a31c | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1247 | a526a31c | blueswir1 | { |
1248 | 3023f332 | aliguori | sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, kernel_filename,
|
1249 | a526a31c | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1250 | a526a31c | blueswir1 | } |
1251 | a526a31c | blueswir1 | |
1252 | a526a31c | blueswir1 | /* SPARCstation LX hardware initialisation */
|
1253 | c227f099 | Anthony Liguori | static void ss_lx_init(ram_addr_t RAM_size, |
1254 | 3023f332 | aliguori | const char *boot_device, |
1255 | a526a31c | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1256 | a526a31c | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1257 | a526a31c | blueswir1 | { |
1258 | 3023f332 | aliguori | sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, kernel_filename,
|
1259 | a526a31c | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1260 | a526a31c | blueswir1 | } |
1261 | a526a31c | blueswir1 | |
1262 | a526a31c | blueswir1 | /* SPARCstation 4 hardware initialisation */
|
1263 | c227f099 | Anthony Liguori | static void ss4_init(ram_addr_t RAM_size, |
1264 | 3023f332 | aliguori | const char *boot_device, |
1265 | a526a31c | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1266 | a526a31c | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1267 | a526a31c | blueswir1 | { |
1268 | 3023f332 | aliguori | sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, kernel_filename,
|
1269 | a526a31c | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1270 | a526a31c | blueswir1 | } |
1271 | a526a31c | blueswir1 | |
1272 | a526a31c | blueswir1 | /* SPARCClassic hardware initialisation */
|
1273 | c227f099 | Anthony Liguori | static void scls_init(ram_addr_t RAM_size, |
1274 | 3023f332 | aliguori | const char *boot_device, |
1275 | a526a31c | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1276 | a526a31c | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1277 | a526a31c | blueswir1 | { |
1278 | 3023f332 | aliguori | sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, kernel_filename,
|
1279 | a526a31c | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1280 | a526a31c | blueswir1 | } |
1281 | a526a31c | blueswir1 | |
1282 | a526a31c | blueswir1 | /* SPARCbook hardware initialisation */
|
1283 | c227f099 | Anthony Liguori | static void sbook_init(ram_addr_t RAM_size, |
1284 | 3023f332 | aliguori | const char *boot_device, |
1285 | a526a31c | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1286 | a526a31c | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1287 | a526a31c | blueswir1 | { |
1288 | 3023f332 | aliguori | sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, kernel_filename,
|
1289 | a526a31c | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1290 | a526a31c | blueswir1 | } |
1291 | a526a31c | blueswir1 | |
1292 | f80f9ec9 | Anthony Liguori | static QEMUMachine ss5_machine = {
|
1293 | 66de733b | blueswir1 | .name = "SS-5",
|
1294 | 66de733b | blueswir1 | .desc = "Sun4m platform, SPARCstation 5",
|
1295 | 66de733b | blueswir1 | .init = ss5_init, |
1296 | c9b1ae2c | blueswir1 | .use_scsi = 1,
|
1297 | 0c257437 | Anthony Liguori | .is_default = 1,
|
1298 | c0e564d5 | bellard | }; |
1299 | e0353fe2 | blueswir1 | |
1300 | f80f9ec9 | Anthony Liguori | static QEMUMachine ss10_machine = {
|
1301 | 66de733b | blueswir1 | .name = "SS-10",
|
1302 | 66de733b | blueswir1 | .desc = "Sun4m platform, SPARCstation 10",
|
1303 | 66de733b | blueswir1 | .init = ss10_init, |
1304 | c9b1ae2c | blueswir1 | .use_scsi = 1,
|
1305 | 1bcee014 | blueswir1 | .max_cpus = 4,
|
1306 | e0353fe2 | blueswir1 | }; |
1307 | 6a3b9cc9 | blueswir1 | |
1308 | f80f9ec9 | Anthony Liguori | static QEMUMachine ss600mp_machine = {
|
1309 | 66de733b | blueswir1 | .name = "SS-600MP",
|
1310 | 66de733b | blueswir1 | .desc = "Sun4m platform, SPARCserver 600MP",
|
1311 | 66de733b | blueswir1 | .init = ss600mp_init, |
1312 | c9b1ae2c | blueswir1 | .use_scsi = 1,
|
1313 | 1bcee014 | blueswir1 | .max_cpus = 4,
|
1314 | 6a3b9cc9 | blueswir1 | }; |
1315 | ae40972f | blueswir1 | |
1316 | f80f9ec9 | Anthony Liguori | static QEMUMachine ss20_machine = {
|
1317 | 66de733b | blueswir1 | .name = "SS-20",
|
1318 | 66de733b | blueswir1 | .desc = "Sun4m platform, SPARCstation 20",
|
1319 | 66de733b | blueswir1 | .init = ss20_init, |
1320 | c9b1ae2c | blueswir1 | .use_scsi = 1,
|
1321 | 1bcee014 | blueswir1 | .max_cpus = 4,
|
1322 | ae40972f | blueswir1 | }; |
1323 | ae40972f | blueswir1 | |
1324 | f80f9ec9 | Anthony Liguori | static QEMUMachine voyager_machine = {
|
1325 | 66de733b | blueswir1 | .name = "Voyager",
|
1326 | 66de733b | blueswir1 | .desc = "Sun4m platform, SPARCstation Voyager",
|
1327 | 66de733b | blueswir1 | .init = vger_init, |
1328 | c9b1ae2c | blueswir1 | .use_scsi = 1,
|
1329 | a526a31c | blueswir1 | }; |
1330 | a526a31c | blueswir1 | |
1331 | f80f9ec9 | Anthony Liguori | static QEMUMachine ss_lx_machine = {
|
1332 | 66de733b | blueswir1 | .name = "LX",
|
1333 | 66de733b | blueswir1 | .desc = "Sun4m platform, SPARCstation LX",
|
1334 | 66de733b | blueswir1 | .init = ss_lx_init, |
1335 | c9b1ae2c | blueswir1 | .use_scsi = 1,
|
1336 | a526a31c | blueswir1 | }; |
1337 | a526a31c | blueswir1 | |
1338 | f80f9ec9 | Anthony Liguori | static QEMUMachine ss4_machine = {
|
1339 | 66de733b | blueswir1 | .name = "SS-4",
|
1340 | 66de733b | blueswir1 | .desc = "Sun4m platform, SPARCstation 4",
|
1341 | 66de733b | blueswir1 | .init = ss4_init, |
1342 | c9b1ae2c | blueswir1 | .use_scsi = 1,
|
1343 | a526a31c | blueswir1 | }; |
1344 | a526a31c | blueswir1 | |
1345 | f80f9ec9 | Anthony Liguori | static QEMUMachine scls_machine = {
|
1346 | 66de733b | blueswir1 | .name = "SPARCClassic",
|
1347 | 66de733b | blueswir1 | .desc = "Sun4m platform, SPARCClassic",
|
1348 | 66de733b | blueswir1 | .init = scls_init, |
1349 | c9b1ae2c | blueswir1 | .use_scsi = 1,
|
1350 | a526a31c | blueswir1 | }; |
1351 | a526a31c | blueswir1 | |
1352 | f80f9ec9 | Anthony Liguori | static QEMUMachine sbook_machine = {
|
1353 | 66de733b | blueswir1 | .name = "SPARCbook",
|
1354 | 66de733b | blueswir1 | .desc = "Sun4m platform, SPARCbook",
|
1355 | 66de733b | blueswir1 | .init = sbook_init, |
1356 | c9b1ae2c | blueswir1 | .use_scsi = 1,
|
1357 | a526a31c | blueswir1 | }; |
1358 | a526a31c | blueswir1 | |
1359 | 7d85892b | blueswir1 | static const struct sun4d_hwdef sun4d_hwdefs[] = { |
1360 | 7d85892b | blueswir1 | /* SS-1000 */
|
1361 | 7d85892b | blueswir1 | { |
1362 | 7d85892b | blueswir1 | .iounit_bases = { |
1363 | 7d85892b | blueswir1 | 0xfe0200000ULL,
|
1364 | 7d85892b | blueswir1 | 0xfe1200000ULL,
|
1365 | 7d85892b | blueswir1 | 0xfe2200000ULL,
|
1366 | 7d85892b | blueswir1 | 0xfe3200000ULL,
|
1367 | 7d85892b | blueswir1 | -1,
|
1368 | 7d85892b | blueswir1 | }, |
1369 | 7d85892b | blueswir1 | .tcx_base = 0x820000000ULL,
|
1370 | 7d85892b | blueswir1 | .slavio_base = 0xf00000000ULL,
|
1371 | 7d85892b | blueswir1 | .ms_kb_base = 0xf00240000ULL,
|
1372 | 7d85892b | blueswir1 | .serial_base = 0xf00200000ULL,
|
1373 | 7d85892b | blueswir1 | .nvram_base = 0xf00280000ULL,
|
1374 | 7d85892b | blueswir1 | .counter_base = 0xf00300000ULL,
|
1375 | 7d85892b | blueswir1 | .espdma_base = 0x800081000ULL,
|
1376 | 7d85892b | blueswir1 | .esp_base = 0x800080000ULL,
|
1377 | 7d85892b | blueswir1 | .ledma_base = 0x800040000ULL,
|
1378 | 7d85892b | blueswir1 | .le_base = 0x800060000ULL,
|
1379 | 7d85892b | blueswir1 | .sbi_base = 0xf02800000ULL,
|
1380 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x80,
|
1381 | 905fdcb5 | blueswir1 | .machine_id = ss1000_id, |
1382 | 7d85892b | blueswir1 | .iounit_version = 0x03000000,
|
1383 | 6ef05b95 | blueswir1 | .max_mem = 0xf00000000ULL,
|
1384 | 7d85892b | blueswir1 | .default_cpu_model = "TI SuperSparc II",
|
1385 | 7d85892b | blueswir1 | }, |
1386 | 7d85892b | blueswir1 | /* SS-2000 */
|
1387 | 7d85892b | blueswir1 | { |
1388 | 7d85892b | blueswir1 | .iounit_bases = { |
1389 | 7d85892b | blueswir1 | 0xfe0200000ULL,
|
1390 | 7d85892b | blueswir1 | 0xfe1200000ULL,
|
1391 | 7d85892b | blueswir1 | 0xfe2200000ULL,
|
1392 | 7d85892b | blueswir1 | 0xfe3200000ULL,
|
1393 | 7d85892b | blueswir1 | 0xfe4200000ULL,
|
1394 | 7d85892b | blueswir1 | }, |
1395 | 7d85892b | blueswir1 | .tcx_base = 0x820000000ULL,
|
1396 | 7d85892b | blueswir1 | .slavio_base = 0xf00000000ULL,
|
1397 | 7d85892b | blueswir1 | .ms_kb_base = 0xf00240000ULL,
|
1398 | 7d85892b | blueswir1 | .serial_base = 0xf00200000ULL,
|
1399 | 7d85892b | blueswir1 | .nvram_base = 0xf00280000ULL,
|
1400 | 7d85892b | blueswir1 | .counter_base = 0xf00300000ULL,
|
1401 | 7d85892b | blueswir1 | .espdma_base = 0x800081000ULL,
|
1402 | 7d85892b | blueswir1 | .esp_base = 0x800080000ULL,
|
1403 | 7d85892b | blueswir1 | .ledma_base = 0x800040000ULL,
|
1404 | 7d85892b | blueswir1 | .le_base = 0x800060000ULL,
|
1405 | 7d85892b | blueswir1 | .sbi_base = 0xf02800000ULL,
|
1406 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x80,
|
1407 | 905fdcb5 | blueswir1 | .machine_id = ss2000_id, |
1408 | 7d85892b | blueswir1 | .iounit_version = 0x03000000,
|
1409 | 6ef05b95 | blueswir1 | .max_mem = 0xf00000000ULL,
|
1410 | 7d85892b | blueswir1 | .default_cpu_model = "TI SuperSparc II",
|
1411 | 7d85892b | blueswir1 | }, |
1412 | 7d85892b | blueswir1 | }; |
1413 | 7d85892b | blueswir1 | |
1414 | c227f099 | Anthony Liguori | static DeviceState *sbi_init(target_phys_addr_t addr, qemu_irq **parent_irq)
|
1415 | 4b48bf05 | Blue Swirl | { |
1416 | 4b48bf05 | Blue Swirl | DeviceState *dev; |
1417 | 4b48bf05 | Blue Swirl | SysBusDevice *s; |
1418 | 4b48bf05 | Blue Swirl | unsigned int i; |
1419 | 4b48bf05 | Blue Swirl | |
1420 | 4b48bf05 | Blue Swirl | dev = qdev_create(NULL, "sbi"); |
1421 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
1422 | 4b48bf05 | Blue Swirl | |
1423 | 4b48bf05 | Blue Swirl | s = sysbus_from_qdev(dev); |
1424 | 4b48bf05 | Blue Swirl | |
1425 | 4b48bf05 | Blue Swirl | for (i = 0; i < MAX_CPUS; i++) { |
1426 | 4b48bf05 | Blue Swirl | sysbus_connect_irq(s, i, *parent_irq[i]); |
1427 | 4b48bf05 | Blue Swirl | } |
1428 | 4b48bf05 | Blue Swirl | |
1429 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 0, addr);
|
1430 | 4b48bf05 | Blue Swirl | |
1431 | 4b48bf05 | Blue Swirl | return dev;
|
1432 | 4b48bf05 | Blue Swirl | } |
1433 | 4b48bf05 | Blue Swirl | |
1434 | c227f099 | Anthony Liguori | static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size, |
1435 | 7d85892b | blueswir1 | const char *boot_device, |
1436 | 3023f332 | aliguori | const char *kernel_filename, |
1437 | 7d85892b | blueswir1 | const char *kernel_cmdline, |
1438 | 7d85892b | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1439 | 7d85892b | blueswir1 | { |
1440 | 7d85892b | blueswir1 | unsigned int i; |
1441 | 7fc06735 | Blue Swirl | void *iounits[MAX_IOUNITS], *espdma, *ledma, *nvram;
|
1442 | 7fc06735 | Blue Swirl | qemu_irq *cpu_irqs[MAX_CPUS], sbi_irq[32], sbi_cpu_irq[MAX_CPUS],
|
1443 | 6f6260c7 | Blue Swirl | espdma_irq, ledma_irq; |
1444 | 74ff8d90 | Blue Swirl | qemu_irq esp_reset; |
1445 | 5c6602c5 | blueswir1 | unsigned long kernel_size; |
1446 | 3cce6243 | blueswir1 | void *fw_cfg;
|
1447 | 7fc06735 | Blue Swirl | DeviceState *dev; |
1448 | 7d85892b | blueswir1 | |
1449 | 7d85892b | blueswir1 | /* init CPUs */
|
1450 | 7d85892b | blueswir1 | if (!cpu_model)
|
1451 | 7d85892b | blueswir1 | cpu_model = hwdef->default_cpu_model; |
1452 | 7d85892b | blueswir1 | |
1453 | 666713c0 | Blue Swirl | for(i = 0; i < smp_cpus; i++) { |
1454 | 89835363 | Blue Swirl | cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]); |
1455 | 7d85892b | blueswir1 | } |
1456 | 7d85892b | blueswir1 | |
1457 | 7d85892b | blueswir1 | for (i = smp_cpus; i < MAX_CPUS; i++)
|
1458 | 7d85892b | blueswir1 | cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
|
1459 | 7d85892b | blueswir1 | |
1460 | 7d85892b | blueswir1 | /* set up devices */
|
1461 | a350db85 | Blue Swirl | ram_init(0, RAM_size, hwdef->max_mem);
|
1462 | a350db85 | Blue Swirl | |
1463 | f48f6569 | Blue Swirl | prom_init(hwdef->slavio_base, bios_name); |
1464 | f48f6569 | Blue Swirl | |
1465 | 7fc06735 | Blue Swirl | dev = sbi_init(hwdef->sbi_base, cpu_irqs); |
1466 | 7fc06735 | Blue Swirl | |
1467 | 7fc06735 | Blue Swirl | for (i = 0; i < 32; i++) { |
1468 | 7fc06735 | Blue Swirl | sbi_irq[i] = qdev_get_gpio_in(dev, i); |
1469 | 7fc06735 | Blue Swirl | } |
1470 | 7fc06735 | Blue Swirl | for (i = 0; i < MAX_CPUS; i++) { |
1471 | 7fc06735 | Blue Swirl | sbi_cpu_irq[i] = qdev_get_gpio_in(dev, 32 + i);
|
1472 | 7fc06735 | Blue Swirl | } |
1473 | 7d85892b | blueswir1 | |
1474 | 7d85892b | blueswir1 | for (i = 0; i < MAX_IOUNITS; i++) |
1475 | c227f099 | Anthony Liguori | if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1) |
1476 | ff403da6 | blueswir1 | iounits[i] = iommu_init(hwdef->iounit_bases[i], |
1477 | ff403da6 | blueswir1 | hwdef->iounit_version, |
1478 | c533e0b3 | Blue Swirl | sbi_irq[0]);
|
1479 | 7d85892b | blueswir1 | |
1480 | c533e0b3 | Blue Swirl | espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[3],
|
1481 | 74ff8d90 | Blue Swirl | iounits[0], &espdma_irq);
|
1482 | 7d85892b | blueswir1 | |
1483 | c533e0b3 | Blue Swirl | ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[4],
|
1484 | 74ff8d90 | Blue Swirl | iounits[0], &ledma_irq);
|
1485 | 7d85892b | blueswir1 | |
1486 | 7d85892b | blueswir1 | if (graphic_depth != 8 && graphic_depth != 24) { |
1487 | 7d85892b | blueswir1 | fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
|
1488 | 7d85892b | blueswir1 | exit (1);
|
1489 | 7d85892b | blueswir1 | } |
1490 | d95d8f1c | Blue Swirl | tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
|
1491 | dc828ca1 | pbrook | graphic_depth); |
1492 | 7d85892b | blueswir1 | |
1493 | 74ff8d90 | Blue Swirl | lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
|
1494 | 7d85892b | blueswir1 | |
1495 | d95d8f1c | Blue Swirl | nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0, 0x2000, 8); |
1496 | 7d85892b | blueswir1 | |
1497 | c533e0b3 | Blue Swirl | slavio_timer_init_all(hwdef->counter_base, sbi_irq[10], sbi_cpu_irq, smp_cpus);
|
1498 | 7d85892b | blueswir1 | |
1499 | c533e0b3 | Blue Swirl | slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[12],
|
1500 | 993fbfdb | Anthony Liguori | display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
|
1501 | 7d85892b | blueswir1 | // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
|
1502 | 7d85892b | blueswir1 | // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
|
1503 | c533e0b3 | Blue Swirl | escc_init(hwdef->serial_base, sbi_irq[12], sbi_irq[12], |
1504 | aeeb69c7 | aurel32 | serial_hds[0], serial_hds[1], ESCC_CLOCK, 1); |
1505 | 7d85892b | blueswir1 | |
1506 | 7d85892b | blueswir1 | if (drive_get_max_bus(IF_SCSI) > 0) { |
1507 | 7d85892b | blueswir1 | fprintf(stderr, "qemu: too many SCSI bus\n");
|
1508 | 7d85892b | blueswir1 | exit(1);
|
1509 | 7d85892b | blueswir1 | } |
1510 | 7d85892b | blueswir1 | |
1511 | 74ff8d90 | Blue Swirl | esp_reset = qdev_get_gpio_in(espdma, 0);
|
1512 | cfb9de9c | Paul Brook | esp_init(hwdef->esp_base, 2,
|
1513 | cfb9de9c | Paul Brook | espdma_memory_read, espdma_memory_write, |
1514 | 74ff8d90 | Blue Swirl | espdma, espdma_irq, &esp_reset); |
1515 | 7d85892b | blueswir1 | |
1516 | 293f78bc | blueswir1 | kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename, |
1517 | 293f78bc | blueswir1 | RAM_size); |
1518 | 7d85892b | blueswir1 | |
1519 | 7d85892b | blueswir1 | nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
|
1520 | 7d85892b | blueswir1 | boot_device, RAM_size, kernel_size, graphic_width, |
1521 | 905fdcb5 | blueswir1 | graphic_height, graphic_depth, hwdef->nvram_machine_id, |
1522 | 905fdcb5 | blueswir1 | "Sun4d");
|
1523 | 3cce6243 | blueswir1 | |
1524 | 3cce6243 | blueswir1 | fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2); |
1525 | 3cce6243 | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
|
1526 | 905fdcb5 | blueswir1 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
1527 | 905fdcb5 | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); |
1528 | 513f789f | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); |
1529 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); |
1530 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); |
1531 | 513f789f | blueswir1 | if (kernel_cmdline) {
|
1532 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); |
1533 | 3c178e72 | Gerd Hoffmann | pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
|
1534 | 6bb4ca57 | Blue Swirl | fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA, |
1535 | 6bb4ca57 | Blue Swirl | (uint8_t*)strdup(kernel_cmdline), |
1536 | 6bb4ca57 | Blue Swirl | strlen(kernel_cmdline) + 1);
|
1537 | 513f789f | blueswir1 | } else {
|
1538 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
|
1539 | 513f789f | blueswir1 | } |
1540 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); |
1541 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used |
1542 | 513f789f | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
|
1543 | 513f789f | blueswir1 | qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); |
1544 | 7d85892b | blueswir1 | } |
1545 | 7d85892b | blueswir1 | |
1546 | 7d85892b | blueswir1 | /* SPARCserver 1000 hardware initialisation */
|
1547 | c227f099 | Anthony Liguori | static void ss1000_init(ram_addr_t RAM_size, |
1548 | 3023f332 | aliguori | const char *boot_device, |
1549 | 7d85892b | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1550 | 7d85892b | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1551 | 7d85892b | blueswir1 | { |
1552 | 3023f332 | aliguori | sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, kernel_filename,
|
1553 | 7d85892b | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1554 | 7d85892b | blueswir1 | } |
1555 | 7d85892b | blueswir1 | |
1556 | 7d85892b | blueswir1 | /* SPARCcenter 2000 hardware initialisation */
|
1557 | c227f099 | Anthony Liguori | static void ss2000_init(ram_addr_t RAM_size, |
1558 | 3023f332 | aliguori | const char *boot_device, |
1559 | 7d85892b | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1560 | 7d85892b | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1561 | 7d85892b | blueswir1 | { |
1562 | 3023f332 | aliguori | sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, kernel_filename,
|
1563 | 7d85892b | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1564 | 7d85892b | blueswir1 | } |
1565 | 7d85892b | blueswir1 | |
1566 | f80f9ec9 | Anthony Liguori | static QEMUMachine ss1000_machine = {
|
1567 | 66de733b | blueswir1 | .name = "SS-1000",
|
1568 | 66de733b | blueswir1 | .desc = "Sun4d platform, SPARCserver 1000",
|
1569 | 66de733b | blueswir1 | .init = ss1000_init, |
1570 | c9b1ae2c | blueswir1 | .use_scsi = 1,
|
1571 | 1bcee014 | blueswir1 | .max_cpus = 8,
|
1572 | 7d85892b | blueswir1 | }; |
1573 | 7d85892b | blueswir1 | |
1574 | f80f9ec9 | Anthony Liguori | static QEMUMachine ss2000_machine = {
|
1575 | 66de733b | blueswir1 | .name = "SS-2000",
|
1576 | 66de733b | blueswir1 | .desc = "Sun4d platform, SPARCcenter 2000",
|
1577 | 66de733b | blueswir1 | .init = ss2000_init, |
1578 | c9b1ae2c | blueswir1 | .use_scsi = 1,
|
1579 | 1bcee014 | blueswir1 | .max_cpus = 20,
|
1580 | 7d85892b | blueswir1 | }; |
1581 | 8137cde8 | blueswir1 | |
1582 | 8137cde8 | blueswir1 | static const struct sun4c_hwdef sun4c_hwdefs[] = { |
1583 | 8137cde8 | blueswir1 | /* SS-2 */
|
1584 | 8137cde8 | blueswir1 | { |
1585 | 8137cde8 | blueswir1 | .iommu_base = 0xf8000000,
|
1586 | 8137cde8 | blueswir1 | .tcx_base = 0xfe000000,
|
1587 | 8137cde8 | blueswir1 | .slavio_base = 0xf6000000,
|
1588 | 8137cde8 | blueswir1 | .intctl_base = 0xf5000000,
|
1589 | 8137cde8 | blueswir1 | .counter_base = 0xf3000000,
|
1590 | 8137cde8 | blueswir1 | .ms_kb_base = 0xf0000000,
|
1591 | 8137cde8 | blueswir1 | .serial_base = 0xf1000000,
|
1592 | 8137cde8 | blueswir1 | .nvram_base = 0xf2000000,
|
1593 | 8137cde8 | blueswir1 | .fd_base = 0xf7200000,
|
1594 | 8137cde8 | blueswir1 | .dma_base = 0xf8400000,
|
1595 | 8137cde8 | blueswir1 | .esp_base = 0xf8800000,
|
1596 | 8137cde8 | blueswir1 | .le_base = 0xf8c00000,
|
1597 | 8137cde8 | blueswir1 | .aux1_base = 0xf7400003,
|
1598 | 8137cde8 | blueswir1 | .nvram_machine_id = 0x55,
|
1599 | 8137cde8 | blueswir1 | .machine_id = ss2_id, |
1600 | 8137cde8 | blueswir1 | .max_mem = 0x10000000,
|
1601 | 8137cde8 | blueswir1 | .default_cpu_model = "Cypress CY7C601",
|
1602 | 8137cde8 | blueswir1 | }, |
1603 | 8137cde8 | blueswir1 | }; |
1604 | 8137cde8 | blueswir1 | |
1605 | c227f099 | Anthony Liguori | static DeviceState *sun4c_intctl_init(target_phys_addr_t addr,
|
1606 | 4b48bf05 | Blue Swirl | qemu_irq *parent_irq) |
1607 | 4b48bf05 | Blue Swirl | { |
1608 | 4b48bf05 | Blue Swirl | DeviceState *dev; |
1609 | 4b48bf05 | Blue Swirl | SysBusDevice *s; |
1610 | 4b48bf05 | Blue Swirl | unsigned int i; |
1611 | 4b48bf05 | Blue Swirl | |
1612 | 4b48bf05 | Blue Swirl | dev = qdev_create(NULL, "sun4c_intctl"); |
1613 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
1614 | 4b48bf05 | Blue Swirl | |
1615 | 4b48bf05 | Blue Swirl | s = sysbus_from_qdev(dev); |
1616 | 4b48bf05 | Blue Swirl | |
1617 | 4b48bf05 | Blue Swirl | for (i = 0; i < MAX_PILS; i++) { |
1618 | 4b48bf05 | Blue Swirl | sysbus_connect_irq(s, i, parent_irq[i]); |
1619 | 4b48bf05 | Blue Swirl | } |
1620 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 0, addr);
|
1621 | 4b48bf05 | Blue Swirl | |
1622 | 4b48bf05 | Blue Swirl | return dev;
|
1623 | 4b48bf05 | Blue Swirl | } |
1624 | 4b48bf05 | Blue Swirl | |
1625 | c227f099 | Anthony Liguori | static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size, |
1626 | 8137cde8 | blueswir1 | const char *boot_device, |
1627 | 3023f332 | aliguori | const char *kernel_filename, |
1628 | 8137cde8 | blueswir1 | const char *kernel_cmdline, |
1629 | 8137cde8 | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1630 | 8137cde8 | blueswir1 | { |
1631 | cfb9de9c | Paul Brook | void *iommu, *espdma, *ledma, *nvram;
|
1632 | e32cba29 | Blue Swirl | qemu_irq *cpu_irqs, slavio_irq[8], espdma_irq, ledma_irq;
|
1633 | 74ff8d90 | Blue Swirl | qemu_irq esp_reset; |
1634 | 2582cfa0 | Blue Swirl | qemu_irq fdc_tc; |
1635 | 5c6602c5 | blueswir1 | unsigned long kernel_size; |
1636 | fd8014e1 | Gerd Hoffmann | DriveInfo *fd[MAX_FD]; |
1637 | 8137cde8 | blueswir1 | void *fw_cfg;
|
1638 | e32cba29 | Blue Swirl | DeviceState *dev; |
1639 | e32cba29 | Blue Swirl | unsigned int i; |
1640 | 8137cde8 | blueswir1 | |
1641 | 8137cde8 | blueswir1 | /* init CPU */
|
1642 | 8137cde8 | blueswir1 | if (!cpu_model)
|
1643 | 8137cde8 | blueswir1 | cpu_model = hwdef->default_cpu_model; |
1644 | 8137cde8 | blueswir1 | |
1645 | 89835363 | Blue Swirl | cpu_devinit(cpu_model, 0, hwdef->slavio_base, &cpu_irqs);
|
1646 | 8137cde8 | blueswir1 | |
1647 | 8137cde8 | blueswir1 | /* set up devices */
|
1648 | a350db85 | Blue Swirl | ram_init(0, RAM_size, hwdef->max_mem);
|
1649 | a350db85 | Blue Swirl | |
1650 | f48f6569 | Blue Swirl | prom_init(hwdef->slavio_base, bios_name); |
1651 | f48f6569 | Blue Swirl | |
1652 | e32cba29 | Blue Swirl | dev = sun4c_intctl_init(hwdef->intctl_base, cpu_irqs); |
1653 | e32cba29 | Blue Swirl | |
1654 | e32cba29 | Blue Swirl | for (i = 0; i < 8; i++) { |
1655 | e32cba29 | Blue Swirl | slavio_irq[i] = qdev_get_gpio_in(dev, i); |
1656 | e32cba29 | Blue Swirl | } |
1657 | 8137cde8 | blueswir1 | |
1658 | 8137cde8 | blueswir1 | iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version, |
1659 | c533e0b3 | Blue Swirl | slavio_irq[1]);
|
1660 | 8137cde8 | blueswir1 | |
1661 | c533e0b3 | Blue Swirl | espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[2],
|
1662 | 74ff8d90 | Blue Swirl | iommu, &espdma_irq); |
1663 | 8137cde8 | blueswir1 | |
1664 | 8137cde8 | blueswir1 | ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
|
1665 | 74ff8d90 | Blue Swirl | slavio_irq[3], iommu, &ledma_irq);
|
1666 | 8137cde8 | blueswir1 | |
1667 | 8137cde8 | blueswir1 | if (graphic_depth != 8 && graphic_depth != 24) { |
1668 | 8137cde8 | blueswir1 | fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
|
1669 | 8137cde8 | blueswir1 | exit (1);
|
1670 | 8137cde8 | blueswir1 | } |
1671 | d95d8f1c | Blue Swirl | tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
|
1672 | dc828ca1 | pbrook | graphic_depth); |
1673 | 8137cde8 | blueswir1 | |
1674 | 74ff8d90 | Blue Swirl | lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
|
1675 | 8137cde8 | blueswir1 | |
1676 | d95d8f1c | Blue Swirl | nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x800, 2); |
1677 | 8137cde8 | blueswir1 | |
1678 | c533e0b3 | Blue Swirl | slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[1],
|
1679 | 993fbfdb | Anthony Liguori | display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
|
1680 | 8137cde8 | blueswir1 | // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
|
1681 | 8137cde8 | blueswir1 | // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
|
1682 | c533e0b3 | Blue Swirl | escc_init(hwdef->serial_base, slavio_irq[1],
|
1683 | c533e0b3 | Blue Swirl | slavio_irq[1], serial_hds[0], serial_hds[1], |
1684 | aeeb69c7 | aurel32 | ESCC_CLOCK, 1);
|
1685 | 8137cde8 | blueswir1 | |
1686 | b2b6f6ec | Blue Swirl | slavio_misc_init(0, hwdef->aux1_base, 0, slavio_irq[1], fdc_tc); |
1687 | 8137cde8 | blueswir1 | |
1688 | c227f099 | Anthony Liguori | if (hwdef->fd_base != (target_phys_addr_t)-1) { |
1689 | 8137cde8 | blueswir1 | /* there is zero or one floppy drive */
|
1690 | ce802585 | blueswir1 | memset(fd, 0, sizeof(fd)); |
1691 | fd8014e1 | Gerd Hoffmann | fd[0] = drive_get(IF_FLOPPY, 0, 0); |
1692 | c533e0b3 | Blue Swirl | sun4m_fdctrl_init(slavio_irq[1], hwdef->fd_base, fd,
|
1693 | 2582cfa0 | Blue Swirl | &fdc_tc); |
1694 | 8137cde8 | blueswir1 | } |
1695 | 8137cde8 | blueswir1 | |
1696 | 8137cde8 | blueswir1 | if (drive_get_max_bus(IF_SCSI) > 0) { |
1697 | 8137cde8 | blueswir1 | fprintf(stderr, "qemu: too many SCSI bus\n");
|
1698 | 8137cde8 | blueswir1 | exit(1);
|
1699 | 8137cde8 | blueswir1 | } |
1700 | 8137cde8 | blueswir1 | |
1701 | 74ff8d90 | Blue Swirl | esp_reset = qdev_get_gpio_in(espdma, 0);
|
1702 | cfb9de9c | Paul Brook | esp_init(hwdef->esp_base, 2,
|
1703 | cfb9de9c | Paul Brook | espdma_memory_read, espdma_memory_write, |
1704 | 74ff8d90 | Blue Swirl | espdma, espdma_irq, &esp_reset); |
1705 | 8137cde8 | blueswir1 | |
1706 | 8137cde8 | blueswir1 | kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename, |
1707 | 8137cde8 | blueswir1 | RAM_size); |
1708 | 8137cde8 | blueswir1 | |
1709 | 8137cde8 | blueswir1 | nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
|
1710 | 8137cde8 | blueswir1 | boot_device, RAM_size, kernel_size, graphic_width, |
1711 | 8137cde8 | blueswir1 | graphic_height, graphic_depth, hwdef->nvram_machine_id, |
1712 | 8137cde8 | blueswir1 | "Sun4c");
|
1713 | 8137cde8 | blueswir1 | |
1714 | 8137cde8 | blueswir1 | fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2); |
1715 | 8137cde8 | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
|
1716 | 8137cde8 | blueswir1 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
1717 | 8137cde8 | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); |
1718 | 513f789f | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); |
1719 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); |
1720 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); |
1721 | 513f789f | blueswir1 | if (kernel_cmdline) {
|
1722 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); |
1723 | 3c178e72 | Gerd Hoffmann | pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
|
1724 | 6bb4ca57 | Blue Swirl | fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA, |
1725 | 6bb4ca57 | Blue Swirl | (uint8_t*)strdup(kernel_cmdline), |
1726 | 6bb4ca57 | Blue Swirl | strlen(kernel_cmdline) + 1);
|
1727 | 513f789f | blueswir1 | } else {
|
1728 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
|
1729 | 513f789f | blueswir1 | } |
1730 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); |
1731 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used |
1732 | 513f789f | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
|
1733 | 513f789f | blueswir1 | qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); |
1734 | 8137cde8 | blueswir1 | } |
1735 | 8137cde8 | blueswir1 | |
1736 | 8137cde8 | blueswir1 | /* SPARCstation 2 hardware initialisation */
|
1737 | c227f099 | Anthony Liguori | static void ss2_init(ram_addr_t RAM_size, |
1738 | 3023f332 | aliguori | const char *boot_device, |
1739 | 8137cde8 | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1740 | 8137cde8 | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1741 | 8137cde8 | blueswir1 | { |
1742 | 3023f332 | aliguori | sun4c_hw_init(&sun4c_hwdefs[0], RAM_size, boot_device, kernel_filename,
|
1743 | 8137cde8 | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1744 | 8137cde8 | blueswir1 | } |
1745 | 8137cde8 | blueswir1 | |
1746 | f80f9ec9 | Anthony Liguori | static QEMUMachine ss2_machine = {
|
1747 | 8137cde8 | blueswir1 | .name = "SS-2",
|
1748 | 8137cde8 | blueswir1 | .desc = "Sun4c platform, SPARCstation 2",
|
1749 | 8137cde8 | blueswir1 | .init = ss2_init, |
1750 | 8137cde8 | blueswir1 | .use_scsi = 1,
|
1751 | 8137cde8 | blueswir1 | }; |
1752 | f80f9ec9 | Anthony Liguori | |
1753 | f80f9ec9 | Anthony Liguori | static void ss2_machine_init(void) |
1754 | f80f9ec9 | Anthony Liguori | { |
1755 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&ss5_machine); |
1756 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&ss10_machine); |
1757 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&ss600mp_machine); |
1758 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&ss20_machine); |
1759 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&voyager_machine); |
1760 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&ss_lx_machine); |
1761 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&ss4_machine); |
1762 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&scls_machine); |
1763 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&sbook_machine); |
1764 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&ss1000_machine); |
1765 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&ss2000_machine); |
1766 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&ss2_machine); |
1767 | f80f9ec9 | Anthony Liguori | } |
1768 | f80f9ec9 | Anthony Liguori | |
1769 | f80f9ec9 | Anthony Liguori | machine_init(ss2_machine_init); |