Revision 7c842590 target-xtensa/translate.c
| b/target-xtensa/translate.c | ||
|---|---|---|
| 2235 | 2235 |
gen_load_store(st32, 2); |
| 2236 | 2236 |
break; |
| 2237 | 2237 |
|
| 2238 |
#define gen_dcache_hit_test(w, shift) do { \
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| 2239 |
TCGv_i32 addr = tcg_temp_new_i32(); \ |
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| 2240 |
TCGv_i32 res = tcg_temp_new_i32(); \ |
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| 2241 |
gen_window_check1(dc, RRI##w##_S); \ |
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| 2242 |
tcg_gen_addi_i32(addr, cpu_R[RRI##w##_S], \ |
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| 2243 |
RRI##w##_IMM##w << shift); \ |
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| 2244 |
tcg_gen_qemu_ld8u(res, addr, dc->cring); \ |
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| 2245 |
tcg_temp_free(addr); \ |
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| 2246 |
tcg_temp_free(res); \ |
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| 2247 |
} while (0) |
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| 2248 |
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| 2249 |
#define gen_dcache_hit_test4() gen_dcache_hit_test(4, 4) |
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| 2250 |
#define gen_dcache_hit_test8() gen_dcache_hit_test(8, 2) |
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| 2251 |
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| 2238 | 2252 |
case 7: /*CACHEc*/ |
| 2239 | 2253 |
if (RRI8_T < 8) {
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| 2240 | 2254 |
HAS_OPTION(XTENSA_OPTION_DCACHE); |
| ... | ... | |
| 2242 | 2256 |
|
| 2243 | 2257 |
switch (RRI8_T) {
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| 2244 | 2258 |
case 0: /*DPFRc*/ |
| 2259 |
gen_window_check1(dc, RRI8_S); |
|
| 2245 | 2260 |
break; |
| 2246 | 2261 |
|
| 2247 | 2262 |
case 1: /*DPFWc*/ |
| 2263 |
gen_window_check1(dc, RRI8_S); |
|
| 2248 | 2264 |
break; |
| 2249 | 2265 |
|
| 2250 | 2266 |
case 2: /*DPFROc*/ |
| 2267 |
gen_window_check1(dc, RRI8_S); |
|
| 2251 | 2268 |
break; |
| 2252 | 2269 |
|
| 2253 | 2270 |
case 3: /*DPFWOc*/ |
| 2271 |
gen_window_check1(dc, RRI8_S); |
|
| 2254 | 2272 |
break; |
| 2255 | 2273 |
|
| 2256 | 2274 |
case 4: /*DHWBc*/ |
| 2275 |
gen_dcache_hit_test8(); |
|
| 2257 | 2276 |
break; |
| 2258 | 2277 |
|
| 2259 | 2278 |
case 5: /*DHWBIc*/ |
| 2279 |
gen_dcache_hit_test8(); |
|
| 2260 | 2280 |
break; |
| 2261 | 2281 |
|
| 2262 | 2282 |
case 6: /*DHIc*/ |
| 2283 |
gen_check_privilege(dc); |
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| 2284 |
gen_dcache_hit_test8(); |
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| 2263 | 2285 |
break; |
| 2264 | 2286 |
|
| 2265 | 2287 |
case 7: /*DIIc*/ |
| 2288 |
gen_check_privilege(dc); |
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| 2289 |
gen_window_check1(dc, RRI8_S); |
|
| 2266 | 2290 |
break; |
| 2267 | 2291 |
|
| 2268 | 2292 |
case 8: /*DCEc*/ |
| 2269 | 2293 |
switch (OP1) {
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| 2270 | 2294 |
case 0: /*DPFLl*/ |
| 2271 | 2295 |
HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK); |
| 2296 |
gen_check_privilege(dc); |
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| 2297 |
gen_dcache_hit_test4(); |
|
| 2272 | 2298 |
break; |
| 2273 | 2299 |
|
| 2274 | 2300 |
case 2: /*DHUl*/ |
| 2275 | 2301 |
HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK); |
| 2302 |
gen_check_privilege(dc); |
|
| 2303 |
gen_dcache_hit_test4(); |
|
| 2276 | 2304 |
break; |
| 2277 | 2305 |
|
| 2278 | 2306 |
case 3: /*DIUl*/ |
| 2279 | 2307 |
HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK); |
| 2308 |
gen_check_privilege(dc); |
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| 2309 |
gen_window_check1(dc, RRI4_S); |
|
| 2280 | 2310 |
break; |
| 2281 | 2311 |
|
| 2282 | 2312 |
case 4: /*DIWBc*/ |
| 2283 | 2313 |
HAS_OPTION(XTENSA_OPTION_DCACHE); |
| 2314 |
gen_check_privilege(dc); |
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| 2315 |
gen_window_check1(dc, RRI4_S); |
|
| 2284 | 2316 |
break; |
| 2285 | 2317 |
|
| 2286 | 2318 |
case 5: /*DIWBIc*/ |
| 2287 | 2319 |
HAS_OPTION(XTENSA_OPTION_DCACHE); |
| 2320 |
gen_check_privilege(dc); |
|
| 2321 |
gen_window_check1(dc, RRI4_S); |
|
| 2288 | 2322 |
break; |
| 2289 | 2323 |
|
| 2290 | 2324 |
default: /*reserved*/ |
| ... | ... | |
| 2294 | 2328 |
} |
| 2295 | 2329 |
break; |
| 2296 | 2330 |
|
| 2331 |
#undef gen_dcache_hit_test |
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| 2332 |
#undef gen_dcache_hit_test4 |
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| 2333 |
#undef gen_dcache_hit_test8 |
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| 2334 |
|
|
| 2297 | 2335 |
case 12: /*IPFc*/ |
| 2298 | 2336 |
HAS_OPTION(XTENSA_OPTION_ICACHE); |
| 2299 | 2337 |
break; |
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