root / qemu-barrier.h @ 7c9958b0
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1 | 85199474 | Marcelo Tosatti | #ifndef __QEMU_BARRIER_H
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2 | 85199474 | Marcelo Tosatti | #define __QEMU_BARRIER_H 1 |
3 | 85199474 | Marcelo Tosatti | |
4 | 1d93f0f0 | Jan Kiszka | /* Compiler barrier */
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5 | 1d93f0f0 | Jan Kiszka | #define barrier() asm volatile("" ::: "memory") |
6 | 1d93f0f0 | Jan Kiszka | |
7 | a281ebc1 | Michael S. Tsirkin | #if defined(__i386__)
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8 | e2251708 | David Gibson | |
9 | e2251708 | David Gibson | /*
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10 | a821ce59 | Michael S. Tsirkin | * Because of the strongly ordered x86 storage model, wmb() and rmb() are nops
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11 | e2251708 | David Gibson | * on x86(well, a compiler barrier only). Well, at least as long as
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12 | e2251708 | David Gibson | * qemu doesn't do accesses to write-combining memory or non-temporal
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13 | e2251708 | David Gibson | * load/stores from C code.
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14 | e2251708 | David Gibson | */
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15 | e2251708 | David Gibson | #define smp_wmb() barrier()
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16 | a821ce59 | Michael S. Tsirkin | #define smp_rmb() barrier()
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17 | a281ebc1 | Michael S. Tsirkin | /*
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18 | a281ebc1 | Michael S. Tsirkin | * We use GCC builtin if it's available, as that can use
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19 | a281ebc1 | Michael S. Tsirkin | * mfence on 32 bit as well, e.g. if built with -march=pentium-m.
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20 | a281ebc1 | Michael S. Tsirkin | * However, on i386, there seem to be known bugs as recently as 4.3.
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21 | a281ebc1 | Michael S. Tsirkin | * */
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22 | a281ebc1 | Michael S. Tsirkin | #if defined(__GNUC__) && __GNUC__ >= 4 && __GNUC_MINOR__ >= 4 |
23 | a281ebc1 | Michael S. Tsirkin | #define smp_mb() __sync_synchronize()
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24 | a281ebc1 | Michael S. Tsirkin | #else
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25 | a281ebc1 | Michael S. Tsirkin | #define smp_mb() asm volatile("lock; addl $0,0(%%esp) " ::: "memory") |
26 | a281ebc1 | Michael S. Tsirkin | #endif
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27 | a281ebc1 | Michael S. Tsirkin | |
28 | a281ebc1 | Michael S. Tsirkin | #elif defined(__x86_64__)
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29 | a281ebc1 | Michael S. Tsirkin | |
30 | a281ebc1 | Michael S. Tsirkin | #define smp_wmb() barrier()
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31 | a821ce59 | Michael S. Tsirkin | #define smp_rmb() barrier()
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32 | a281ebc1 | Michael S. Tsirkin | #define smp_mb() asm volatile("mfence" ::: "memory") |
33 | e2251708 | David Gibson | |
34 | 463ce4ae | Eric Sunshine | #elif defined(_ARCH_PPC)
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35 | e2251708 | David Gibson | |
36 | e2251708 | David Gibson | /*
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37 | a281ebc1 | Michael S. Tsirkin | * We use an eieio() for wmb() on powerpc. This assumes we don't
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38 | e2251708 | David Gibson | * need to order cacheable and non-cacheable stores with respect to
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39 | e2251708 | David Gibson | * each other
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40 | e2251708 | David Gibson | */
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41 | e2251708 | David Gibson | #define smp_wmb() asm volatile("eieio" ::: "memory") |
42 | a821ce59 | Michael S. Tsirkin | |
43 | a821ce59 | Michael S. Tsirkin | #if defined(__powerpc64__)
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44 | a821ce59 | Michael S. Tsirkin | #define smp_rmb() asm volatile("lwsync" ::: "memory") |
45 | a821ce59 | Michael S. Tsirkin | #else
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46 | a821ce59 | Michael S. Tsirkin | #define smp_rmb() asm volatile("sync" ::: "memory") |
47 | a821ce59 | Michael S. Tsirkin | #endif
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48 | a821ce59 | Michael S. Tsirkin | |
49 | a281ebc1 | Michael S. Tsirkin | #define smp_mb() asm volatile("sync" ::: "memory") |
50 | e2251708 | David Gibson | |
51 | e2251708 | David Gibson | #else
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52 | e2251708 | David Gibson | |
53 | e2251708 | David Gibson | /*
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54 | e2251708 | David Gibson | * For (host) platforms we don't have explicit barrier definitions
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55 | e2251708 | David Gibson | * for, we use the gcc __sync_synchronize() primitive to generate a
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56 | e2251708 | David Gibson | * full barrier. This should be safe on all platforms, though it may
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57 | a821ce59 | Michael S. Tsirkin | * be overkill for wmb() and rmb().
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58 | e2251708 | David Gibson | */
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59 | e2251708 | David Gibson | #define smp_wmb() __sync_synchronize()
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60 | a281ebc1 | Michael S. Tsirkin | #define smp_mb() __sync_synchronize()
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61 | a821ce59 | Michael S. Tsirkin | #define smp_rmb() __sync_synchronize()
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62 | e2251708 | David Gibson | |
63 | e2251708 | David Gibson | #endif
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64 | e2251708 | David Gibson | |
65 | 85199474 | Marcelo Tosatti | #endif |