root / hw / lm832x.c @ 7cc0dd20
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1 | 1d4e547b | balrog | /*
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2 | 1d4e547b | balrog | * National Semiconductor LM8322/8323 GPIO keyboard & PWM chips.
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3 | 1d4e547b | balrog | *
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4 | 1d4e547b | balrog | * Copyright (C) 2008 Nokia Corporation
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5 | 1d4e547b | balrog | * Written by Andrzej Zaborowski <andrew@openedhand.com>
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6 | 1d4e547b | balrog | *
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7 | 1d4e547b | balrog | * This program is free software; you can redistribute it and/or
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8 | 1d4e547b | balrog | * modify it under the terms of the GNU General Public License as
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9 | 1d4e547b | balrog | * published by the Free Software Foundation; either version 2 or
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10 | 1d4e547b | balrog | * (at your option) version 3 of the License.
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11 | 1d4e547b | balrog | *
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12 | 1d4e547b | balrog | * This program is distributed in the hope that it will be useful,
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13 | 1d4e547b | balrog | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 | 1d4e547b | balrog | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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15 | 1d4e547b | balrog | * GNU General Public License for more details.
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16 | 1d4e547b | balrog | *
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17 | 1d4e547b | balrog | * You should have received a copy of the GNU General Public License
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18 | 1d4e547b | balrog | * along with this program; if not, write to the Free Software
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19 | 1d4e547b | balrog | * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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20 | 1d4e547b | balrog | * MA 02111-1307 USA
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21 | 1d4e547b | balrog | */
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22 | 1d4e547b | balrog | |
23 | 1d4e547b | balrog | #include "hw.h" |
24 | 1d4e547b | balrog | #include "i2c.h" |
25 | 1d4e547b | balrog | #include "qemu-timer.h" |
26 | 1d4e547b | balrog | #include "console.h" |
27 | 1d4e547b | balrog | |
28 | 1d4e547b | balrog | struct lm_kbd_s {
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29 | 1d4e547b | balrog | i2c_slave i2c; |
30 | 1d4e547b | balrog | int i2c_dir;
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31 | 1d4e547b | balrog | int i2c_cycle;
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32 | 1d4e547b | balrog | int reg;
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33 | 1d4e547b | balrog | |
34 | 1d4e547b | balrog | qemu_irq nirq; |
35 | 1d4e547b | balrog | uint16_t model; |
36 | 1d4e547b | balrog | |
37 | 1d4e547b | balrog | struct {
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38 | 1d4e547b | balrog | qemu_irq out[2];
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39 | 1d4e547b | balrog | int in[2][2]; |
40 | 1d4e547b | balrog | } mux; |
41 | 1d4e547b | balrog | |
42 | 1d4e547b | balrog | uint8_t config; |
43 | 1d4e547b | balrog | uint8_t status; |
44 | 1d4e547b | balrog | uint8_t acttime; |
45 | 1d4e547b | balrog | uint8_t error; |
46 | 1d4e547b | balrog | uint8_t clock; |
47 | 1d4e547b | balrog | |
48 | 1d4e547b | balrog | struct {
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49 | 1d4e547b | balrog | uint16_t pull; |
50 | 1d4e547b | balrog | uint16_t mask; |
51 | 1d4e547b | balrog | uint16_t dir; |
52 | 1d4e547b | balrog | uint16_t level; |
53 | 1d4e547b | balrog | qemu_irq out[16];
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54 | 1d4e547b | balrog | } gpio; |
55 | 1d4e547b | balrog | |
56 | 1d4e547b | balrog | struct {
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57 | 1d4e547b | balrog | uint8_t dbnctime; |
58 | 1d4e547b | balrog | uint8_t size; |
59 | 1d4e547b | balrog | int start;
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60 | 1d4e547b | balrog | int len;
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61 | 1d4e547b | balrog | uint8_t fifo[16];
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62 | 1d4e547b | balrog | } kbd; |
63 | 1d4e547b | balrog | |
64 | 1d4e547b | balrog | struct {
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65 | 1d4e547b | balrog | uint16_t file[256];
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66 | 1d4e547b | balrog | uint8_t faddr; |
67 | 1d4e547b | balrog | uint8_t addr[3];
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68 | 1d4e547b | balrog | QEMUTimer *tm[3];
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69 | 1d4e547b | balrog | } pwm; |
70 | 1d4e547b | balrog | }; |
71 | 1d4e547b | balrog | |
72 | 1d4e547b | balrog | #define INT_KEYPAD (1 << 0) |
73 | 1d4e547b | balrog | #define INT_ERROR (1 << 3) |
74 | 1d4e547b | balrog | #define INT_NOINIT (1 << 4) |
75 | 1d4e547b | balrog | #define INT_PWMEND(n) (1 << (5 + n)) |
76 | 1d4e547b | balrog | |
77 | 1d4e547b | balrog | #define ERR_BADPAR (1 << 0) |
78 | 1d4e547b | balrog | #define ERR_CMDUNK (1 << 1) |
79 | 1d4e547b | balrog | #define ERR_KEYOVR (1 << 2) |
80 | 1d4e547b | balrog | #define ERR_FIFOOVR (1 << 6) |
81 | 1d4e547b | balrog | |
82 | 1d4e547b | balrog | static void lm_kbd_irq_update(struct lm_kbd_s *s) |
83 | 1d4e547b | balrog | { |
84 | 1d4e547b | balrog | qemu_set_irq(s->nirq, !s->status); |
85 | 1d4e547b | balrog | } |
86 | 1d4e547b | balrog | |
87 | 1d4e547b | balrog | static void lm_kbd_gpio_update(struct lm_kbd_s *s) |
88 | 1d4e547b | balrog | { |
89 | 1d4e547b | balrog | } |
90 | 1d4e547b | balrog | |
91 | 1d4e547b | balrog | static void lm_kbd_reset(struct lm_kbd_s *s) |
92 | 1d4e547b | balrog | { |
93 | 1d4e547b | balrog | s->config = 0x80;
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94 | 1d4e547b | balrog | s->status = INT_NOINIT; |
95 | 1d4e547b | balrog | s->acttime = 125;
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96 | 1d4e547b | balrog | s->kbd.dbnctime = 3;
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97 | 1d4e547b | balrog | s->kbd.size = 0x33;
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98 | 1d4e547b | balrog | s->clock = 0x08;
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99 | 1d4e547b | balrog | |
100 | 1d4e547b | balrog | lm_kbd_irq_update(s); |
101 | 1d4e547b | balrog | lm_kbd_gpio_update(s); |
102 | 1d4e547b | balrog | } |
103 | 1d4e547b | balrog | |
104 | 1d4e547b | balrog | static void lm_kbd_error(struct lm_kbd_s *s, int err) |
105 | 1d4e547b | balrog | { |
106 | 1d4e547b | balrog | s->error |= err; |
107 | 1d4e547b | balrog | s->status |= INT_ERROR; |
108 | 1d4e547b | balrog | lm_kbd_irq_update(s); |
109 | 1d4e547b | balrog | } |
110 | 1d4e547b | balrog | |
111 | 1d4e547b | balrog | static void lm_kbd_pwm_tick(struct lm_kbd_s *s, int line) |
112 | 1d4e547b | balrog | { |
113 | 1d4e547b | balrog | } |
114 | 1d4e547b | balrog | |
115 | 1d4e547b | balrog | static void lm_kbd_pwm_start(struct lm_kbd_s *s, int line) |
116 | 1d4e547b | balrog | { |
117 | 1d4e547b | balrog | lm_kbd_pwm_tick(s, line); |
118 | 1d4e547b | balrog | } |
119 | 1d4e547b | balrog | |
120 | 1d4e547b | balrog | static void lm_kbd_pwm0_tick(void *opaque) |
121 | 1d4e547b | balrog | { |
122 | 1d4e547b | balrog | lm_kbd_pwm_tick(opaque, 0);
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123 | 1d4e547b | balrog | } |
124 | 1d4e547b | balrog | static void lm_kbd_pwm1_tick(void *opaque) |
125 | 1d4e547b | balrog | { |
126 | 1d4e547b | balrog | lm_kbd_pwm_tick(opaque, 1);
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127 | 1d4e547b | balrog | } |
128 | 1d4e547b | balrog | static void lm_kbd_pwm2_tick(void *opaque) |
129 | 1d4e547b | balrog | { |
130 | 1d4e547b | balrog | lm_kbd_pwm_tick(opaque, 2);
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131 | 1d4e547b | balrog | } |
132 | 1d4e547b | balrog | |
133 | 1d4e547b | balrog | enum {
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134 | 1d4e547b | balrog | LM832x_CMD_READ_ID = 0x80, /* Read chip ID. */ |
135 | 1d4e547b | balrog | LM832x_CMD_WRITE_CFG = 0x81, /* Set configuration item. */ |
136 | 1d4e547b | balrog | LM832x_CMD_READ_INT = 0x82, /* Get interrupt status. */ |
137 | 1d4e547b | balrog | LM832x_CMD_RESET = 0x83, /* Reset, same as external one */ |
138 | 1d4e547b | balrog | LM823x_CMD_WRITE_PULL_DOWN = 0x84, /* Select GPIO pull-up/down. */ |
139 | 1d4e547b | balrog | LM832x_CMD_WRITE_PORT_SEL = 0x85, /* Select GPIO in/out. */ |
140 | 1d4e547b | balrog | LM832x_CMD_WRITE_PORT_STATE = 0x86, /* Set GPIO pull-up/down. */ |
141 | 1d4e547b | balrog | LM832x_CMD_READ_PORT_SEL = 0x87, /* Get GPIO in/out. */ |
142 | 1d4e547b | balrog | LM832x_CMD_READ_PORT_STATE = 0x88, /* Get GPIO pull-up/down. */ |
143 | 1d4e547b | balrog | LM832x_CMD_READ_FIFO = 0x89, /* Read byte from FIFO. */ |
144 | 1d4e547b | balrog | LM832x_CMD_RPT_READ_FIFO = 0x8a, /* Read FIFO (no increment). */ |
145 | 1d4e547b | balrog | LM832x_CMD_SET_ACTIVE = 0x8b, /* Set active time. */ |
146 | 1d4e547b | balrog | LM832x_CMD_READ_ERROR = 0x8c, /* Get error status. */ |
147 | 1d4e547b | balrog | LM832x_CMD_READ_ROTATOR = 0x8e, /* Read rotator status. */ |
148 | 1d4e547b | balrog | LM832x_CMD_SET_DEBOUNCE = 0x8f, /* Set debouncing time. */ |
149 | 1d4e547b | balrog | LM832x_CMD_SET_KEY_SIZE = 0x90, /* Set keypad size. */ |
150 | 1d4e547b | balrog | LM832x_CMD_READ_KEY_SIZE = 0x91, /* Get keypad size. */ |
151 | 1d4e547b | balrog | LM832x_CMD_READ_CFG = 0x92, /* Get configuration item. */ |
152 | 1d4e547b | balrog | LM832x_CMD_WRITE_CLOCK = 0x93, /* Set clock config. */ |
153 | 1d4e547b | balrog | LM832x_CMD_READ_CLOCK = 0x94, /* Get clock config. */ |
154 | 1d4e547b | balrog | LM832x_CMD_PWM_WRITE = 0x95, /* Write PWM script. */ |
155 | 1d4e547b | balrog | LM832x_CMD_PWM_START = 0x96, /* Start PWM engine. */ |
156 | 1d4e547b | balrog | LM832x_CMD_PWM_STOP = 0x97, /* Stop PWM engine. */ |
157 | 1d4e547b | balrog | }; |
158 | 1d4e547b | balrog | |
159 | 1d4e547b | balrog | #define LM832x_MAX_KPX 8 |
160 | 1d4e547b | balrog | #define LM832x_MAX_KPY 12 |
161 | 1d4e547b | balrog | |
162 | 1d4e547b | balrog | static uint8_t lm_kbd_read(struct lm_kbd_s *s, int reg, int byte) |
163 | 1d4e547b | balrog | { |
164 | 1d4e547b | balrog | int ret;
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165 | 1d4e547b | balrog | |
166 | 1d4e547b | balrog | switch (reg) {
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167 | 1d4e547b | balrog | case LM832x_CMD_READ_ID:
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168 | 1d4e547b | balrog | ret = 0x0400;
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169 | 1d4e547b | balrog | break;
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170 | 1d4e547b | balrog | |
171 | 1d4e547b | balrog | case LM832x_CMD_READ_INT:
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172 | 1d4e547b | balrog | ret = s->status; |
173 | 1d4e547b | balrog | if (!(s->status & INT_NOINIT)) {
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174 | 1d4e547b | balrog | s->status = 0;
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175 | 1d4e547b | balrog | lm_kbd_irq_update(s); |
176 | 1d4e547b | balrog | } |
177 | 1d4e547b | balrog | break;
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178 | 1d4e547b | balrog | |
179 | 1d4e547b | balrog | case LM832x_CMD_READ_PORT_SEL:
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180 | 1d4e547b | balrog | ret = s->gpio.dir; |
181 | 1d4e547b | balrog | break;
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182 | 1d4e547b | balrog | case LM832x_CMD_READ_PORT_STATE:
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183 | 1d4e547b | balrog | ret = s->gpio.mask; |
184 | 1d4e547b | balrog | break;
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185 | 1d4e547b | balrog | |
186 | 1d4e547b | balrog | case LM832x_CMD_READ_FIFO:
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187 | 1d4e547b | balrog | if (s->kbd.len <= 1) |
188 | 1d4e547b | balrog | return 0x00; |
189 | 1d4e547b | balrog | |
190 | 1d4e547b | balrog | /* Example response from the two commands after a INT_KEYPAD
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191 | 1d4e547b | balrog | * interrupt caused by the key 0x3c being pressed:
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192 | 1d4e547b | balrog | * RPT_READ_FIFO: 55 bc 00 4e ff 0a 50 08 00 29 d9 08 01 c9 01
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193 | 1d4e547b | balrog | * READ_FIFO: bc 00 00 4e ff 0a 50 08 00 29 d9 08 01 c9 01
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194 | 1d4e547b | balrog | * RPT_READ_FIFO: bc 00 00 4e ff 0a 50 08 00 29 d9 08 01 c9 01
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195 | 1d4e547b | balrog | *
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196 | 1d4e547b | balrog | * 55 is the code of the key release event serviced in the previous
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197 | 1d4e547b | balrog | * interrupt handling.
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198 | 1d4e547b | balrog | *
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199 | 1d4e547b | balrog | * TODO: find out whether the FIFO is advanced a single character
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200 | 1d4e547b | balrog | * before reading every byte or the whole size of the FIFO at the
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201 | 1d4e547b | balrog | * last LM832x_CMD_READ_FIFO. This affects LM832x_CMD_RPT_READ_FIFO
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202 | 1d4e547b | balrog | * output in cases where there are more than one event in the FIFO.
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203 | 1d4e547b | balrog | * Assume 0xbc and 0x3c events are in the FIFO:
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204 | 1d4e547b | balrog | * RPT_READ_FIFO: 55 bc 3c 00 4e ff 0a 50 08 00 29 d9 08 01 c9
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205 | 1d4e547b | balrog | * READ_FIFO: bc 3c 00 00 4e ff 0a 50 08 00 29 d9 08 01 c9
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206 | 1d4e547b | balrog | * Does RPT_READ_FIFO now return 0xbc and 0x3c or only 0x3c?
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207 | 1d4e547b | balrog | */
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208 | 1d4e547b | balrog | s->kbd.start ++; |
209 | 1d4e547b | balrog | s->kbd.start &= sizeof(s->kbd.fifo) - 1; |
210 | 1d4e547b | balrog | s->kbd.len --; |
211 | 1d4e547b | balrog | |
212 | 1d4e547b | balrog | return s->kbd.fifo[s->kbd.start];
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213 | 1d4e547b | balrog | case LM832x_CMD_RPT_READ_FIFO:
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214 | 1d4e547b | balrog | if (byte >= s->kbd.len)
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215 | 1d4e547b | balrog | return 0x00; |
216 | 1d4e547b | balrog | |
217 | 1d4e547b | balrog | return s->kbd.fifo[(s->kbd.start + byte) & (sizeof(s->kbd.fifo) - 1)]; |
218 | 1d4e547b | balrog | |
219 | 1d4e547b | balrog | case LM832x_CMD_READ_ERROR:
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220 | 1d4e547b | balrog | return s->error;
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221 | 1d4e547b | balrog | |
222 | 1d4e547b | balrog | case LM832x_CMD_READ_ROTATOR:
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223 | 1d4e547b | balrog | return 0; |
224 | 1d4e547b | balrog | |
225 | 1d4e547b | balrog | case LM832x_CMD_READ_KEY_SIZE:
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226 | 1d4e547b | balrog | return s->kbd.size;
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227 | 1d4e547b | balrog | |
228 | 1d4e547b | balrog | case LM832x_CMD_READ_CFG:
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229 | 1d4e547b | balrog | return s->config & 0xf; |
230 | 1d4e547b | balrog | |
231 | 1d4e547b | balrog | case LM832x_CMD_READ_CLOCK:
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232 | 1d4e547b | balrog | return (s->clock & 0xfc) | 2; |
233 | 1d4e547b | balrog | |
234 | 1d4e547b | balrog | default:
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235 | 1d4e547b | balrog | lm_kbd_error(s, ERR_CMDUNK); |
236 | 1d4e547b | balrog | fprintf(stderr, "%s: unknown command %02x\n", __FUNCTION__, reg);
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237 | 1d4e547b | balrog | return 0x00; |
238 | 1d4e547b | balrog | } |
239 | 1d4e547b | balrog | |
240 | 1d4e547b | balrog | return ret >> (byte << 3); |
241 | 1d4e547b | balrog | } |
242 | 1d4e547b | balrog | |
243 | 1d4e547b | balrog | static void lm_kbd_write(struct lm_kbd_s *s, int reg, int byte, uint8_t value) |
244 | 1d4e547b | balrog | { |
245 | 1d4e547b | balrog | switch (reg) {
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246 | 1d4e547b | balrog | case LM832x_CMD_WRITE_CFG:
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247 | 1d4e547b | balrog | s->config = value; |
248 | 1d4e547b | balrog | /* This must be done whenever s->mux.in is updated (never). */
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249 | 1d4e547b | balrog | if ((s->config >> 1) & 1) /* MUX1EN */ |
250 | 1d4e547b | balrog | qemu_set_irq(s->mux.out[0], s->mux.in[0][(s->config >> 0) & 1]); |
251 | 1d4e547b | balrog | if ((s->config >> 3) & 1) /* MUX2EN */ |
252 | 1d4e547b | balrog | qemu_set_irq(s->mux.out[0], s->mux.in[0][(s->config >> 2) & 1]); |
253 | 1d4e547b | balrog | /* TODO: check that this is issued only following the chip reset
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254 | 1d4e547b | balrog | * and not in the middle of operation and that it is followed by
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255 | 1d4e547b | balrog | * the GPIO ports re-resablishing through WRITE_PORT_SEL and
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256 | 1d4e547b | balrog | * WRITE_PORT_STATE (using a timer perhaps) and otherwise output
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257 | 1d4e547b | balrog | * warnings. */
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258 | 1d4e547b | balrog | s->status = 0;
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259 | 1d4e547b | balrog | lm_kbd_irq_update(s); |
260 | 1d4e547b | balrog | s->kbd.len = 0;
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261 | 1d4e547b | balrog | s->kbd.start = 0;
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262 | 1d4e547b | balrog | s->reg = -1;
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263 | 1d4e547b | balrog | break;
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264 | 1d4e547b | balrog | |
265 | 1d4e547b | balrog | case LM832x_CMD_RESET:
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266 | 1d4e547b | balrog | if (value == 0xaa) |
267 | 1d4e547b | balrog | lm_kbd_reset(s); |
268 | 1d4e547b | balrog | else
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269 | 1d4e547b | balrog | lm_kbd_error(s, ERR_BADPAR); |
270 | 1d4e547b | balrog | s->reg = -1;
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271 | 1d4e547b | balrog | break;
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272 | 1d4e547b | balrog | |
273 | 1d4e547b | balrog | case LM823x_CMD_WRITE_PULL_DOWN:
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274 | 1d4e547b | balrog | if (!byte)
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275 | 1d4e547b | balrog | s->gpio.pull = value; |
276 | 1d4e547b | balrog | else {
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277 | 1d4e547b | balrog | s->gpio.pull |= value << 8;
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278 | 1d4e547b | balrog | lm_kbd_gpio_update(s); |
279 | 1d4e547b | balrog | s->reg = -1;
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280 | 1d4e547b | balrog | } |
281 | 1d4e547b | balrog | break;
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282 | 1d4e547b | balrog | case LM832x_CMD_WRITE_PORT_SEL:
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283 | 1d4e547b | balrog | if (!byte)
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284 | 1d4e547b | balrog | s->gpio.dir = value; |
285 | 1d4e547b | balrog | else {
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286 | 1d4e547b | balrog | s->gpio.dir |= value << 8;
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287 | 1d4e547b | balrog | lm_kbd_gpio_update(s); |
288 | 1d4e547b | balrog | s->reg = -1;
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289 | 1d4e547b | balrog | } |
290 | 1d4e547b | balrog | break;
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291 | 1d4e547b | balrog | case LM832x_CMD_WRITE_PORT_STATE:
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292 | 1d4e547b | balrog | if (!byte)
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293 | 1d4e547b | balrog | s->gpio.mask = value; |
294 | 1d4e547b | balrog | else {
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295 | 1d4e547b | balrog | s->gpio.mask |= value << 8;
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296 | 1d4e547b | balrog | lm_kbd_gpio_update(s); |
297 | 1d4e547b | balrog | s->reg = -1;
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298 | 1d4e547b | balrog | } |
299 | 1d4e547b | balrog | break;
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300 | 1d4e547b | balrog | |
301 | 1d4e547b | balrog | case LM832x_CMD_SET_ACTIVE:
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302 | 1d4e547b | balrog | s->acttime = value; |
303 | 1d4e547b | balrog | s->reg = -1;
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304 | 1d4e547b | balrog | break;
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305 | 1d4e547b | balrog | |
306 | 1d4e547b | balrog | case LM832x_CMD_SET_DEBOUNCE:
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307 | 1d4e547b | balrog | s->kbd.dbnctime = value; |
308 | 1d4e547b | balrog | s->reg = -1;
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309 | 1d4e547b | balrog | if (!value)
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310 | 1d4e547b | balrog | lm_kbd_error(s, ERR_BADPAR); |
311 | 1d4e547b | balrog | break;
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312 | 1d4e547b | balrog | |
313 | 1d4e547b | balrog | case LM832x_CMD_SET_KEY_SIZE:
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314 | 1d4e547b | balrog | s->kbd.size = value; |
315 | 1d4e547b | balrog | s->reg = -1;
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316 | 1d4e547b | balrog | if (
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317 | 1d4e547b | balrog | (value & 0xf) < 3 || (value & 0xf) > LM832x_MAX_KPY || |
318 | 1d4e547b | balrog | (value >> 4) < 3 || (value >> 4) > LM832x_MAX_KPX) |
319 | 1d4e547b | balrog | lm_kbd_error(s, ERR_BADPAR); |
320 | 1d4e547b | balrog | break;
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321 | 1d4e547b | balrog | |
322 | 1d4e547b | balrog | case LM832x_CMD_WRITE_CLOCK:
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323 | 1d4e547b | balrog | s->clock = value; |
324 | 1d4e547b | balrog | s->reg = -1;
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325 | 1d4e547b | balrog | if ((value & 3) && (value & 3) != 3) { |
326 | 1d4e547b | balrog | lm_kbd_error(s, ERR_BADPAR); |
327 | 1d4e547b | balrog | fprintf(stderr, "%s: invalid clock setting in RCPWM\n",
|
328 | 1d4e547b | balrog | __FUNCTION__); |
329 | 1d4e547b | balrog | } |
330 | 1d4e547b | balrog | /* TODO: Validate that the command is only issued once */
|
331 | 1d4e547b | balrog | break;
|
332 | 1d4e547b | balrog | |
333 | 1d4e547b | balrog | case LM832x_CMD_PWM_WRITE:
|
334 | 1d4e547b | balrog | if (byte == 0) { |
335 | 1d4e547b | balrog | if (!(value & 3) || (value >> 2) > 59) { |
336 | 1d4e547b | balrog | lm_kbd_error(s, ERR_BADPAR); |
337 | 1d4e547b | balrog | s->reg = -1;
|
338 | 1d4e547b | balrog | break;
|
339 | 1d4e547b | balrog | } |
340 | 1d4e547b | balrog | |
341 | 1d4e547b | balrog | s->pwm.faddr = value; |
342 | 1d4e547b | balrog | s->pwm.file[s->pwm.faddr] = 0;
|
343 | 1d4e547b | balrog | } else if (byte == 1) { |
344 | 1d4e547b | balrog | s->pwm.file[s->pwm.faddr] |= value << 8;
|
345 | 1d4e547b | balrog | } else if (byte == 2) { |
346 | 1d4e547b | balrog | s->pwm.file[s->pwm.faddr] |= value << 0;
|
347 | 1d4e547b | balrog | s->reg = -1;
|
348 | 1d4e547b | balrog | } |
349 | 1d4e547b | balrog | break;
|
350 | 1d4e547b | balrog | case LM832x_CMD_PWM_START:
|
351 | 1d4e547b | balrog | s->reg = -1;
|
352 | 1d4e547b | balrog | if (!(value & 3) || (value >> 2) > 59) { |
353 | 1d4e547b | balrog | lm_kbd_error(s, ERR_BADPAR); |
354 | 1d4e547b | balrog | break;
|
355 | 1d4e547b | balrog | } |
356 | 1d4e547b | balrog | |
357 | 1d4e547b | balrog | s->pwm.addr[(value & 3) - 1] = value >> 2; |
358 | 1d4e547b | balrog | lm_kbd_pwm_start(s, (value & 3) - 1); |
359 | 1d4e547b | balrog | break;
|
360 | 1d4e547b | balrog | case LM832x_CMD_PWM_STOP:
|
361 | 1d4e547b | balrog | s->reg = -1;
|
362 | 1d4e547b | balrog | if (!(value & 3)) { |
363 | 1d4e547b | balrog | lm_kbd_error(s, ERR_BADPAR); |
364 | 1d4e547b | balrog | break;
|
365 | 1d4e547b | balrog | } |
366 | 1d4e547b | balrog | |
367 | 1d4e547b | balrog | qemu_del_timer(s->pwm.tm[(value & 3) - 1]); |
368 | 1d4e547b | balrog | break;
|
369 | 1d4e547b | balrog | |
370 | 1d4e547b | balrog | case -1: |
371 | 1d4e547b | balrog | lm_kbd_error(s, ERR_BADPAR); |
372 | 1d4e547b | balrog | break;
|
373 | 1d4e547b | balrog | default:
|
374 | 1d4e547b | balrog | lm_kbd_error(s, ERR_CMDUNK); |
375 | 1d4e547b | balrog | fprintf(stderr, "%s: unknown command %02x\n", __FUNCTION__, reg);
|
376 | 1d4e547b | balrog | break;
|
377 | 1d4e547b | balrog | } |
378 | 1d4e547b | balrog | } |
379 | 1d4e547b | balrog | |
380 | 1d4e547b | balrog | static void lm_i2c_event(i2c_slave *i2c, enum i2c_event event) |
381 | 1d4e547b | balrog | { |
382 | 1d4e547b | balrog | struct lm_kbd_s *s = (struct lm_kbd_s *) i2c; |
383 | 1d4e547b | balrog | |
384 | 1d4e547b | balrog | switch (event) {
|
385 | 1d4e547b | balrog | case I2C_START_RECV:
|
386 | 1d4e547b | balrog | case I2C_START_SEND:
|
387 | 1d4e547b | balrog | s->i2c_cycle = 0;
|
388 | 1d4e547b | balrog | s->i2c_dir = (event == I2C_START_SEND); |
389 | 1d4e547b | balrog | break;
|
390 | 1d4e547b | balrog | |
391 | 1d4e547b | balrog | default:
|
392 | 1d4e547b | balrog | break;
|
393 | 1d4e547b | balrog | } |
394 | 1d4e547b | balrog | } |
395 | 1d4e547b | balrog | |
396 | 1d4e547b | balrog | static int lm_i2c_rx(i2c_slave *i2c) |
397 | 1d4e547b | balrog | { |
398 | 1d4e547b | balrog | struct lm_kbd_s *s = (struct lm_kbd_s *) i2c; |
399 | 1d4e547b | balrog | |
400 | 1d4e547b | balrog | return lm_kbd_read(s, s->reg, s->i2c_cycle ++);
|
401 | 1d4e547b | balrog | } |
402 | 1d4e547b | balrog | |
403 | 1d4e547b | balrog | static int lm_i2c_tx(i2c_slave *i2c, uint8_t data) |
404 | 1d4e547b | balrog | { |
405 | 1d4e547b | balrog | struct lm_kbd_s *s = (struct lm_kbd_s *) i2c; |
406 | 1d4e547b | balrog | |
407 | 1d4e547b | balrog | if (!s->i2c_cycle)
|
408 | 1d4e547b | balrog | s->reg = data; |
409 | 1d4e547b | balrog | else
|
410 | 1d4e547b | balrog | lm_kbd_write(s, s->reg, s->i2c_cycle - 1, data);
|
411 | 1d4e547b | balrog | s->i2c_cycle ++; |
412 | 1d4e547b | balrog | |
413 | 1d4e547b | balrog | return 0; |
414 | 1d4e547b | balrog | } |
415 | 1d4e547b | balrog | |
416 | 1d4e547b | balrog | static void lm_kbd_save(QEMUFile *f, void *opaque) |
417 | 1d4e547b | balrog | { |
418 | 1d4e547b | balrog | struct lm_kbd_s *s = (struct lm_kbd_s *) opaque; |
419 | 1d4e547b | balrog | int i;
|
420 | 1d4e547b | balrog | |
421 | 1d4e547b | balrog | i2c_slave_save(f, &s->i2c); |
422 | 1d4e547b | balrog | qemu_put_byte(f, s->i2c_dir); |
423 | 1d4e547b | balrog | qemu_put_byte(f, s->i2c_cycle); |
424 | 1d4e547b | balrog | qemu_put_byte(f, (uint8_t) s->reg); |
425 | 1d4e547b | balrog | |
426 | 1d4e547b | balrog | qemu_put_8s(f, &s->config); |
427 | 1d4e547b | balrog | qemu_put_8s(f, &s->status); |
428 | 1d4e547b | balrog | qemu_put_8s(f, &s->acttime); |
429 | 1d4e547b | balrog | qemu_put_8s(f, &s->error); |
430 | 1d4e547b | balrog | qemu_put_8s(f, &s->clock); |
431 | 1d4e547b | balrog | |
432 | 1d4e547b | balrog | qemu_put_be16s(f, &s->gpio.pull); |
433 | 1d4e547b | balrog | qemu_put_be16s(f, &s->gpio.mask); |
434 | 1d4e547b | balrog | qemu_put_be16s(f, &s->gpio.dir); |
435 | 1d4e547b | balrog | qemu_put_be16s(f, &s->gpio.level); |
436 | 1d4e547b | balrog | |
437 | 1d4e547b | balrog | qemu_put_byte(f, s->kbd.dbnctime); |
438 | 1d4e547b | balrog | qemu_put_byte(f, s->kbd.size); |
439 | 1d4e547b | balrog | qemu_put_byte(f, s->kbd.start); |
440 | 1d4e547b | balrog | qemu_put_byte(f, s->kbd.len); |
441 | 1d4e547b | balrog | qemu_put_buffer(f, s->kbd.fifo, sizeof(s->kbd.fifo));
|
442 | 1d4e547b | balrog | |
443 | 1d4e547b | balrog | for (i = 0; i < sizeof(s->pwm.file); i ++) |
444 | 1d4e547b | balrog | qemu_put_be16s(f, &s->pwm.file[i]); |
445 | 1d4e547b | balrog | qemu_put_8s(f, &s->pwm.faddr); |
446 | 1d4e547b | balrog | qemu_put_buffer(f, s->pwm.addr, sizeof(s->pwm.addr));
|
447 | 1d4e547b | balrog | qemu_put_timer(f, s->pwm.tm[0]);
|
448 | 1d4e547b | balrog | qemu_put_timer(f, s->pwm.tm[1]);
|
449 | 1d4e547b | balrog | qemu_put_timer(f, s->pwm.tm[2]);
|
450 | 1d4e547b | balrog | } |
451 | 1d4e547b | balrog | |
452 | 1d4e547b | balrog | static int lm_kbd_load(QEMUFile *f, void *opaque, int version_id) |
453 | 1d4e547b | balrog | { |
454 | 1d4e547b | balrog | struct lm_kbd_s *s = (struct lm_kbd_s *) opaque; |
455 | 1d4e547b | balrog | int i;
|
456 | 1d4e547b | balrog | |
457 | 1d4e547b | balrog | i2c_slave_load(f, &s->i2c); |
458 | 1d4e547b | balrog | s->i2c_dir = qemu_get_byte(f); |
459 | 1d4e547b | balrog | s->i2c_cycle = qemu_get_byte(f); |
460 | 1d4e547b | balrog | s->reg = (int8_t) qemu_get_byte(f); |
461 | 1d4e547b | balrog | |
462 | 1d4e547b | balrog | qemu_get_8s(f, &s->config); |
463 | 1d4e547b | balrog | qemu_get_8s(f, &s->status); |
464 | 1d4e547b | balrog | qemu_get_8s(f, &s->acttime); |
465 | 1d4e547b | balrog | qemu_get_8s(f, &s->error); |
466 | 1d4e547b | balrog | qemu_get_8s(f, &s->clock); |
467 | 1d4e547b | balrog | |
468 | 1d4e547b | balrog | qemu_get_be16s(f, &s->gpio.pull); |
469 | 1d4e547b | balrog | qemu_get_be16s(f, &s->gpio.mask); |
470 | 1d4e547b | balrog | qemu_get_be16s(f, &s->gpio.dir); |
471 | 1d4e547b | balrog | qemu_get_be16s(f, &s->gpio.level); |
472 | 1d4e547b | balrog | |
473 | 1d4e547b | balrog | s->kbd.dbnctime = qemu_get_byte(f); |
474 | 1d4e547b | balrog | s->kbd.size = qemu_get_byte(f); |
475 | 1d4e547b | balrog | s->kbd.start = qemu_get_byte(f); |
476 | 1d4e547b | balrog | s->kbd.len = qemu_get_byte(f); |
477 | 1d4e547b | balrog | qemu_get_buffer(f, s->kbd.fifo, sizeof(s->kbd.fifo));
|
478 | 1d4e547b | balrog | |
479 | 1d4e547b | balrog | for (i = 0; i < sizeof(s->pwm.file); i ++) |
480 | 1d4e547b | balrog | qemu_get_be16s(f, &s->pwm.file[i]); |
481 | 1d4e547b | balrog | qemu_get_8s(f, &s->pwm.faddr); |
482 | 1d4e547b | balrog | qemu_get_buffer(f, s->pwm.addr, sizeof(s->pwm.addr));
|
483 | 1d4e547b | balrog | qemu_get_timer(f, s->pwm.tm[0]);
|
484 | 1d4e547b | balrog | qemu_get_timer(f, s->pwm.tm[1]);
|
485 | 1d4e547b | balrog | qemu_get_timer(f, s->pwm.tm[2]);
|
486 | 1d4e547b | balrog | |
487 | 1d4e547b | balrog | lm_kbd_irq_update(s); |
488 | 1d4e547b | balrog | lm_kbd_gpio_update(s); |
489 | 1d4e547b | balrog | |
490 | 1d4e547b | balrog | return 0; |
491 | 1d4e547b | balrog | } |
492 | 1d4e547b | balrog | |
493 | 1d4e547b | balrog | struct i2c_slave *lm8323_init(i2c_bus *bus, qemu_irq nirq)
|
494 | 1d4e547b | balrog | { |
495 | 1d4e547b | balrog | struct lm_kbd_s *s;
|
496 | 1d4e547b | balrog | |
497 | 1d4e547b | balrog | s = (struct lm_kbd_s *) i2c_slave_init(bus, 0, sizeof(struct lm_kbd_s)); |
498 | 1d4e547b | balrog | s->model = 0x8323;
|
499 | 1d4e547b | balrog | s->pwm.tm[0] = qemu_new_timer(vm_clock, lm_kbd_pwm0_tick, s);
|
500 | 1d4e547b | balrog | s->pwm.tm[1] = qemu_new_timer(vm_clock, lm_kbd_pwm1_tick, s);
|
501 | 1d4e547b | balrog | s->pwm.tm[2] = qemu_new_timer(vm_clock, lm_kbd_pwm2_tick, s);
|
502 | 1d4e547b | balrog | s->nirq = nirq; |
503 | 1d4e547b | balrog | |
504 | 1d4e547b | balrog | s->i2c.event = lm_i2c_event; |
505 | 1d4e547b | balrog | s->i2c.recv = lm_i2c_rx; |
506 | 1d4e547b | balrog | s->i2c.send = lm_i2c_tx; |
507 | 1d4e547b | balrog | |
508 | 1d4e547b | balrog | lm_kbd_reset(s); |
509 | 1d4e547b | balrog | |
510 | 1d4e547b | balrog | qemu_register_reset((void *) lm_kbd_reset, s);
|
511 | 18be5187 | pbrook | register_savevm("LM8323", -1, 0, lm_kbd_save, lm_kbd_load, s); |
512 | 1d4e547b | balrog | |
513 | 1d4e547b | balrog | return &s->i2c;
|
514 | 1d4e547b | balrog | } |
515 | 1d4e547b | balrog | |
516 | 1d4e547b | balrog | void lm832x_key_event(struct i2c_slave *i2c, int key, int state) |
517 | 1d4e547b | balrog | { |
518 | 1d4e547b | balrog | struct lm_kbd_s *s = (struct lm_kbd_s *) i2c; |
519 | 1d4e547b | balrog | |
520 | 1d4e547b | balrog | if ((s->status & INT_ERROR) && (s->error & ERR_FIFOOVR))
|
521 | 1d4e547b | balrog | return;
|
522 | 1d4e547b | balrog | |
523 | 1d4e547b | balrog | if (s->kbd.len >= sizeof(s->kbd.fifo)) |
524 | 1d4e547b | balrog | return lm_kbd_error(s, ERR_FIFOOVR);
|
525 | 1d4e547b | balrog | |
526 | 1d4e547b | balrog | s->kbd.fifo[(s->kbd.start + s->kbd.len ++) & (sizeof(s->kbd.fifo) - 1)] = |
527 | 1d4e547b | balrog | key | (state << 7);
|
528 | 1d4e547b | balrog | |
529 | 1d4e547b | balrog | /* We never set ERR_KEYOVR because we support multiple keys fine. */
|
530 | 1d4e547b | balrog | s->status |= INT_KEYPAD; |
531 | 1d4e547b | balrog | lm_kbd_irq_update(s); |
532 | 1d4e547b | balrog | } |