Revision 7d7c4930

b/tcg/mips/tcg-target.c
308 308
    OPC_SRAV     = OPC_SPECIAL | 0x07,
309 309
    OPC_JR       = OPC_SPECIAL | 0x08,
310 310
    OPC_JALR     = OPC_SPECIAL | 0x09,
311
    OPC_MOVZ     = OPC_SPECIAL | 0x0A,
312
    OPC_MOVN     = OPC_SPECIAL | 0x0B,
311 313
    OPC_MFHI     = OPC_SPECIAL | 0x10,
312 314
    OPC_MFLO     = OPC_SPECIAL | 0x12,
313 315
    OPC_MULT     = OPC_SPECIAL | 0x18,
......
735 737
    reloc_pc16(label_ptr, (tcg_target_long) s->code_ptr);
736 738
}
737 739

  
740
static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret,
741
                            TCGArg c1, TCGArg c2, TCGArg v)
742
{
743
    switch (cond) {
744
    case TCG_COND_EQ:
745
        if (c1 == 0) {
746
            tcg_out_opc_reg(s, OPC_MOVZ, ret, v, c2);
747
        } else if (c2 == 0) {
748
            tcg_out_opc_reg(s, OPC_MOVZ, ret, v, c1);
749
        } else {
750
            tcg_out_opc_reg(s, OPC_XOR, TCG_REG_AT, c1, c2);
751
            tcg_out_opc_reg(s, OPC_MOVZ, ret, v, TCG_REG_AT);
752
        }
753
        break;
754
    case TCG_COND_NE:
755
        if (c1 == 0) {
756
            tcg_out_opc_reg(s, OPC_MOVN, ret, v, c2);
757
        } else if (c2 == 0) {
758
            tcg_out_opc_reg(s, OPC_MOVN, ret, v, c1);
759
        } else {
760
            tcg_out_opc_reg(s, OPC_XOR, TCG_REG_AT, c1, c2);
761
            tcg_out_opc_reg(s, OPC_MOVN, ret, v, TCG_REG_AT);
762
        }
763
        break;
764
    case TCG_COND_LT:
765
        tcg_out_opc_reg(s, OPC_SLT, TCG_REG_AT, c1, c2);
766
        tcg_out_opc_reg(s, OPC_MOVN, ret, v, TCG_REG_AT);
767
        break;
768
    case TCG_COND_LTU:
769
        tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_AT, c1, c2);
770
        tcg_out_opc_reg(s, OPC_MOVN, ret, v, TCG_REG_AT);
771
        break;
772
    case TCG_COND_GE:
773
        tcg_out_opc_reg(s, OPC_SLT, TCG_REG_AT, c1, c2);
774
        tcg_out_opc_reg(s, OPC_MOVZ, ret, v, TCG_REG_AT);
775
        break;
776
    case TCG_COND_GEU:
777
        tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_AT, c1, c2);
778
        tcg_out_opc_reg(s, OPC_MOVZ, ret, v, TCG_REG_AT);
779
        break;
780
    case TCG_COND_LE:
781
        tcg_out_opc_reg(s, OPC_SLT, TCG_REG_AT, c2, c1);
782
        tcg_out_opc_reg(s, OPC_MOVZ, ret, v, TCG_REG_AT);
783
        break;
784
    case TCG_COND_LEU:
785
        tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_AT, c2, c1);
786
        tcg_out_opc_reg(s, OPC_MOVZ, ret, v, TCG_REG_AT);
787
        break;
788
    case TCG_COND_GT:
789
        tcg_out_opc_reg(s, OPC_SLT, TCG_REG_AT, c2, c1);
790
        tcg_out_opc_reg(s, OPC_MOVN, ret, v, TCG_REG_AT);
791
        break;
792
    case TCG_COND_GTU:
793
        tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_AT, c2, c1);
794
        tcg_out_opc_reg(s, OPC_MOVN, ret, v, TCG_REG_AT);
795
        break;
796
    default:
797
        tcg_abort();
798
        break;
799
    }
800
}
801

  
738 802
static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret,
739 803
                            TCGArg arg1, TCGArg arg2)
740 804
{
......
1468 1532
        tcg_out_brcond2(s, args[4], args[0], args[1], args[2], args[3], args[5]);
1469 1533
        break;
1470 1534

  
1535
    case INDEX_op_movcond_i32:
1536
        tcg_out_movcond(s, args[5], args[0], args[1], args[2], args[3]);
1537
        break;
1538

  
1471 1539
    case INDEX_op_setcond_i32:
1472 1540
        tcg_out_setcond(s, args[3], args[0], args[1], args[2]);
1473 1541
        break;
......
1559 1627
    { INDEX_op_deposit_i32, { "r", "0", "rZ" } },
1560 1628

  
1561 1629
    { INDEX_op_brcond_i32, { "rZ", "rZ" } },
1630
    { INDEX_op_movcond_i32, { "r", "rZ", "rZ", "rZ", "0" } },
1562 1631
    { INDEX_op_setcond_i32, { "r", "rZ", "rZ" } },
1563 1632
    { INDEX_op_setcond2_i32, { "r", "rZ", "rZ", "rZ", "rZ" } },
1564 1633

  
b/tcg/mips/tcg-target.h
86 86
#define TCG_TARGET_HAS_orc_i32          0
87 87
#define TCG_TARGET_HAS_eqv_i32          0
88 88
#define TCG_TARGET_HAS_nand_i32         0
89

  
90
/* optional instructions only implemented on MIPS4, MIPS32 and Loongson 2 */
91
#if defined(_MIPS_ARCH_MIPS4) || defined(_MIPS_ARCH_MIPS32) || \
92
    defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_LOONGSON2E) || \
93
    defined(_MIPS_ARCH_LOONGSON2F)
94
#define TCG_TARGET_HAS_movcond_i32      1
95
#else
89 96
#define TCG_TARGET_HAS_movcond_i32      0
97
#endif
90 98

  
91 99
/* optional instructions only implemented on MIPS32R2 */
92 100
#ifdef _MIPS_ARCH_MIPS32R2

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