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1 | 6f7e9aec | bellard | /*
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2 | 67e999be | bellard | * QEMU ESP/NCR53C9x emulation
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3 | 5fafdf24 | ths | *
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4 | 4e9aec74 | pbrook | * Copyright (c) 2005-2006 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 6f7e9aec | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 6f7e9aec | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 6f7e9aec | bellard | * in the Software without restriction, including without limitation the rights
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9 | 6f7e9aec | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 6f7e9aec | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 6f7e9aec | bellard | * furnished to do so, subject to the following conditions:
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12 | 6f7e9aec | bellard | *
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13 | 6f7e9aec | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 6f7e9aec | bellard | * all copies or substantial portions of the Software.
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15 | 6f7e9aec | bellard | *
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16 | 6f7e9aec | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 6f7e9aec | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 6f7e9aec | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 6f7e9aec | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 6f7e9aec | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 6f7e9aec | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 6f7e9aec | bellard | * THE SOFTWARE.
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23 | 6f7e9aec | bellard | */
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24 | 5d20fa6b | blueswir1 | |
25 | cfb9de9c | Paul Brook | #include "sysbus.h" |
26 | 43b443b6 | Gerd Hoffmann | #include "scsi.h" |
27 | 1cd3af54 | Gerd Hoffmann | #include "esp.h" |
28 | 6f7e9aec | bellard | |
29 | 6f7e9aec | bellard | /* debug ESP card */
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30 | 2f275b8f | bellard | //#define DEBUG_ESP
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31 | 6f7e9aec | bellard | |
32 | 67e999be | bellard | /*
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33 | 5ad6bb97 | blueswir1 | * On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O),
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34 | 5ad6bb97 | blueswir1 | * also produced as NCR89C100. See
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35 | 67e999be | bellard | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
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36 | 67e999be | bellard | * and
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37 | 67e999be | bellard | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt
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38 | 67e999be | bellard | */
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39 | 67e999be | bellard | |
40 | 6f7e9aec | bellard | #ifdef DEBUG_ESP
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41 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...) \
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42 | 001faf32 | Blue Swirl | do { printf("ESP: " fmt , ## __VA_ARGS__); } while (0) |
43 | 6f7e9aec | bellard | #else
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44 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...) do {} while (0) |
45 | 6f7e9aec | bellard | #endif
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46 | 6f7e9aec | bellard | |
47 | 001faf32 | Blue Swirl | #define ESP_ERROR(fmt, ...) \
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48 | 001faf32 | Blue Swirl | do { printf("ESP ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0) |
49 | 8dea1dd4 | blueswir1 | |
50 | 5aca8c3b | blueswir1 | #define ESP_REGS 16 |
51 | 8dea1dd4 | blueswir1 | #define TI_BUFSZ 16 |
52 | 67e999be | bellard | |
53 | 4e9aec74 | pbrook | typedef struct ESPState ESPState; |
54 | 6f7e9aec | bellard | |
55 | 4e9aec74 | pbrook | struct ESPState {
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56 | cfb9de9c | Paul Brook | SysBusDevice busdev; |
57 | 5d20fa6b | blueswir1 | uint32_t it_shift; |
58 | 70c0de96 | blueswir1 | qemu_irq irq; |
59 | 5aca8c3b | blueswir1 | uint8_t rregs[ESP_REGS]; |
60 | 5aca8c3b | blueswir1 | uint8_t wregs[ESP_REGS]; |
61 | 67e999be | bellard | int32_t ti_size; |
62 | 4f6200f0 | bellard | uint32_t ti_rptr, ti_wptr; |
63 | 4f6200f0 | bellard | uint8_t ti_buf[TI_BUFSZ]; |
64 | 22548760 | blueswir1 | uint32_t sense; |
65 | 22548760 | blueswir1 | uint32_t dma; |
66 | ca9c39fa | Gerd Hoffmann | SCSIBus bus; |
67 | 2e5d83bb | pbrook | SCSIDevice *current_dev; |
68 | 9f149aa9 | pbrook | uint8_t cmdbuf[TI_BUFSZ]; |
69 | 22548760 | blueswir1 | uint32_t cmdlen; |
70 | 22548760 | blueswir1 | uint32_t do_cmd; |
71 | 4d611c9a | pbrook | |
72 | 6787f5fa | pbrook | /* The amount of data left in the current DMA transfer. */
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73 | 4d611c9a | pbrook | uint32_t dma_left; |
74 | 6787f5fa | pbrook | /* The size of the current DMA transfer. Zero if no transfer is in
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75 | 6787f5fa | pbrook | progress. */
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76 | 6787f5fa | pbrook | uint32_t dma_counter; |
77 | a917d384 | pbrook | uint8_t *async_buf; |
78 | 4d611c9a | pbrook | uint32_t async_len; |
79 | 8b17de88 | blueswir1 | |
80 | ff9868ec | Blue Swirl | ESPDMAMemoryReadWriteFunc dma_memory_read; |
81 | ff9868ec | Blue Swirl | ESPDMAMemoryReadWriteFunc dma_memory_write; |
82 | 67e999be | bellard | void *dma_opaque;
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83 | 4e9aec74 | pbrook | }; |
84 | 6f7e9aec | bellard | |
85 | 5ad6bb97 | blueswir1 | #define ESP_TCLO 0x0 |
86 | 5ad6bb97 | blueswir1 | #define ESP_TCMID 0x1 |
87 | 5ad6bb97 | blueswir1 | #define ESP_FIFO 0x2 |
88 | 5ad6bb97 | blueswir1 | #define ESP_CMD 0x3 |
89 | 5ad6bb97 | blueswir1 | #define ESP_RSTAT 0x4 |
90 | 5ad6bb97 | blueswir1 | #define ESP_WBUSID 0x4 |
91 | 5ad6bb97 | blueswir1 | #define ESP_RINTR 0x5 |
92 | 5ad6bb97 | blueswir1 | #define ESP_WSEL 0x5 |
93 | 5ad6bb97 | blueswir1 | #define ESP_RSEQ 0x6 |
94 | 5ad6bb97 | blueswir1 | #define ESP_WSYNTP 0x6 |
95 | 5ad6bb97 | blueswir1 | #define ESP_RFLAGS 0x7 |
96 | 5ad6bb97 | blueswir1 | #define ESP_WSYNO 0x7 |
97 | 5ad6bb97 | blueswir1 | #define ESP_CFG1 0x8 |
98 | 5ad6bb97 | blueswir1 | #define ESP_RRES1 0x9 |
99 | 5ad6bb97 | blueswir1 | #define ESP_WCCF 0x9 |
100 | 5ad6bb97 | blueswir1 | #define ESP_RRES2 0xa |
101 | 5ad6bb97 | blueswir1 | #define ESP_WTEST 0xa |
102 | 5ad6bb97 | blueswir1 | #define ESP_CFG2 0xb |
103 | 5ad6bb97 | blueswir1 | #define ESP_CFG3 0xc |
104 | 5ad6bb97 | blueswir1 | #define ESP_RES3 0xd |
105 | 5ad6bb97 | blueswir1 | #define ESP_TCHI 0xe |
106 | 5ad6bb97 | blueswir1 | #define ESP_RES4 0xf |
107 | 5ad6bb97 | blueswir1 | |
108 | 5ad6bb97 | blueswir1 | #define CMD_DMA 0x80 |
109 | 5ad6bb97 | blueswir1 | #define CMD_CMD 0x7f |
110 | 5ad6bb97 | blueswir1 | |
111 | 5ad6bb97 | blueswir1 | #define CMD_NOP 0x00 |
112 | 5ad6bb97 | blueswir1 | #define CMD_FLUSH 0x01 |
113 | 5ad6bb97 | blueswir1 | #define CMD_RESET 0x02 |
114 | 5ad6bb97 | blueswir1 | #define CMD_BUSRESET 0x03 |
115 | 5ad6bb97 | blueswir1 | #define CMD_TI 0x10 |
116 | 5ad6bb97 | blueswir1 | #define CMD_ICCS 0x11 |
117 | 5ad6bb97 | blueswir1 | #define CMD_MSGACC 0x12 |
118 | 0fd0eb21 | Blue Swirl | #define CMD_PAD 0x18 |
119 | 5ad6bb97 | blueswir1 | #define CMD_SATN 0x1a |
120 | 5e1e0a3b | Blue Swirl | #define CMD_SEL 0x41 |
121 | 5ad6bb97 | blueswir1 | #define CMD_SELATN 0x42 |
122 | 5ad6bb97 | blueswir1 | #define CMD_SELATNS 0x43 |
123 | 5ad6bb97 | blueswir1 | #define CMD_ENSEL 0x44 |
124 | 5ad6bb97 | blueswir1 | |
125 | 2f275b8f | bellard | #define STAT_DO 0x00 |
126 | 2f275b8f | bellard | #define STAT_DI 0x01 |
127 | 2f275b8f | bellard | #define STAT_CD 0x02 |
128 | 2f275b8f | bellard | #define STAT_ST 0x03 |
129 | 8dea1dd4 | blueswir1 | #define STAT_MO 0x06 |
130 | 8dea1dd4 | blueswir1 | #define STAT_MI 0x07 |
131 | 5ad6bb97 | blueswir1 | #define STAT_PIO_MASK 0x06 |
132 | 2f275b8f | bellard | |
133 | 2f275b8f | bellard | #define STAT_TC 0x10 |
134 | 4d611c9a | pbrook | #define STAT_PE 0x20 |
135 | 4d611c9a | pbrook | #define STAT_GE 0x40 |
136 | c73f96fd | blueswir1 | #define STAT_INT 0x80 |
137 | 2f275b8f | bellard | |
138 | 8dea1dd4 | blueswir1 | #define BUSID_DID 0x07 |
139 | 8dea1dd4 | blueswir1 | |
140 | 2f275b8f | bellard | #define INTR_FC 0x08 |
141 | 2f275b8f | bellard | #define INTR_BS 0x10 |
142 | 2f275b8f | bellard | #define INTR_DC 0x20 |
143 | 9e61bde5 | bellard | #define INTR_RST 0x80 |
144 | 2f275b8f | bellard | |
145 | 2f275b8f | bellard | #define SEQ_0 0x0 |
146 | 2f275b8f | bellard | #define SEQ_CD 0x4 |
147 | 2f275b8f | bellard | |
148 | 5ad6bb97 | blueswir1 | #define CFG1_RESREPT 0x40 |
149 | 5ad6bb97 | blueswir1 | |
150 | 5ad6bb97 | blueswir1 | #define TCHI_FAS100A 0x4 |
151 | 5ad6bb97 | blueswir1 | |
152 | c73f96fd | blueswir1 | static void esp_raise_irq(ESPState *s) |
153 | c73f96fd | blueswir1 | { |
154 | c73f96fd | blueswir1 | if (!(s->rregs[ESP_RSTAT] & STAT_INT)) {
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155 | c73f96fd | blueswir1 | s->rregs[ESP_RSTAT] |= STAT_INT; |
156 | c73f96fd | blueswir1 | qemu_irq_raise(s->irq); |
157 | dca47edd | Blue Swirl | DPRINTF("Raise IRQ\n");
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158 | c73f96fd | blueswir1 | } |
159 | c73f96fd | blueswir1 | } |
160 | c73f96fd | blueswir1 | |
161 | c73f96fd | blueswir1 | static void esp_lower_irq(ESPState *s) |
162 | c73f96fd | blueswir1 | { |
163 | c73f96fd | blueswir1 | if (s->rregs[ESP_RSTAT] & STAT_INT) {
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164 | c73f96fd | blueswir1 | s->rregs[ESP_RSTAT] &= ~STAT_INT; |
165 | c73f96fd | blueswir1 | qemu_irq_lower(s->irq); |
166 | dca47edd | Blue Swirl | DPRINTF("Lower IRQ\n");
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167 | c73f96fd | blueswir1 | } |
168 | c73f96fd | blueswir1 | } |
169 | c73f96fd | blueswir1 | |
170 | 22548760 | blueswir1 | static uint32_t get_cmd(ESPState *s, uint8_t *buf)
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171 | 2f275b8f | bellard | { |
172 | a917d384 | pbrook | uint32_t dmalen; |
173 | 2f275b8f | bellard | int target;
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174 | 2f275b8f | bellard | |
175 | 8dea1dd4 | blueswir1 | target = s->wregs[ESP_WBUSID] & BUSID_DID; |
176 | 4f6200f0 | bellard | if (s->dma) {
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177 | fc4d65da | blueswir1 | dmalen = s->rregs[ESP_TCLO] | (s->rregs[ESP_TCMID] << 8);
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178 | 8b17de88 | blueswir1 | s->dma_memory_read(s->dma_opaque, buf, dmalen); |
179 | 4f6200f0 | bellard | } else {
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180 | fc4d65da | blueswir1 | dmalen = s->ti_size; |
181 | fc4d65da | blueswir1 | memcpy(buf, s->ti_buf, dmalen); |
182 | f930d07e | blueswir1 | buf[0] = 0; |
183 | 4f6200f0 | bellard | } |
184 | fc4d65da | blueswir1 | DPRINTF("get_cmd: len %d target %d\n", dmalen, target);
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185 | 2e5d83bb | pbrook | |
186 | 2f275b8f | bellard | s->ti_size = 0;
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187 | 4f6200f0 | bellard | s->ti_rptr = 0;
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188 | 4f6200f0 | bellard | s->ti_wptr = 0;
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189 | 2f275b8f | bellard | |
190 | a917d384 | pbrook | if (s->current_dev) {
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191 | a917d384 | pbrook | /* Started a new command before the old one finished. Cancel it. */
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192 | d52affa7 | Gerd Hoffmann | s->current_dev->info->cancel_io(s->current_dev, 0);
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193 | a917d384 | pbrook | s->async_len = 0;
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194 | a917d384 | pbrook | } |
195 | a917d384 | pbrook | |
196 | ca9c39fa | Gerd Hoffmann | if (target >= ESP_MAX_DEVS || !s->bus.devs[target]) {
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197 | 2e5d83bb | pbrook | // No such drive
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198 | c73f96fd | blueswir1 | s->rregs[ESP_RSTAT] = 0;
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199 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RINTR] = INTR_DC; |
200 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RSEQ] = SEQ_0; |
201 | c73f96fd | blueswir1 | esp_raise_irq(s); |
202 | f930d07e | blueswir1 | return 0; |
203 | 2f275b8f | bellard | } |
204 | ca9c39fa | Gerd Hoffmann | s->current_dev = s->bus.devs[target]; |
205 | 9f149aa9 | pbrook | return dmalen;
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206 | 9f149aa9 | pbrook | } |
207 | 9f149aa9 | pbrook | |
208 | f2818f22 | Artyom Tarasenko | static void do_busid_cmd(ESPState *s, uint8_t *buf, uint8_t busid) |
209 | 9f149aa9 | pbrook | { |
210 | 9f149aa9 | pbrook | int32_t datalen; |
211 | 9f149aa9 | pbrook | int lun;
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212 | 9f149aa9 | pbrook | |
213 | f2818f22 | Artyom Tarasenko | DPRINTF("do_busid_cmd: busid 0x%x\n", busid);
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214 | f2818f22 | Artyom Tarasenko | lun = busid & 7;
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215 | d52affa7 | Gerd Hoffmann | datalen = s->current_dev->info->send_command(s->current_dev, 0, buf, lun);
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216 | 67e999be | bellard | s->ti_size = datalen; |
217 | 67e999be | bellard | if (datalen != 0) { |
218 | c73f96fd | blueswir1 | s->rregs[ESP_RSTAT] = STAT_TC; |
219 | a917d384 | pbrook | s->dma_left = 0;
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220 | 6787f5fa | pbrook | s->dma_counter = 0;
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221 | 2e5d83bb | pbrook | if (datalen > 0) { |
222 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RSTAT] |= STAT_DI; |
223 | d52affa7 | Gerd Hoffmann | s->current_dev->info->read_data(s->current_dev, 0);
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224 | 2e5d83bb | pbrook | } else {
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225 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RSTAT] |= STAT_DO; |
226 | d52affa7 | Gerd Hoffmann | s->current_dev->info->write_data(s->current_dev, 0);
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227 | b9788fc4 | bellard | } |
228 | 2f275b8f | bellard | } |
229 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RINTR] = INTR_BS | INTR_FC; |
230 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RSEQ] = SEQ_CD; |
231 | c73f96fd | blueswir1 | esp_raise_irq(s); |
232 | 2f275b8f | bellard | } |
233 | 2f275b8f | bellard | |
234 | f2818f22 | Artyom Tarasenko | static void do_cmd(ESPState *s, uint8_t *buf) |
235 | f2818f22 | Artyom Tarasenko | { |
236 | f2818f22 | Artyom Tarasenko | uint8_t busid = buf[0];
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237 | f2818f22 | Artyom Tarasenko | |
238 | f2818f22 | Artyom Tarasenko | do_busid_cmd(s, &buf[1], busid);
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239 | f2818f22 | Artyom Tarasenko | } |
240 | f2818f22 | Artyom Tarasenko | |
241 | 9f149aa9 | pbrook | static void handle_satn(ESPState *s) |
242 | 9f149aa9 | pbrook | { |
243 | 9f149aa9 | pbrook | uint8_t buf[32];
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244 | 9f149aa9 | pbrook | int len;
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245 | 9f149aa9 | pbrook | |
246 | 9f149aa9 | pbrook | len = get_cmd(s, buf); |
247 | 9f149aa9 | pbrook | if (len)
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248 | 9f149aa9 | pbrook | do_cmd(s, buf); |
249 | 9f149aa9 | pbrook | } |
250 | 9f149aa9 | pbrook | |
251 | f2818f22 | Artyom Tarasenko | static void handle_s_without_atn(ESPState *s) |
252 | f2818f22 | Artyom Tarasenko | { |
253 | f2818f22 | Artyom Tarasenko | uint8_t buf[32];
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254 | f2818f22 | Artyom Tarasenko | int len;
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255 | f2818f22 | Artyom Tarasenko | |
256 | f2818f22 | Artyom Tarasenko | len = get_cmd(s, buf); |
257 | f2818f22 | Artyom Tarasenko | if (len) {
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258 | f2818f22 | Artyom Tarasenko | do_busid_cmd(s, buf, 0);
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259 | f2818f22 | Artyom Tarasenko | } |
260 | f2818f22 | Artyom Tarasenko | } |
261 | f2818f22 | Artyom Tarasenko | |
262 | 9f149aa9 | pbrook | static void handle_satn_stop(ESPState *s) |
263 | 9f149aa9 | pbrook | { |
264 | 9f149aa9 | pbrook | s->cmdlen = get_cmd(s, s->cmdbuf); |
265 | 9f149aa9 | pbrook | if (s->cmdlen) {
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266 | 9f149aa9 | pbrook | DPRINTF("Set ATN & Stop: cmdlen %d\n", s->cmdlen);
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267 | 9f149aa9 | pbrook | s->do_cmd = 1;
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268 | c73f96fd | blueswir1 | s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD; |
269 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RINTR] = INTR_BS | INTR_FC; |
270 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RSEQ] = SEQ_CD; |
271 | c73f96fd | blueswir1 | esp_raise_irq(s); |
272 | 9f149aa9 | pbrook | } |
273 | 9f149aa9 | pbrook | } |
274 | 9f149aa9 | pbrook | |
275 | 0fc5c15a | pbrook | static void write_response(ESPState *s) |
276 | 2f275b8f | bellard | { |
277 | 0fc5c15a | pbrook | DPRINTF("Transfer status (sense=%d)\n", s->sense);
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278 | 0fc5c15a | pbrook | s->ti_buf[0] = s->sense;
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279 | 0fc5c15a | pbrook | s->ti_buf[1] = 0; |
280 | 4f6200f0 | bellard | if (s->dma) {
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281 | 8b17de88 | blueswir1 | s->dma_memory_write(s->dma_opaque, s->ti_buf, 2);
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282 | c73f96fd | blueswir1 | s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST; |
283 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RINTR] = INTR_BS | INTR_FC; |
284 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RSEQ] = SEQ_CD; |
285 | 4f6200f0 | bellard | } else {
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286 | f930d07e | blueswir1 | s->ti_size = 2;
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287 | f930d07e | blueswir1 | s->ti_rptr = 0;
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288 | f930d07e | blueswir1 | s->ti_wptr = 0;
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289 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RFLAGS] = 2;
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290 | 4f6200f0 | bellard | } |
291 | c73f96fd | blueswir1 | esp_raise_irq(s); |
292 | 2f275b8f | bellard | } |
293 | 4f6200f0 | bellard | |
294 | a917d384 | pbrook | static void esp_dma_done(ESPState *s) |
295 | a917d384 | pbrook | { |
296 | c73f96fd | blueswir1 | s->rregs[ESP_RSTAT] |= STAT_TC; |
297 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RINTR] = INTR_BS; |
298 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RSEQ] = 0;
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299 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RFLAGS] = 0;
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300 | 5ad6bb97 | blueswir1 | s->rregs[ESP_TCLO] = 0;
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301 | 5ad6bb97 | blueswir1 | s->rregs[ESP_TCMID] = 0;
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302 | c73f96fd | blueswir1 | esp_raise_irq(s); |
303 | a917d384 | pbrook | } |
304 | a917d384 | pbrook | |
305 | 4d611c9a | pbrook | static void esp_do_dma(ESPState *s) |
306 | 4d611c9a | pbrook | { |
307 | 67e999be | bellard | uint32_t len; |
308 | 4d611c9a | pbrook | int to_device;
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309 | a917d384 | pbrook | |
310 | 67e999be | bellard | to_device = (s->ti_size < 0);
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311 | a917d384 | pbrook | len = s->dma_left; |
312 | 4d611c9a | pbrook | if (s->do_cmd) {
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313 | 4d611c9a | pbrook | DPRINTF("command len %d + %d\n", s->cmdlen, len);
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314 | 8b17de88 | blueswir1 | s->dma_memory_read(s->dma_opaque, &s->cmdbuf[s->cmdlen], len); |
315 | 4d611c9a | pbrook | s->ti_size = 0;
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316 | 4d611c9a | pbrook | s->cmdlen = 0;
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317 | 4d611c9a | pbrook | s->do_cmd = 0;
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318 | 4d611c9a | pbrook | do_cmd(s, s->cmdbuf); |
319 | 4d611c9a | pbrook | return;
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320 | a917d384 | pbrook | } |
321 | a917d384 | pbrook | if (s->async_len == 0) { |
322 | a917d384 | pbrook | /* Defer until data is available. */
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323 | a917d384 | pbrook | return;
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324 | a917d384 | pbrook | } |
325 | a917d384 | pbrook | if (len > s->async_len) {
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326 | a917d384 | pbrook | len = s->async_len; |
327 | a917d384 | pbrook | } |
328 | a917d384 | pbrook | if (to_device) {
|
329 | 8b17de88 | blueswir1 | s->dma_memory_read(s->dma_opaque, s->async_buf, len); |
330 | 4d611c9a | pbrook | } else {
|
331 | 8b17de88 | blueswir1 | s->dma_memory_write(s->dma_opaque, s->async_buf, len); |
332 | a917d384 | pbrook | } |
333 | a917d384 | pbrook | s->dma_left -= len; |
334 | a917d384 | pbrook | s->async_buf += len; |
335 | a917d384 | pbrook | s->async_len -= len; |
336 | 6787f5fa | pbrook | if (to_device)
|
337 | 6787f5fa | pbrook | s->ti_size += len; |
338 | 6787f5fa | pbrook | else
|
339 | 6787f5fa | pbrook | s->ti_size -= len; |
340 | a917d384 | pbrook | if (s->async_len == 0) { |
341 | 4d611c9a | pbrook | if (to_device) {
|
342 | 67e999be | bellard | // ti_size is negative
|
343 | d52affa7 | Gerd Hoffmann | s->current_dev->info->write_data(s->current_dev, 0);
|
344 | 4d611c9a | pbrook | } else {
|
345 | d52affa7 | Gerd Hoffmann | s->current_dev->info->read_data(s->current_dev, 0);
|
346 | 6787f5fa | pbrook | /* If there is still data to be read from the device then
|
347 | 8dea1dd4 | blueswir1 | complete the DMA operation immediately. Otherwise defer
|
348 | 6787f5fa | pbrook | until the scsi layer has completed. */
|
349 | 6787f5fa | pbrook | if (s->dma_left == 0 && s->ti_size > 0) { |
350 | 6787f5fa | pbrook | esp_dma_done(s); |
351 | 6787f5fa | pbrook | } |
352 | 4d611c9a | pbrook | } |
353 | 6787f5fa | pbrook | } else {
|
354 | 6787f5fa | pbrook | /* Partially filled a scsi buffer. Complete immediately. */
|
355 | a917d384 | pbrook | esp_dma_done(s); |
356 | a917d384 | pbrook | } |
357 | 4d611c9a | pbrook | } |
358 | 4d611c9a | pbrook | |
359 | d52affa7 | Gerd Hoffmann | static void esp_command_complete(SCSIBus *bus, int reason, uint32_t tag, |
360 | a917d384 | pbrook | uint32_t arg) |
361 | 2e5d83bb | pbrook | { |
362 | d52affa7 | Gerd Hoffmann | ESPState *s = DO_UPCAST(ESPState, busdev.qdev, bus->qbus.parent); |
363 | 2e5d83bb | pbrook | |
364 | 4d611c9a | pbrook | if (reason == SCSI_REASON_DONE) {
|
365 | 4d611c9a | pbrook | DPRINTF("SCSI Command complete\n");
|
366 | 4d611c9a | pbrook | if (s->ti_size != 0) |
367 | 4d611c9a | pbrook | DPRINTF("SCSI command completed unexpectedly\n");
|
368 | 4d611c9a | pbrook | s->ti_size = 0;
|
369 | a917d384 | pbrook | s->dma_left = 0;
|
370 | a917d384 | pbrook | s->async_len = 0;
|
371 | a917d384 | pbrook | if (arg)
|
372 | 4d611c9a | pbrook | DPRINTF("Command failed\n");
|
373 | a917d384 | pbrook | s->sense = arg; |
374 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RSTAT] = STAT_ST; |
375 | a917d384 | pbrook | esp_dma_done(s); |
376 | a917d384 | pbrook | s->current_dev = NULL;
|
377 | 4d611c9a | pbrook | } else {
|
378 | 4d611c9a | pbrook | DPRINTF("transfer %d/%d\n", s->dma_left, s->ti_size);
|
379 | a917d384 | pbrook | s->async_len = arg; |
380 | d52affa7 | Gerd Hoffmann | s->async_buf = s->current_dev->info->get_buf(s->current_dev, 0);
|
381 | 6787f5fa | pbrook | if (s->dma_left) {
|
382 | a917d384 | pbrook | esp_do_dma(s); |
383 | 6787f5fa | pbrook | } else if (s->dma_counter != 0 && s->ti_size <= 0) { |
384 | 6787f5fa | pbrook | /* If this was the last part of a DMA transfer then the
|
385 | 6787f5fa | pbrook | completion interrupt is deferred to here. */
|
386 | 6787f5fa | pbrook | esp_dma_done(s); |
387 | 6787f5fa | pbrook | } |
388 | 4d611c9a | pbrook | } |
389 | 2e5d83bb | pbrook | } |
390 | 2e5d83bb | pbrook | |
391 | 2f275b8f | bellard | static void handle_ti(ESPState *s) |
392 | 2f275b8f | bellard | { |
393 | 4d611c9a | pbrook | uint32_t dmalen, minlen; |
394 | 2f275b8f | bellard | |
395 | 5ad6bb97 | blueswir1 | dmalen = s->rregs[ESP_TCLO] | (s->rregs[ESP_TCMID] << 8);
|
396 | db59203d | pbrook | if (dmalen==0) { |
397 | db59203d | pbrook | dmalen=0x10000;
|
398 | db59203d | pbrook | } |
399 | 6787f5fa | pbrook | s->dma_counter = dmalen; |
400 | db59203d | pbrook | |
401 | 9f149aa9 | pbrook | if (s->do_cmd)
|
402 | 9f149aa9 | pbrook | minlen = (dmalen < 32) ? dmalen : 32; |
403 | 67e999be | bellard | else if (s->ti_size < 0) |
404 | 67e999be | bellard | minlen = (dmalen < -s->ti_size) ? dmalen : -s->ti_size; |
405 | 9f149aa9 | pbrook | else
|
406 | 9f149aa9 | pbrook | minlen = (dmalen < s->ti_size) ? dmalen : s->ti_size; |
407 | db59203d | pbrook | DPRINTF("Transfer Information len %d\n", minlen);
|
408 | 4f6200f0 | bellard | if (s->dma) {
|
409 | 4d611c9a | pbrook | s->dma_left = minlen; |
410 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RSTAT] &= ~STAT_TC; |
411 | 4d611c9a | pbrook | esp_do_dma(s); |
412 | 9f149aa9 | pbrook | } else if (s->do_cmd) { |
413 | 9f149aa9 | pbrook | DPRINTF("command len %d\n", s->cmdlen);
|
414 | 9f149aa9 | pbrook | s->ti_size = 0;
|
415 | 9f149aa9 | pbrook | s->cmdlen = 0;
|
416 | 9f149aa9 | pbrook | s->do_cmd = 0;
|
417 | 9f149aa9 | pbrook | do_cmd(s, s->cmdbuf); |
418 | 9f149aa9 | pbrook | return;
|
419 | 9f149aa9 | pbrook | } |
420 | 2f275b8f | bellard | } |
421 | 2f275b8f | bellard | |
422 | 85948643 | Blue Swirl | static void esp_hard_reset(DeviceState *d) |
423 | 6f7e9aec | bellard | { |
424 | 63235df8 | Blue Swirl | ESPState *s = container_of(d, ESPState, busdev.qdev); |
425 | 67e999be | bellard | |
426 | 5aca8c3b | blueswir1 | memset(s->rregs, 0, ESP_REGS);
|
427 | 5aca8c3b | blueswir1 | memset(s->wregs, 0, ESP_REGS);
|
428 | 5ad6bb97 | blueswir1 | s->rregs[ESP_TCHI] = TCHI_FAS100A; // Indicate fas100a
|
429 | 4e9aec74 | pbrook | s->ti_size = 0;
|
430 | 4e9aec74 | pbrook | s->ti_rptr = 0;
|
431 | 4e9aec74 | pbrook | s->ti_wptr = 0;
|
432 | 4e9aec74 | pbrook | s->dma = 0;
|
433 | 9f149aa9 | pbrook | s->do_cmd = 0;
|
434 | 8dea1dd4 | blueswir1 | |
435 | 8dea1dd4 | blueswir1 | s->rregs[ESP_CFG1] = 7;
|
436 | 6f7e9aec | bellard | } |
437 | 6f7e9aec | bellard | |
438 | 85948643 | Blue Swirl | static void esp_soft_reset(DeviceState *d) |
439 | 85948643 | Blue Swirl | { |
440 | 85948643 | Blue Swirl | ESPState *s = container_of(d, ESPState, busdev.qdev); |
441 | 85948643 | Blue Swirl | |
442 | 85948643 | Blue Swirl | qemu_irq_lower(s->irq); |
443 | 85948643 | Blue Swirl | esp_hard_reset(d); |
444 | 85948643 | Blue Swirl | } |
445 | 85948643 | Blue Swirl | |
446 | 2d069bab | blueswir1 | static void parent_esp_reset(void *opaque, int irq, int level) |
447 | 2d069bab | blueswir1 | { |
448 | 85948643 | Blue Swirl | if (level) {
|
449 | 85948643 | Blue Swirl | esp_soft_reset(opaque); |
450 | 85948643 | Blue Swirl | } |
451 | 2d069bab | blueswir1 | } |
452 | 2d069bab | blueswir1 | |
453 | c227f099 | Anthony Liguori | static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr) |
454 | 6f7e9aec | bellard | { |
455 | 6f7e9aec | bellard | ESPState *s = opaque; |
456 | 2814df28 | Blue Swirl | uint32_t saddr, old_val; |
457 | 6f7e9aec | bellard | |
458 | e64d7d59 | blueswir1 | saddr = addr >> s->it_shift; |
459 | 9e61bde5 | bellard | DPRINTF("read reg[%d]: 0x%2.2x\n", saddr, s->rregs[saddr]);
|
460 | 6f7e9aec | bellard | switch (saddr) {
|
461 | 5ad6bb97 | blueswir1 | case ESP_FIFO:
|
462 | f930d07e | blueswir1 | if (s->ti_size > 0) { |
463 | f930d07e | blueswir1 | s->ti_size--; |
464 | 5ad6bb97 | blueswir1 | if ((s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) { |
465 | 8dea1dd4 | blueswir1 | /* Data out. */
|
466 | 8dea1dd4 | blueswir1 | ESP_ERROR("PIO data read not implemented\n");
|
467 | 5ad6bb97 | blueswir1 | s->rregs[ESP_FIFO] = 0;
|
468 | 2e5d83bb | pbrook | } else {
|
469 | 5ad6bb97 | blueswir1 | s->rregs[ESP_FIFO] = s->ti_buf[s->ti_rptr++]; |
470 | 2e5d83bb | pbrook | } |
471 | c73f96fd | blueswir1 | esp_raise_irq(s); |
472 | f930d07e | blueswir1 | } |
473 | f930d07e | blueswir1 | if (s->ti_size == 0) { |
474 | 4f6200f0 | bellard | s->ti_rptr = 0;
|
475 | 4f6200f0 | bellard | s->ti_wptr = 0;
|
476 | 4f6200f0 | bellard | } |
477 | f930d07e | blueswir1 | break;
|
478 | 5ad6bb97 | blueswir1 | case ESP_RINTR:
|
479 | 2814df28 | Blue Swirl | /* Clear sequence step, interrupt register and all status bits
|
480 | 2814df28 | Blue Swirl | except TC */
|
481 | 2814df28 | Blue Swirl | old_val = s->rregs[ESP_RINTR]; |
482 | 2814df28 | Blue Swirl | s->rregs[ESP_RINTR] = 0;
|
483 | 2814df28 | Blue Swirl | s->rregs[ESP_RSTAT] &= ~STAT_TC; |
484 | 2814df28 | Blue Swirl | s->rregs[ESP_RSEQ] = SEQ_CD; |
485 | c73f96fd | blueswir1 | esp_lower_irq(s); |
486 | 2814df28 | Blue Swirl | |
487 | 2814df28 | Blue Swirl | return old_val;
|
488 | 6f7e9aec | bellard | default:
|
489 | f930d07e | blueswir1 | break;
|
490 | 6f7e9aec | bellard | } |
491 | 2f275b8f | bellard | return s->rregs[saddr];
|
492 | 6f7e9aec | bellard | } |
493 | 6f7e9aec | bellard | |
494 | c227f099 | Anthony Liguori | static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
495 | 6f7e9aec | bellard | { |
496 | 6f7e9aec | bellard | ESPState *s = opaque; |
497 | 6f7e9aec | bellard | uint32_t saddr; |
498 | 6f7e9aec | bellard | |
499 | e64d7d59 | blueswir1 | saddr = addr >> s->it_shift; |
500 | 5ad6bb97 | blueswir1 | DPRINTF("write reg[%d]: 0x%2.2x -> 0x%2.2x\n", saddr, s->wregs[saddr],
|
501 | 5ad6bb97 | blueswir1 | val); |
502 | 6f7e9aec | bellard | switch (saddr) {
|
503 | 5ad6bb97 | blueswir1 | case ESP_TCLO:
|
504 | 5ad6bb97 | blueswir1 | case ESP_TCMID:
|
505 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RSTAT] &= ~STAT_TC; |
506 | 4f6200f0 | bellard | break;
|
507 | 5ad6bb97 | blueswir1 | case ESP_FIFO:
|
508 | 9f149aa9 | pbrook | if (s->do_cmd) {
|
509 | 9f149aa9 | pbrook | s->cmdbuf[s->cmdlen++] = val & 0xff;
|
510 | 8dea1dd4 | blueswir1 | } else if (s->ti_size == TI_BUFSZ - 1) { |
511 | 8dea1dd4 | blueswir1 | ESP_ERROR("fifo overrun\n");
|
512 | 2e5d83bb | pbrook | } else {
|
513 | 2e5d83bb | pbrook | s->ti_size++; |
514 | 2e5d83bb | pbrook | s->ti_buf[s->ti_wptr++] = val & 0xff;
|
515 | 2e5d83bb | pbrook | } |
516 | f930d07e | blueswir1 | break;
|
517 | 5ad6bb97 | blueswir1 | case ESP_CMD:
|
518 | 4f6200f0 | bellard | s->rregs[saddr] = val; |
519 | 5ad6bb97 | blueswir1 | if (val & CMD_DMA) {
|
520 | f930d07e | blueswir1 | s->dma = 1;
|
521 | 6787f5fa | pbrook | /* Reload DMA counter. */
|
522 | 5ad6bb97 | blueswir1 | s->rregs[ESP_TCLO] = s->wregs[ESP_TCLO]; |
523 | 5ad6bb97 | blueswir1 | s->rregs[ESP_TCMID] = s->wregs[ESP_TCMID]; |
524 | f930d07e | blueswir1 | } else {
|
525 | f930d07e | blueswir1 | s->dma = 0;
|
526 | f930d07e | blueswir1 | } |
527 | 5ad6bb97 | blueswir1 | switch(val & CMD_CMD) {
|
528 | 5ad6bb97 | blueswir1 | case CMD_NOP:
|
529 | f930d07e | blueswir1 | DPRINTF("NOP (%2.2x)\n", val);
|
530 | f930d07e | blueswir1 | break;
|
531 | 5ad6bb97 | blueswir1 | case CMD_FLUSH:
|
532 | f930d07e | blueswir1 | DPRINTF("Flush FIFO (%2.2x)\n", val);
|
533 | 9e61bde5 | bellard | //s->ti_size = 0;
|
534 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RINTR] = INTR_FC; |
535 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RSEQ] = 0;
|
536 | a214c598 | blueswir1 | s->rregs[ESP_RFLAGS] = 0;
|
537 | f930d07e | blueswir1 | break;
|
538 | 5ad6bb97 | blueswir1 | case CMD_RESET:
|
539 | f930d07e | blueswir1 | DPRINTF("Chip reset (%2.2x)\n", val);
|
540 | 85948643 | Blue Swirl | esp_soft_reset(&s->busdev.qdev); |
541 | f930d07e | blueswir1 | break;
|
542 | 5ad6bb97 | blueswir1 | case CMD_BUSRESET:
|
543 | f930d07e | blueswir1 | DPRINTF("Bus reset (%2.2x)\n", val);
|
544 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RINTR] = INTR_RST; |
545 | 5ad6bb97 | blueswir1 | if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) {
|
546 | c73f96fd | blueswir1 | esp_raise_irq(s); |
547 | 9e61bde5 | bellard | } |
548 | f930d07e | blueswir1 | break;
|
549 | 5ad6bb97 | blueswir1 | case CMD_TI:
|
550 | f930d07e | blueswir1 | handle_ti(s); |
551 | f930d07e | blueswir1 | break;
|
552 | 5ad6bb97 | blueswir1 | case CMD_ICCS:
|
553 | f930d07e | blueswir1 | DPRINTF("Initiator Command Complete Sequence (%2.2x)\n", val);
|
554 | f930d07e | blueswir1 | write_response(s); |
555 | 4bf5801d | blueswir1 | s->rregs[ESP_RINTR] = INTR_FC; |
556 | 4bf5801d | blueswir1 | s->rregs[ESP_RSTAT] |= STAT_MI; |
557 | f930d07e | blueswir1 | break;
|
558 | 5ad6bb97 | blueswir1 | case CMD_MSGACC:
|
559 | f930d07e | blueswir1 | DPRINTF("Message Accepted (%2.2x)\n", val);
|
560 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RINTR] = INTR_DC; |
561 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RSEQ] = 0;
|
562 | 4e2a68c1 | Artyom Tarasenko | s->rregs[ESP_RFLAGS] = 0;
|
563 | 4e2a68c1 | Artyom Tarasenko | esp_raise_irq(s); |
564 | f930d07e | blueswir1 | break;
|
565 | 0fd0eb21 | Blue Swirl | case CMD_PAD:
|
566 | 0fd0eb21 | Blue Swirl | DPRINTF("Transfer padding (%2.2x)\n", val);
|
567 | 0fd0eb21 | Blue Swirl | s->rregs[ESP_RSTAT] = STAT_TC; |
568 | 0fd0eb21 | Blue Swirl | s->rregs[ESP_RINTR] = INTR_FC; |
569 | 0fd0eb21 | Blue Swirl | s->rregs[ESP_RSEQ] = 0;
|
570 | 0fd0eb21 | Blue Swirl | break;
|
571 | 5ad6bb97 | blueswir1 | case CMD_SATN:
|
572 | f930d07e | blueswir1 | DPRINTF("Set ATN (%2.2x)\n", val);
|
573 | f930d07e | blueswir1 | break;
|
574 | 5e1e0a3b | Blue Swirl | case CMD_SEL:
|
575 | 5e1e0a3b | Blue Swirl | DPRINTF("Select without ATN (%2.2x)\n", val);
|
576 | f2818f22 | Artyom Tarasenko | handle_s_without_atn(s); |
577 | 5e1e0a3b | Blue Swirl | break;
|
578 | 5ad6bb97 | blueswir1 | case CMD_SELATN:
|
579 | 5e1e0a3b | Blue Swirl | DPRINTF("Select with ATN (%2.2x)\n", val);
|
580 | f930d07e | blueswir1 | handle_satn(s); |
581 | f930d07e | blueswir1 | break;
|
582 | 5ad6bb97 | blueswir1 | case CMD_SELATNS:
|
583 | 5e1e0a3b | Blue Swirl | DPRINTF("Select with ATN & stop (%2.2x)\n", val);
|
584 | f930d07e | blueswir1 | handle_satn_stop(s); |
585 | f930d07e | blueswir1 | break;
|
586 | 5ad6bb97 | blueswir1 | case CMD_ENSEL:
|
587 | 74ec6048 | blueswir1 | DPRINTF("Enable selection (%2.2x)\n", val);
|
588 | e3926838 | blueswir1 | s->rregs[ESP_RINTR] = 0;
|
589 | 74ec6048 | blueswir1 | break;
|
590 | f930d07e | blueswir1 | default:
|
591 | 8dea1dd4 | blueswir1 | ESP_ERROR("Unhandled ESP command (%2.2x)\n", val);
|
592 | f930d07e | blueswir1 | break;
|
593 | f930d07e | blueswir1 | } |
594 | f930d07e | blueswir1 | break;
|
595 | 5ad6bb97 | blueswir1 | case ESP_WBUSID ... ESP_WSYNO:
|
596 | f930d07e | blueswir1 | break;
|
597 | 5ad6bb97 | blueswir1 | case ESP_CFG1:
|
598 | 4f6200f0 | bellard | s->rregs[saddr] = val; |
599 | 4f6200f0 | bellard | break;
|
600 | 5ad6bb97 | blueswir1 | case ESP_WCCF ... ESP_WTEST:
|
601 | 4f6200f0 | bellard | break;
|
602 | b44c08fa | blueswir1 | case ESP_CFG2 ... ESP_RES4:
|
603 | 4f6200f0 | bellard | s->rregs[saddr] = val; |
604 | 4f6200f0 | bellard | break;
|
605 | 6f7e9aec | bellard | default:
|
606 | 8dea1dd4 | blueswir1 | ESP_ERROR("invalid write of 0x%02x at [0x%x]\n", val, saddr);
|
607 | 8dea1dd4 | blueswir1 | return;
|
608 | 6f7e9aec | bellard | } |
609 | 2f275b8f | bellard | s->wregs[saddr] = val; |
610 | 6f7e9aec | bellard | } |
611 | 6f7e9aec | bellard | |
612 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const esp_mem_read[3] = { |
613 | 6f7e9aec | bellard | esp_mem_readb, |
614 | 7c560456 | blueswir1 | NULL,
|
615 | 7c560456 | blueswir1 | NULL,
|
616 | 6f7e9aec | bellard | }; |
617 | 6f7e9aec | bellard | |
618 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const esp_mem_write[3] = { |
619 | 6f7e9aec | bellard | esp_mem_writeb, |
620 | 7c560456 | blueswir1 | NULL,
|
621 | daa41b00 | blueswir1 | esp_mem_writeb, |
622 | 6f7e9aec | bellard | }; |
623 | 6f7e9aec | bellard | |
624 | cc9952f3 | Blue Swirl | static const VMStateDescription vmstate_esp = { |
625 | cc9952f3 | Blue Swirl | .name ="esp",
|
626 | cc9952f3 | Blue Swirl | .version_id = 3,
|
627 | cc9952f3 | Blue Swirl | .minimum_version_id = 3,
|
628 | cc9952f3 | Blue Swirl | .minimum_version_id_old = 3,
|
629 | cc9952f3 | Blue Swirl | .fields = (VMStateField []) { |
630 | cc9952f3 | Blue Swirl | VMSTATE_BUFFER(rregs, ESPState), |
631 | cc9952f3 | Blue Swirl | VMSTATE_BUFFER(wregs, ESPState), |
632 | cc9952f3 | Blue Swirl | VMSTATE_INT32(ti_size, ESPState), |
633 | cc9952f3 | Blue Swirl | VMSTATE_UINT32(ti_rptr, ESPState), |
634 | cc9952f3 | Blue Swirl | VMSTATE_UINT32(ti_wptr, ESPState), |
635 | cc9952f3 | Blue Swirl | VMSTATE_BUFFER(ti_buf, ESPState), |
636 | cc9952f3 | Blue Swirl | VMSTATE_UINT32(sense, ESPState), |
637 | cc9952f3 | Blue Swirl | VMSTATE_UINT32(dma, ESPState), |
638 | cc9952f3 | Blue Swirl | VMSTATE_BUFFER(cmdbuf, ESPState), |
639 | cc9952f3 | Blue Swirl | VMSTATE_UINT32(cmdlen, ESPState), |
640 | cc9952f3 | Blue Swirl | VMSTATE_UINT32(do_cmd, ESPState), |
641 | cc9952f3 | Blue Swirl | VMSTATE_UINT32(dma_left, ESPState), |
642 | cc9952f3 | Blue Swirl | VMSTATE_END_OF_LIST() |
643 | cc9952f3 | Blue Swirl | } |
644 | cc9952f3 | Blue Swirl | }; |
645 | 6f7e9aec | bellard | |
646 | c227f099 | Anthony Liguori | void esp_init(target_phys_addr_t espaddr, int it_shift, |
647 | ff9868ec | Blue Swirl | ESPDMAMemoryReadWriteFunc dma_memory_read, |
648 | ff9868ec | Blue Swirl | ESPDMAMemoryReadWriteFunc dma_memory_write, |
649 | cfb9de9c | Paul Brook | void *dma_opaque, qemu_irq irq, qemu_irq *reset)
|
650 | 6f7e9aec | bellard | { |
651 | cfb9de9c | Paul Brook | DeviceState *dev; |
652 | cfb9de9c | Paul Brook | SysBusDevice *s; |
653 | ee6847d1 | Gerd Hoffmann | ESPState *esp; |
654 | cfb9de9c | Paul Brook | |
655 | cfb9de9c | Paul Brook | dev = qdev_create(NULL, "esp"); |
656 | ee6847d1 | Gerd Hoffmann | esp = DO_UPCAST(ESPState, busdev.qdev, dev); |
657 | ee6847d1 | Gerd Hoffmann | esp->dma_memory_read = dma_memory_read; |
658 | ee6847d1 | Gerd Hoffmann | esp->dma_memory_write = dma_memory_write; |
659 | ee6847d1 | Gerd Hoffmann | esp->dma_opaque = dma_opaque; |
660 | ee6847d1 | Gerd Hoffmann | esp->it_shift = it_shift; |
661 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
662 | cfb9de9c | Paul Brook | s = sysbus_from_qdev(dev); |
663 | cfb9de9c | Paul Brook | sysbus_connect_irq(s, 0, irq);
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664 | cfb9de9c | Paul Brook | sysbus_mmio_map(s, 0, espaddr);
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665 | 74ff8d90 | Blue Swirl | *reset = qdev_get_gpio_in(dev, 0);
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666 | cfb9de9c | Paul Brook | } |
667 | 6f7e9aec | bellard | |
668 | 81a322d4 | Gerd Hoffmann | static int esp_init1(SysBusDevice *dev) |
669 | cfb9de9c | Paul Brook | { |
670 | cfb9de9c | Paul Brook | ESPState *s = FROM_SYSBUS(ESPState, dev); |
671 | cfb9de9c | Paul Brook | int esp_io_memory;
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672 | 6f7e9aec | bellard | |
673 | cfb9de9c | Paul Brook | sysbus_init_irq(dev, &s->irq); |
674 | cfb9de9c | Paul Brook | assert(s->it_shift != -1);
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675 | 6f7e9aec | bellard | |
676 | 1eed09cb | Avi Kivity | esp_io_memory = cpu_register_io_memory(esp_mem_read, esp_mem_write, s); |
677 | cfb9de9c | Paul Brook | sysbus_init_mmio(dev, ESP_REGS << s->it_shift, esp_io_memory); |
678 | 6f7e9aec | bellard | |
679 | 067a3ddc | Paul Brook | qdev_init_gpio_in(&dev->qdev, parent_esp_reset, 1);
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680 | 2d069bab | blueswir1 | |
681 | ca9c39fa | Gerd Hoffmann | scsi_bus_new(&s->bus, &dev->qdev, 0, ESP_MAX_DEVS, esp_command_complete);
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682 | ca9c39fa | Gerd Hoffmann | scsi_bus_legacy_handle_cmdline(&s->bus); |
683 | 81a322d4 | Gerd Hoffmann | return 0; |
684 | 67e999be | bellard | } |
685 | cfb9de9c | Paul Brook | |
686 | 63235df8 | Blue Swirl | static SysBusDeviceInfo esp_info = {
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687 | 63235df8 | Blue Swirl | .init = esp_init1, |
688 | 63235df8 | Blue Swirl | .qdev.name = "esp",
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689 | 63235df8 | Blue Swirl | .qdev.size = sizeof(ESPState),
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690 | 63235df8 | Blue Swirl | .qdev.vmsd = &vmstate_esp, |
691 | 85948643 | Blue Swirl | .qdev.reset = esp_hard_reset, |
692 | 63235df8 | Blue Swirl | .qdev.props = (Property[]) { |
693 | 63235df8 | Blue Swirl | {.name = NULL}
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694 | 63235df8 | Blue Swirl | } |
695 | 63235df8 | Blue Swirl | }; |
696 | 63235df8 | Blue Swirl | |
697 | cfb9de9c | Paul Brook | static void esp_register_devices(void) |
698 | cfb9de9c | Paul Brook | { |
699 | 63235df8 | Blue Swirl | sysbus_register_withprop(&esp_info); |
700 | cfb9de9c | Paul Brook | } |
701 | cfb9de9c | Paul Brook | |
702 | cfb9de9c | Paul Brook | device_init(esp_register_devices) |