Revision 7d977de7
| b/hw/dma.c | ||
|---|---|---|
| 78 | 78 |
|
| 79 | 79 |
}; |
| 80 | 80 |
|
| 81 |
static void write_page (CPUState *env, uint32_t nport, uint32_t data)
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|
| 81 |
static void write_page (void *opaque, uint32_t nport, uint32_t data)
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| 82 | 82 |
{
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| 83 | 83 |
int ichan; |
| 84 | 84 |
int ncont; |
| ... | ... | |
| 113 | 113 |
return ff; |
| 114 | 114 |
} |
| 115 | 115 |
|
| 116 |
static uint32_t read_chan (CPUState *env, uint32_t nport)
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| 116 |
static uint32_t read_chan (void *opaque, uint32_t nport)
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| 117 | 117 |
{
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| 118 | 118 |
int ff; |
| 119 | 119 |
int ncont, ichan, nreg; |
| ... | ... | |
| 135 | 135 |
return (val >> (ncont + (ff << 3))) & 0xff; |
| 136 | 136 |
} |
| 137 | 137 |
|
| 138 |
static void write_chan (CPUState *env, uint32_t nport, uint32_t data)
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|
| 138 |
static void write_chan (void *opaque, uint32_t nport, uint32_t data)
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| 139 | 139 |
{
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| 140 | 140 |
int ncont, ichan, nreg; |
| 141 | 141 |
struct dma_regs *r; |
| ... | ... | |
| 153 | 153 |
} |
| 154 | 154 |
} |
| 155 | 155 |
|
| 156 |
static void write_cont (CPUState *env, uint32_t nport, uint32_t data)
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| 156 |
static void write_cont (void *opaque, uint32_t nport, uint32_t data)
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| 157 | 157 |
{
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| 158 | 158 |
int iport, ichan, ncont; |
| 159 | 159 |
struct dma_cont *d; |
| ... | ... | |
| 345 | 345 |
int page_port_list[] = { 0x1, 0x2, 0x3, 0x7 };
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| 346 | 346 |
|
| 347 | 347 |
for (i = 0; i < 8; i++) {
|
| 348 |
register_ioport_write (i, 1, write_chan, 1);
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| 348 |
register_ioport_write (i, 1, 1, write_chan, NULL);
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| 349 | 349 |
|
| 350 |
register_ioport_write (0xc0 + (i << 1), 1, write_chan, 1);
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| 350 |
register_ioport_write (0xc0 + (i << 1), 1, 1, write_chan, NULL);
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| 351 | 351 |
|
| 352 |
register_ioport_read (i, 1, read_chan, 1);
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| 353 |
register_ioport_read (0xc0 + (i << 1), 1, read_chan, 1);
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|
| 352 |
register_ioport_read (i, 1, 1, read_chan, NULL);
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| 353 |
register_ioport_read (0xc0 + (i << 1), 1, 1, read_chan, NULL);
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| 354 | 354 |
} |
| 355 | 355 |
|
| 356 | 356 |
for (i = 0; i < LENOFA (page_port_list); i++) {
|
| 357 |
register_ioport_write (page_port_list[i] + 0x80, 1, write_page, 1);
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| 358 |
register_ioport_write (page_port_list[i] + 0x88, 1, write_page, 1);
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| 357 |
register_ioport_write (page_port_list[i] + 0x80, 1, 1, write_page, NULL);
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| 358 |
register_ioport_write (page_port_list[i] + 0x88, 1, 1, write_page, NULL);
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| 359 | 359 |
} |
| 360 | 360 |
|
| 361 | 361 |
for (i = 0; i < 8; i++) {
|
| 362 |
register_ioport_write (i + 8, 1, write_cont, 1);
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| 363 |
register_ioport_write (0xd0 + (i << 1), 1, write_cont, 1);
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| 362 |
register_ioport_write (i + 8, 1, 1, write_cont, NULL);
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| 363 |
register_ioport_write (0xd0 + (i << 1), 1, 1, write_cont, NULL);
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| 364 | 364 |
} |
| 365 | 365 |
|
| 366 | 366 |
write_cont (NULL, 0x0d, 0); |
| b/hw/sb16.c | ||
|---|---|---|
| 50 | 50 |
#endif |
| 51 | 51 |
|
| 52 | 52 |
#define IO_READ_PROTO(name) \ |
| 53 |
uint32_t name (struct CPUState *env, uint32_t nport)
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| 53 |
uint32_t name (void *opaque, uint32_t nport)
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| 54 | 54 |
#define IO_WRITE_PROTO(name) \ |
| 55 |
void name (struct CPUState *env, uint32_t nport, uint32_t val)
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| 55 |
void name (void *opaque, uint32_t nport, uint32_t val)
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| 56 | 56 |
|
| 57 | 57 |
static struct {
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| 58 | 58 |
int ver_lo; |
| ... | ... | |
| 550 | 550 |
|
| 551 | 551 |
static IO_WRITE_PROTO(mixer_write_indexw) |
| 552 | 552 |
{
|
| 553 |
mixer_write_indexb (env, nport, val & 0xff);
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| 554 |
mixer_write_datab (env, nport, (val >> 8) & 0xff);
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| 553 |
mixer_write_indexb (opaque, nport, val & 0xff);
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| 554 |
mixer_write_datab (opaque, nport, (val >> 8) & 0xff);
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| 555 | 555 |
} |
| 556 | 556 |
|
| 557 | 557 |
static IO_READ_PROTO(mixer_read) |
| ... | ... | |
| 718 | 718 |
} |
| 719 | 719 |
|
| 720 | 720 |
for (i = 0; i < LENOFA (dsp_write_ports); i++) {
|
| 721 |
register_ioport_write (sb.port + dsp_write_ports[i], 1, dsp_write, 1);
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| 721 |
register_ioport_write (sb.port + dsp_write_ports[i], 1, 1, dsp_write, NULL);
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| 722 | 722 |
} |
| 723 | 723 |
|
| 724 | 724 |
for (i = 0; i < LENOFA (dsp_read_ports); i++) {
|
| 725 |
register_ioport_read (sb.port + dsp_read_ports[i], 1, dsp_read, 1);
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| 725 |
register_ioport_read (sb.port + dsp_read_ports[i], 1, 1, dsp_read, NULL);
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| 726 | 726 |
} |
| 727 | 727 |
|
| 728 |
register_ioport_write (sb.port + 0x4, 1, mixer_write_indexb, 1);
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| 729 |
register_ioport_write (sb.port + 0x4, 1, mixer_write_indexw, 2);
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| 730 |
register_ioport_read (sb.port + 0x5, 1, mixer_read, 1);
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| 731 |
register_ioport_write (sb.port + 0x5, 1, mixer_write_datab, 1);
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| 728 |
register_ioport_write (sb.port + 0x4, 1, 1, mixer_write_indexb, NULL);
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| 729 |
register_ioport_write (sb.port + 0x4, 1, 2, mixer_write_indexw, NULL);
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| 730 |
register_ioport_read (sb.port + 0x5, 1, 1, mixer_read, NULL);
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| 731 |
register_ioport_write (sb.port + 0x5, 1, 1, mixer_write_datab, NULL);
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| 732 | 732 |
|
| 733 | 733 |
DMA_register_channel (sb.hdma, SB_read_DMA, NULL); |
| 734 | 734 |
DMA_register_channel (sb.dma, SB_read_DMA, NULL); |
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