root / target-sh4 / translate.c @ 7da76bce
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1 | fdf9b3e8 | bellard | /*
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2 | fdf9b3e8 | bellard | * SH4 translation
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3 | 5fafdf24 | ths | *
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4 | fdf9b3e8 | bellard | * Copyright (c) 2005 Samuel Tardieu
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5 | fdf9b3e8 | bellard | *
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6 | fdf9b3e8 | bellard | * This library is free software; you can redistribute it and/or
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7 | fdf9b3e8 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | fdf9b3e8 | bellard | * License as published by the Free Software Foundation; either
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9 | fdf9b3e8 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | fdf9b3e8 | bellard | *
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11 | fdf9b3e8 | bellard | * This library is distributed in the hope that it will be useful,
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12 | fdf9b3e8 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | fdf9b3e8 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | fdf9b3e8 | bellard | * Lesser General Public License for more details.
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15 | fdf9b3e8 | bellard | *
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16 | fdf9b3e8 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | fdf9b3e8 | bellard | * License along with this library; if not, write to the Free Software
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18 | fdf9b3e8 | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | fdf9b3e8 | bellard | */
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20 | fdf9b3e8 | bellard | #include <stdarg.h> |
21 | fdf9b3e8 | bellard | #include <stdlib.h> |
22 | fdf9b3e8 | bellard | #include <stdio.h> |
23 | fdf9b3e8 | bellard | #include <string.h> |
24 | fdf9b3e8 | bellard | #include <inttypes.h> |
25 | fdf9b3e8 | bellard | #include <assert.h> |
26 | fdf9b3e8 | bellard | |
27 | fdf9b3e8 | bellard | #define DEBUG_DISAS
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28 | fdf9b3e8 | bellard | #define SH4_DEBUG_DISAS
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29 | fdf9b3e8 | bellard | //#define SH4_SINGLE_STEP
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30 | fdf9b3e8 | bellard | |
31 | fdf9b3e8 | bellard | #include "cpu.h" |
32 | fdf9b3e8 | bellard | #include "exec-all.h" |
33 | fdf9b3e8 | bellard | #include "disas.h" |
34 | 57fec1fe | bellard | #include "tcg-op.h" |
35 | ca10f867 | aurel32 | #include "qemu-common.h" |
36 | fdf9b3e8 | bellard | |
37 | fdf9b3e8 | bellard | typedef struct DisasContext { |
38 | fdf9b3e8 | bellard | struct TranslationBlock *tb;
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39 | fdf9b3e8 | bellard | target_ulong pc; |
40 | fdf9b3e8 | bellard | uint32_t sr; |
41 | eda9b09b | bellard | uint32_t fpscr; |
42 | fdf9b3e8 | bellard | uint16_t opcode; |
43 | fdf9b3e8 | bellard | uint32_t flags; |
44 | 823029f9 | ths | int bstate;
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45 | fdf9b3e8 | bellard | int memidx;
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46 | fdf9b3e8 | bellard | uint32_t delayed_pc; |
47 | fdf9b3e8 | bellard | int singlestep_enabled;
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48 | fdf9b3e8 | bellard | } DisasContext; |
49 | fdf9b3e8 | bellard | |
50 | 823029f9 | ths | enum {
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51 | 823029f9 | ths | BS_NONE = 0, /* We go out of the TB without reaching a branch or an |
52 | 823029f9 | ths | * exception condition
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53 | 823029f9 | ths | */
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54 | 823029f9 | ths | BS_STOP = 1, /* We want to stop translation for any reason */ |
55 | 823029f9 | ths | BS_BRANCH = 2, /* We reached a branch condition */ |
56 | 823029f9 | ths | BS_EXCP = 3, /* We reached an exception condition */ |
57 | 823029f9 | ths | }; |
58 | 823029f9 | ths | |
59 | 2e70f6ef | pbrook | static TCGv cpu_env;
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60 | 2e70f6ef | pbrook | |
61 | 2e70f6ef | pbrook | #include "gen-icount.h" |
62 | 2e70f6ef | pbrook | |
63 | a5f1b965 | blueswir1 | static void sh4_translate_init(void) |
64 | 2e70f6ef | pbrook | { |
65 | 2e70f6ef | pbrook | static int done_init = 0; |
66 | 2e70f6ef | pbrook | if (done_init)
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67 | 2e70f6ef | pbrook | return;
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68 | 2e70f6ef | pbrook | cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
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69 | 2e70f6ef | pbrook | done_init = 1;
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70 | 2e70f6ef | pbrook | } |
71 | 2e70f6ef | pbrook | |
72 | fdf9b3e8 | bellard | #ifdef CONFIG_USER_ONLY
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73 | fdf9b3e8 | bellard | |
74 | eda9b09b | bellard | #define GEN_OP_LD(width, reg) \
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75 | eda9b09b | bellard | void gen_op_ld##width##_T0_##reg (DisasContext *ctx) { \ |
76 | eda9b09b | bellard | gen_op_ld##width##_T0_##reg##_raw(); \ |
77 | fdf9b3e8 | bellard | } |
78 | eda9b09b | bellard | #define GEN_OP_ST(width, reg) \
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79 | eda9b09b | bellard | void gen_op_st##width##_##reg##_T1 (DisasContext *ctx) { \ |
80 | eda9b09b | bellard | gen_op_st##width##_##reg##_T1_raw(); \ |
81 | fdf9b3e8 | bellard | } |
82 | fdf9b3e8 | bellard | |
83 | fdf9b3e8 | bellard | #else
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84 | fdf9b3e8 | bellard | |
85 | eda9b09b | bellard | #define GEN_OP_LD(width, reg) \
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86 | eda9b09b | bellard | void gen_op_ld##width##_T0_##reg (DisasContext *ctx) { \ |
87 | eda9b09b | bellard | if (ctx->memidx) gen_op_ld##width##_T0_##reg##_kernel(); \ |
88 | eda9b09b | bellard | else gen_op_ld##width##_T0_##reg##_user();\ |
89 | fdf9b3e8 | bellard | } |
90 | eda9b09b | bellard | #define GEN_OP_ST(width, reg) \
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91 | eda9b09b | bellard | void gen_op_st##width##_##reg##_T1 (DisasContext *ctx) { \ |
92 | eda9b09b | bellard | if (ctx->memidx) gen_op_st##width##_##reg##_T1_kernel(); \ |
93 | eda9b09b | bellard | else gen_op_st##width##_##reg##_T1_user();\ |
94 | fdf9b3e8 | bellard | } |
95 | fdf9b3e8 | bellard | |
96 | fdf9b3e8 | bellard | #endif
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97 | fdf9b3e8 | bellard | |
98 | eda9b09b | bellard | GEN_OP_LD(ub, T0) |
99 | eda9b09b | bellard | GEN_OP_LD(b, T0) |
100 | eda9b09b | bellard | GEN_OP_ST(b, T0) |
101 | eda9b09b | bellard | GEN_OP_LD(uw, T0) |
102 | eda9b09b | bellard | GEN_OP_LD(w, T0) |
103 | eda9b09b | bellard | GEN_OP_ST(w, T0) |
104 | eda9b09b | bellard | GEN_OP_LD(l, T0) |
105 | eda9b09b | bellard | GEN_OP_ST(l, T0) |
106 | eda9b09b | bellard | GEN_OP_LD(fl, FT0) |
107 | eda9b09b | bellard | GEN_OP_ST(fl, FT0) |
108 | eda9b09b | bellard | GEN_OP_LD(fq, DT0) |
109 | eda9b09b | bellard | GEN_OP_ST(fq, DT0) |
110 | fdf9b3e8 | bellard | |
111 | fdf9b3e8 | bellard | void cpu_dump_state(CPUState * env, FILE * f,
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112 | fdf9b3e8 | bellard | int (*cpu_fprintf) (FILE * f, const char *fmt, ...), |
113 | fdf9b3e8 | bellard | int flags)
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114 | fdf9b3e8 | bellard | { |
115 | fdf9b3e8 | bellard | int i;
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116 | eda9b09b | bellard | cpu_fprintf(f, "pc=0x%08x sr=0x%08x pr=0x%08x fpscr=0x%08x\n",
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117 | eda9b09b | bellard | env->pc, env->sr, env->pr, env->fpscr); |
118 | 274a9e70 | aurel32 | cpu_fprintf(f, "spc=0x%08x ssr=0x%08x gbr=0x%08x vbr=0x%08x\n",
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119 | 274a9e70 | aurel32 | env->spc, env->ssr, env->gbr, env->vbr); |
120 | 274a9e70 | aurel32 | cpu_fprintf(f, "sgr=0x%08x dbr=0x%08x delayed_pc=0x%08x fpul=0x%08x\n",
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121 | 274a9e70 | aurel32 | env->sgr, env->dbr, env->delayed_pc, env->fpul); |
122 | fdf9b3e8 | bellard | for (i = 0; i < 24; i += 4) { |
123 | fdf9b3e8 | bellard | cpu_fprintf(f, "r%d=0x%08x r%d=0x%08x r%d=0x%08x r%d=0x%08x\n",
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124 | fdf9b3e8 | bellard | i, env->gregs[i], i + 1, env->gregs[i + 1], |
125 | fdf9b3e8 | bellard | i + 2, env->gregs[i + 2], i + 3, env->gregs[i + 3]); |
126 | fdf9b3e8 | bellard | } |
127 | fdf9b3e8 | bellard | if (env->flags & DELAY_SLOT) {
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128 | fdf9b3e8 | bellard | cpu_fprintf(f, "in delay slot (delayed_pc=0x%08x)\n",
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129 | fdf9b3e8 | bellard | env->delayed_pc); |
130 | fdf9b3e8 | bellard | } else if (env->flags & DELAY_SLOT_CONDITIONAL) { |
131 | fdf9b3e8 | bellard | cpu_fprintf(f, "in conditional delay slot (delayed_pc=0x%08x)\n",
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132 | fdf9b3e8 | bellard | env->delayed_pc); |
133 | fdf9b3e8 | bellard | } |
134 | fdf9b3e8 | bellard | } |
135 | fdf9b3e8 | bellard | |
136 | fdf9b3e8 | bellard | void cpu_sh4_reset(CPUSH4State * env)
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137 | fdf9b3e8 | bellard | { |
138 | 9c2a9ea1 | pbrook | #if defined(CONFIG_USER_ONLY)
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139 | 4c909d14 | ths | env->sr = SR_FD; /* FD - kernel does lazy fpu context switch */
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140 | 9c2a9ea1 | pbrook | #else
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141 | fdf9b3e8 | bellard | env->sr = 0x700000F0; /* MD, RB, BL, I3-I0 */ |
142 | 9c2a9ea1 | pbrook | #endif
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143 | fdf9b3e8 | bellard | env->vbr = 0;
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144 | fdf9b3e8 | bellard | env->pc = 0xA0000000;
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145 | ea6cf6be | ths | #if defined(CONFIG_USER_ONLY)
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146 | ea6cf6be | ths | env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */
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147 | b0b3de89 | bellard | set_float_rounding_mode(float_round_nearest_even, &env->fp_status); /* ?! */
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148 | ea6cf6be | ths | #else
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149 | ea6cf6be | ths | env->fpscr = 0x00040001; /* CPU reset value according to SH4 manual */ |
150 | b0b3de89 | bellard | set_float_rounding_mode(float_round_to_zero, &env->fp_status); |
151 | ea6cf6be | ths | #endif
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152 | fdf9b3e8 | bellard | env->mmucr = 0;
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153 | fdf9b3e8 | bellard | } |
154 | fdf9b3e8 | bellard | |
155 | aaed909a | bellard | CPUSH4State *cpu_sh4_init(const char *cpu_model) |
156 | fdf9b3e8 | bellard | { |
157 | fdf9b3e8 | bellard | CPUSH4State *env; |
158 | fdf9b3e8 | bellard | |
159 | fdf9b3e8 | bellard | env = qemu_mallocz(sizeof(CPUSH4State));
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160 | fdf9b3e8 | bellard | if (!env)
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161 | fdf9b3e8 | bellard | return NULL; |
162 | fdf9b3e8 | bellard | cpu_exec_init(env); |
163 | 2e70f6ef | pbrook | sh4_translate_init(); |
164 | fdf9b3e8 | bellard | cpu_sh4_reset(env); |
165 | fdf9b3e8 | bellard | tlb_flush(env, 1);
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166 | fdf9b3e8 | bellard | return env;
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167 | fdf9b3e8 | bellard | } |
168 | fdf9b3e8 | bellard | |
169 | fdf9b3e8 | bellard | static void gen_goto_tb(DisasContext * ctx, int n, target_ulong dest) |
170 | fdf9b3e8 | bellard | { |
171 | fdf9b3e8 | bellard | TranslationBlock *tb; |
172 | fdf9b3e8 | bellard | tb = ctx->tb; |
173 | fdf9b3e8 | bellard | |
174 | fdf9b3e8 | bellard | if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
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175 | fdf9b3e8 | bellard | !ctx->singlestep_enabled) { |
176 | fdf9b3e8 | bellard | /* Use a direct jump if in same page and singlestep not enabled */
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177 | 57fec1fe | bellard | tcg_gen_goto_tb(n); |
178 | 57fec1fe | bellard | gen_op_movl_imm_PC(dest); |
179 | 57fec1fe | bellard | tcg_gen_exit_tb((long) tb + n);
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180 | fdf9b3e8 | bellard | } else {
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181 | 57fec1fe | bellard | gen_op_movl_imm_PC(dest); |
182 | 57fec1fe | bellard | if (ctx->singlestep_enabled)
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183 | 57fec1fe | bellard | gen_op_debug(); |
184 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
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185 | fdf9b3e8 | bellard | } |
186 | fdf9b3e8 | bellard | } |
187 | fdf9b3e8 | bellard | |
188 | fdf9b3e8 | bellard | static void gen_jump(DisasContext * ctx) |
189 | fdf9b3e8 | bellard | { |
190 | fdf9b3e8 | bellard | if (ctx->delayed_pc == (uint32_t) - 1) { |
191 | fdf9b3e8 | bellard | /* Target is not statically known, it comes necessarily from a
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192 | fdf9b3e8 | bellard | delayed jump as immediate jump are conditinal jumps */
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193 | fdf9b3e8 | bellard | gen_op_movl_delayed_pc_PC(); |
194 | fdf9b3e8 | bellard | if (ctx->singlestep_enabled)
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195 | fdf9b3e8 | bellard | gen_op_debug(); |
196 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
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197 | fdf9b3e8 | bellard | } else {
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198 | fdf9b3e8 | bellard | gen_goto_tb(ctx, 0, ctx->delayed_pc);
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199 | fdf9b3e8 | bellard | } |
200 | fdf9b3e8 | bellard | } |
201 | fdf9b3e8 | bellard | |
202 | fdf9b3e8 | bellard | /* Immediate conditional jump (bt or bf) */
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203 | fdf9b3e8 | bellard | static void gen_conditional_jump(DisasContext * ctx, |
204 | fdf9b3e8 | bellard | target_ulong ift, target_ulong ifnott) |
205 | fdf9b3e8 | bellard | { |
206 | fdf9b3e8 | bellard | int l1;
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207 | fdf9b3e8 | bellard | |
208 | fdf9b3e8 | bellard | l1 = gen_new_label(); |
209 | fdf9b3e8 | bellard | gen_op_jT(l1); |
210 | fdf9b3e8 | bellard | gen_goto_tb(ctx, 0, ifnott);
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211 | fdf9b3e8 | bellard | gen_set_label(l1); |
212 | fdf9b3e8 | bellard | gen_goto_tb(ctx, 1, ift);
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213 | fdf9b3e8 | bellard | } |
214 | fdf9b3e8 | bellard | |
215 | fdf9b3e8 | bellard | /* Delayed conditional jump (bt or bf) */
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216 | fdf9b3e8 | bellard | static void gen_delayed_conditional_jump(DisasContext * ctx) |
217 | fdf9b3e8 | bellard | { |
218 | fdf9b3e8 | bellard | int l1;
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219 | fdf9b3e8 | bellard | |
220 | fdf9b3e8 | bellard | l1 = gen_new_label(); |
221 | 9c2a9ea1 | pbrook | gen_op_jdelayed(l1); |
222 | 823029f9 | ths | gen_goto_tb(ctx, 1, ctx->pc + 2); |
223 | fdf9b3e8 | bellard | gen_set_label(l1); |
224 | 9c2a9ea1 | pbrook | gen_jump(ctx); |
225 | fdf9b3e8 | bellard | } |
226 | fdf9b3e8 | bellard | |
227 | fdf9b3e8 | bellard | #define B3_0 (ctx->opcode & 0xf) |
228 | fdf9b3e8 | bellard | #define B6_4 ((ctx->opcode >> 4) & 0x7) |
229 | fdf9b3e8 | bellard | #define B7_4 ((ctx->opcode >> 4) & 0xf) |
230 | fdf9b3e8 | bellard | #define B7_0 (ctx->opcode & 0xff) |
231 | fdf9b3e8 | bellard | #define B7_0s ((int32_t) (int8_t) (ctx->opcode & 0xff)) |
232 | fdf9b3e8 | bellard | #define B11_0s (ctx->opcode & 0x800 ? 0xfffff000 | (ctx->opcode & 0xfff) : \ |
233 | fdf9b3e8 | bellard | (ctx->opcode & 0xfff))
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234 | fdf9b3e8 | bellard | #define B11_8 ((ctx->opcode >> 8) & 0xf) |
235 | fdf9b3e8 | bellard | #define B15_12 ((ctx->opcode >> 12) & 0xf) |
236 | fdf9b3e8 | bellard | |
237 | fdf9b3e8 | bellard | #define REG(x) ((x) < 8 && (ctx->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB) ? \ |
238 | fdf9b3e8 | bellard | (x) + 16 : (x))
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239 | fdf9b3e8 | bellard | |
240 | fdf9b3e8 | bellard | #define ALTREG(x) ((x) < 8 && (ctx->sr & (SR_MD | SR_RB)) != (SR_MD | SR_RB) \ |
241 | fdf9b3e8 | bellard | ? (x) + 16 : (x))
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242 | fdf9b3e8 | bellard | |
243 | eda9b09b | bellard | #define FREG(x) (ctx->fpscr & FPSCR_FR ? (x) ^ 0x10 : (x)) |
244 | f09111e0 | ths | #define XHACK(x) ((((x) & 1 ) << 4) | ((x) & 0xe)) |
245 | eda9b09b | bellard | #define XREG(x) (ctx->fpscr & FPSCR_FR ? XHACK(x) ^ 0x10 : XHACK(x)) |
246 | ea6cf6be | ths | #define DREG(x) FREG(x) /* Assumes lsb of (x) is always 0 */ |
247 | eda9b09b | bellard | |
248 | fdf9b3e8 | bellard | #define CHECK_NOT_DELAY_SLOT \
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249 | fdf9b3e8 | bellard | if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) \
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250 | 823029f9 | ths | {gen_op_raise_slot_illegal_instruction (); ctx->bstate = BS_EXCP; \ |
251 | fdf9b3e8 | bellard | return;}
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252 | fdf9b3e8 | bellard | |
253 | 823029f9 | ths | void _decode_opc(DisasContext * ctx)
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254 | fdf9b3e8 | bellard | { |
255 | fdf9b3e8 | bellard | #if 0
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256 | fdf9b3e8 | bellard | fprintf(stderr, "Translating opcode 0x%04x\n", ctx->opcode);
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257 | fdf9b3e8 | bellard | #endif
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258 | fdf9b3e8 | bellard | switch (ctx->opcode) {
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259 | fdf9b3e8 | bellard | case 0x0019: /* div0u */ |
260 | fdf9b3e8 | bellard | gen_op_div0u(); |
261 | fdf9b3e8 | bellard | return;
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262 | fdf9b3e8 | bellard | case 0x000b: /* rts */ |
263 | fdf9b3e8 | bellard | CHECK_NOT_DELAY_SLOT gen_op_rts(); |
264 | fdf9b3e8 | bellard | ctx->flags |= DELAY_SLOT; |
265 | fdf9b3e8 | bellard | ctx->delayed_pc = (uint32_t) - 1;
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266 | fdf9b3e8 | bellard | return;
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267 | fdf9b3e8 | bellard | case 0x0028: /* clrmac */ |
268 | fdf9b3e8 | bellard | gen_op_clrmac(); |
269 | fdf9b3e8 | bellard | return;
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270 | fdf9b3e8 | bellard | case 0x0048: /* clrs */ |
271 | fdf9b3e8 | bellard | gen_op_clrs(); |
272 | fdf9b3e8 | bellard | return;
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273 | fdf9b3e8 | bellard | case 0x0008: /* clrt */ |
274 | fdf9b3e8 | bellard | gen_op_clrt(); |
275 | fdf9b3e8 | bellard | return;
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276 | fdf9b3e8 | bellard | case 0x0038: /* ldtlb */ |
277 | ea2b542a | aurel32 | #if defined(CONFIG_USER_ONLY)
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278 | fdf9b3e8 | bellard | assert(0); /* XXXXX */ |
279 | ea2b542a | aurel32 | #else
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280 | ea2b542a | aurel32 | gen_op_ldtlb(); |
281 | ea2b542a | aurel32 | #endif
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282 | fdf9b3e8 | bellard | return;
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283 | c5e814b2 | ths | case 0x002b: /* rte */ |
284 | fdf9b3e8 | bellard | CHECK_NOT_DELAY_SLOT gen_op_rte(); |
285 | fdf9b3e8 | bellard | ctx->flags |= DELAY_SLOT; |
286 | fdf9b3e8 | bellard | ctx->delayed_pc = (uint32_t) - 1;
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287 | fdf9b3e8 | bellard | return;
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288 | fdf9b3e8 | bellard | case 0x0058: /* sets */ |
289 | fdf9b3e8 | bellard | gen_op_sets(); |
290 | fdf9b3e8 | bellard | return;
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291 | fdf9b3e8 | bellard | case 0x0018: /* sett */ |
292 | fdf9b3e8 | bellard | gen_op_sett(); |
293 | fdf9b3e8 | bellard | return;
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294 | 24988dc2 | aurel32 | case 0xfbfd: /* frchg */ |
295 | eda9b09b | bellard | gen_op_frchg(); |
296 | 823029f9 | ths | ctx->bstate = BS_STOP; |
297 | fdf9b3e8 | bellard | return;
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298 | 24988dc2 | aurel32 | case 0xf3fd: /* fschg */ |
299 | eda9b09b | bellard | gen_op_fschg(); |
300 | 823029f9 | ths | ctx->bstate = BS_STOP; |
301 | fdf9b3e8 | bellard | return;
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302 | fdf9b3e8 | bellard | case 0x0009: /* nop */ |
303 | fdf9b3e8 | bellard | return;
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304 | fdf9b3e8 | bellard | case 0x001b: /* sleep */ |
305 | 833ed386 | aurel32 | if (ctx->memidx) {
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306 | 833ed386 | aurel32 | gen_op_sleep(); |
307 | 833ed386 | aurel32 | } else {
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308 | 833ed386 | aurel32 | gen_op_raise_illegal_instruction(); |
309 | 833ed386 | aurel32 | ctx->bstate = BS_EXCP; |
310 | 833ed386 | aurel32 | } |
311 | fdf9b3e8 | bellard | return;
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312 | fdf9b3e8 | bellard | } |
313 | fdf9b3e8 | bellard | |
314 | fdf9b3e8 | bellard | switch (ctx->opcode & 0xf000) { |
315 | fdf9b3e8 | bellard | case 0x1000: /* mov.l Rm,@(disp,Rn) */ |
316 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
317 | fdf9b3e8 | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
318 | fdf9b3e8 | bellard | gen_op_addl_imm_T1(B3_0 * 4);
|
319 | fdf9b3e8 | bellard | gen_op_stl_T0_T1(ctx); |
320 | fdf9b3e8 | bellard | return;
|
321 | fdf9b3e8 | bellard | case 0x5000: /* mov.l @(disp,Rm),Rn */ |
322 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
323 | fdf9b3e8 | bellard | gen_op_addl_imm_T0(B3_0 * 4);
|
324 | fdf9b3e8 | bellard | gen_op_ldl_T0_T0(ctx); |
325 | fdf9b3e8 | bellard | gen_op_movl_T0_rN(REG(B11_8)); |
326 | fdf9b3e8 | bellard | return;
|
327 | 24988dc2 | aurel32 | case 0xe000: /* mov #imm,Rn */ |
328 | fdf9b3e8 | bellard | gen_op_movl_imm_rN(B7_0s, REG(B11_8)); |
329 | fdf9b3e8 | bellard | return;
|
330 | fdf9b3e8 | bellard | case 0x9000: /* mov.w @(disp,PC),Rn */ |
331 | fdf9b3e8 | bellard | gen_op_movl_imm_T0(ctx->pc + 4 + B7_0 * 2); |
332 | fdf9b3e8 | bellard | gen_op_ldw_T0_T0(ctx); |
333 | fdf9b3e8 | bellard | gen_op_movl_T0_rN(REG(B11_8)); |
334 | fdf9b3e8 | bellard | return;
|
335 | fdf9b3e8 | bellard | case 0xd000: /* mov.l @(disp,PC),Rn */ |
336 | fdf9b3e8 | bellard | gen_op_movl_imm_T0((ctx->pc + 4 + B7_0 * 4) & ~3); |
337 | fdf9b3e8 | bellard | gen_op_ldl_T0_T0(ctx); |
338 | fdf9b3e8 | bellard | gen_op_movl_T0_rN(REG(B11_8)); |
339 | fdf9b3e8 | bellard | return;
|
340 | 24988dc2 | aurel32 | case 0x7000: /* add #imm,Rn */ |
341 | fdf9b3e8 | bellard | gen_op_add_imm_rN(B7_0s, REG(B11_8)); |
342 | fdf9b3e8 | bellard | return;
|
343 | fdf9b3e8 | bellard | case 0xa000: /* bra disp */ |
344 | fdf9b3e8 | bellard | CHECK_NOT_DELAY_SLOT |
345 | fdf9b3e8 | bellard | gen_op_bra(ctx->delayed_pc = ctx->pc + 4 + B11_0s * 2); |
346 | fdf9b3e8 | bellard | ctx->flags |= DELAY_SLOT; |
347 | fdf9b3e8 | bellard | return;
|
348 | fdf9b3e8 | bellard | case 0xb000: /* bsr disp */ |
349 | fdf9b3e8 | bellard | CHECK_NOT_DELAY_SLOT |
350 | fdf9b3e8 | bellard | gen_op_bsr(ctx->pc + 4, ctx->delayed_pc =
|
351 | fdf9b3e8 | bellard | ctx->pc + 4 + B11_0s * 2); |
352 | fdf9b3e8 | bellard | ctx->flags |= DELAY_SLOT; |
353 | fdf9b3e8 | bellard | return;
|
354 | fdf9b3e8 | bellard | } |
355 | fdf9b3e8 | bellard | |
356 | fdf9b3e8 | bellard | switch (ctx->opcode & 0xf00f) { |
357 | fdf9b3e8 | bellard | case 0x6003: /* mov Rm,Rn */ |
358 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
359 | fdf9b3e8 | bellard | gen_op_movl_T0_rN(REG(B11_8)); |
360 | fdf9b3e8 | bellard | return;
|
361 | fdf9b3e8 | bellard | case 0x2000: /* mov.b Rm,@Rn */ |
362 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
363 | fdf9b3e8 | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
364 | fdf9b3e8 | bellard | gen_op_stb_T0_T1(ctx); |
365 | fdf9b3e8 | bellard | return;
|
366 | fdf9b3e8 | bellard | case 0x2001: /* mov.w Rm,@Rn */ |
367 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
368 | fdf9b3e8 | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
369 | fdf9b3e8 | bellard | gen_op_stw_T0_T1(ctx); |
370 | fdf9b3e8 | bellard | return;
|
371 | fdf9b3e8 | bellard | case 0x2002: /* mov.l Rm,@Rn */ |
372 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
373 | fdf9b3e8 | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
374 | fdf9b3e8 | bellard | gen_op_stl_T0_T1(ctx); |
375 | fdf9b3e8 | bellard | return;
|
376 | fdf9b3e8 | bellard | case 0x6000: /* mov.b @Rm,Rn */ |
377 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
378 | fdf9b3e8 | bellard | gen_op_ldb_T0_T0(ctx); |
379 | fdf9b3e8 | bellard | gen_op_movl_T0_rN(REG(B11_8)); |
380 | fdf9b3e8 | bellard | return;
|
381 | fdf9b3e8 | bellard | case 0x6001: /* mov.w @Rm,Rn */ |
382 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
383 | fdf9b3e8 | bellard | gen_op_ldw_T0_T0(ctx); |
384 | fdf9b3e8 | bellard | gen_op_movl_T0_rN(REG(B11_8)); |
385 | fdf9b3e8 | bellard | return;
|
386 | fdf9b3e8 | bellard | case 0x6002: /* mov.l @Rm,Rn */ |
387 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
388 | fdf9b3e8 | bellard | gen_op_ldl_T0_T0(ctx); |
389 | fdf9b3e8 | bellard | gen_op_movl_T0_rN(REG(B11_8)); |
390 | fdf9b3e8 | bellard | return;
|
391 | fdf9b3e8 | bellard | case 0x2004: /* mov.b Rm,@-Rn */ |
392 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
393 | 7da76bce | aurel32 | gen_op_dec1_rN(REG(B11_8)); /* modify register status */
|
394 | fdf9b3e8 | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
395 | 7da76bce | aurel32 | gen_op_inc1_rN(REG(B11_8)); /* recover register status */
|
396 | 7da76bce | aurel32 | gen_op_stb_T0_T1(ctx); /* might cause re-execution */
|
397 | 7da76bce | aurel32 | gen_op_dec1_rN(REG(B11_8)); /* modify register status */
|
398 | fdf9b3e8 | bellard | return;
|
399 | fdf9b3e8 | bellard | case 0x2005: /* mov.w Rm,@-Rn */ |
400 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
401 | 24988dc2 | aurel32 | gen_op_dec2_rN(REG(B11_8)); |
402 | fdf9b3e8 | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
403 | 7da76bce | aurel32 | gen_op_inc2_rN(REG(B11_8)); |
404 | fdf9b3e8 | bellard | gen_op_stw_T0_T1(ctx); |
405 | 7da76bce | aurel32 | gen_op_dec2_rN(REG(B11_8)); |
406 | fdf9b3e8 | bellard | return;
|
407 | fdf9b3e8 | bellard | case 0x2006: /* mov.l Rm,@-Rn */ |
408 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
409 | 24988dc2 | aurel32 | gen_op_dec4_rN(REG(B11_8)); |
410 | fdf9b3e8 | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
411 | 7da76bce | aurel32 | gen_op_inc4_rN(REG(B11_8)); |
412 | fdf9b3e8 | bellard | gen_op_stl_T0_T1(ctx); |
413 | 7da76bce | aurel32 | gen_op_dec4_rN(REG(B11_8)); |
414 | fdf9b3e8 | bellard | return;
|
415 | eda9b09b | bellard | case 0x6004: /* mov.b @Rm+,Rn */ |
416 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
417 | fdf9b3e8 | bellard | gen_op_ldb_T0_T0(ctx); |
418 | fdf9b3e8 | bellard | gen_op_movl_T0_rN(REG(B11_8)); |
419 | 24988dc2 | aurel32 | if ( B11_8 != B7_4 )
|
420 | 24988dc2 | aurel32 | gen_op_inc1_rN(REG(B7_4)); |
421 | fdf9b3e8 | bellard | return;
|
422 | fdf9b3e8 | bellard | case 0x6005: /* mov.w @Rm+,Rn */ |
423 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
424 | fdf9b3e8 | bellard | gen_op_ldw_T0_T0(ctx); |
425 | fdf9b3e8 | bellard | gen_op_movl_T0_rN(REG(B11_8)); |
426 | 24988dc2 | aurel32 | if ( B11_8 != B7_4 )
|
427 | 24988dc2 | aurel32 | gen_op_inc2_rN(REG(B7_4)); |
428 | fdf9b3e8 | bellard | return;
|
429 | fdf9b3e8 | bellard | case 0x6006: /* mov.l @Rm+,Rn */ |
430 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
431 | fdf9b3e8 | bellard | gen_op_ldl_T0_T0(ctx); |
432 | fdf9b3e8 | bellard | gen_op_movl_T0_rN(REG(B11_8)); |
433 | 24988dc2 | aurel32 | if ( B11_8 != B7_4 )
|
434 | 24988dc2 | aurel32 | gen_op_inc4_rN(REG(B7_4)); |
435 | fdf9b3e8 | bellard | return;
|
436 | fdf9b3e8 | bellard | case 0x0004: /* mov.b Rm,@(R0,Rn) */ |
437 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
438 | fdf9b3e8 | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
439 | fdf9b3e8 | bellard | gen_op_add_rN_T1(REG(0));
|
440 | fdf9b3e8 | bellard | gen_op_stb_T0_T1(ctx); |
441 | fdf9b3e8 | bellard | return;
|
442 | fdf9b3e8 | bellard | case 0x0005: /* mov.w Rm,@(R0,Rn) */ |
443 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
444 | fdf9b3e8 | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
445 | fdf9b3e8 | bellard | gen_op_add_rN_T1(REG(0));
|
446 | fdf9b3e8 | bellard | gen_op_stw_T0_T1(ctx); |
447 | fdf9b3e8 | bellard | return;
|
448 | fdf9b3e8 | bellard | case 0x0006: /* mov.l Rm,@(R0,Rn) */ |
449 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
450 | fdf9b3e8 | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
451 | fdf9b3e8 | bellard | gen_op_add_rN_T1(REG(0));
|
452 | fdf9b3e8 | bellard | gen_op_stl_T0_T1(ctx); |
453 | fdf9b3e8 | bellard | return;
|
454 | fdf9b3e8 | bellard | case 0x000c: /* mov.b @(R0,Rm),Rn */ |
455 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
456 | fdf9b3e8 | bellard | gen_op_add_rN_T0(REG(0));
|
457 | fdf9b3e8 | bellard | gen_op_ldb_T0_T0(ctx); |
458 | fdf9b3e8 | bellard | gen_op_movl_T0_rN(REG(B11_8)); |
459 | fdf9b3e8 | bellard | return;
|
460 | fdf9b3e8 | bellard | case 0x000d: /* mov.w @(R0,Rm),Rn */ |
461 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
462 | fdf9b3e8 | bellard | gen_op_add_rN_T0(REG(0));
|
463 | fdf9b3e8 | bellard | gen_op_ldw_T0_T0(ctx); |
464 | fdf9b3e8 | bellard | gen_op_movl_T0_rN(REG(B11_8)); |
465 | fdf9b3e8 | bellard | return;
|
466 | fdf9b3e8 | bellard | case 0x000e: /* mov.l @(R0,Rm),Rn */ |
467 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
468 | fdf9b3e8 | bellard | gen_op_add_rN_T0(REG(0));
|
469 | fdf9b3e8 | bellard | gen_op_ldl_T0_T0(ctx); |
470 | fdf9b3e8 | bellard | gen_op_movl_T0_rN(REG(B11_8)); |
471 | fdf9b3e8 | bellard | return;
|
472 | fdf9b3e8 | bellard | case 0x6008: /* swap.b Rm,Rn */ |
473 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
474 | fdf9b3e8 | bellard | gen_op_swapb_T0(); |
475 | fdf9b3e8 | bellard | gen_op_movl_T0_rN(REG(B11_8)); |
476 | fdf9b3e8 | bellard | return;
|
477 | fdf9b3e8 | bellard | case 0x6009: /* swap.w Rm,Rn */ |
478 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
479 | fdf9b3e8 | bellard | gen_op_swapw_T0(); |
480 | fdf9b3e8 | bellard | gen_op_movl_T0_rN(REG(B11_8)); |
481 | fdf9b3e8 | bellard | return;
|
482 | fdf9b3e8 | bellard | case 0x200d: /* xtrct Rm,Rn */ |
483 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
484 | fdf9b3e8 | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
485 | fdf9b3e8 | bellard | gen_op_xtrct_T0_T1(); |
486 | fdf9b3e8 | bellard | gen_op_movl_T1_rN(REG(B11_8)); |
487 | fdf9b3e8 | bellard | return;
|
488 | fdf9b3e8 | bellard | case 0x300c: /* add Rm,Rn */ |
489 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
490 | fdf9b3e8 | bellard | gen_op_add_T0_rN(REG(B11_8)); |
491 | fdf9b3e8 | bellard | return;
|
492 | fdf9b3e8 | bellard | case 0x300e: /* addc Rm,Rn */ |
493 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
494 | fdf9b3e8 | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
495 | fdf9b3e8 | bellard | gen_op_addc_T0_T1(); |
496 | fdf9b3e8 | bellard | gen_op_movl_T1_rN(REG(B11_8)); |
497 | fdf9b3e8 | bellard | return;
|
498 | fdf9b3e8 | bellard | case 0x300f: /* addv Rm,Rn */ |
499 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
500 | fdf9b3e8 | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
501 | fdf9b3e8 | bellard | gen_op_addv_T0_T1(); |
502 | fdf9b3e8 | bellard | gen_op_movl_T1_rN(REG(B11_8)); |
503 | fdf9b3e8 | bellard | return;
|
504 | fdf9b3e8 | bellard | case 0x2009: /* and Rm,Rn */ |
505 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
506 | fdf9b3e8 | bellard | gen_op_and_T0_rN(REG(B11_8)); |
507 | fdf9b3e8 | bellard | return;
|
508 | fdf9b3e8 | bellard | case 0x3000: /* cmp/eq Rm,Rn */ |
509 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
510 | fdf9b3e8 | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
511 | fdf9b3e8 | bellard | gen_op_cmp_eq_T0_T1(); |
512 | fdf9b3e8 | bellard | return;
|
513 | fdf9b3e8 | bellard | case 0x3003: /* cmp/ge Rm,Rn */ |
514 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
515 | fdf9b3e8 | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
516 | fdf9b3e8 | bellard | gen_op_cmp_ge_T0_T1(); |
517 | fdf9b3e8 | bellard | return;
|
518 | fdf9b3e8 | bellard | case 0x3007: /* cmp/gt Rm,Rn */ |
519 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
520 | fdf9b3e8 | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
521 | fdf9b3e8 | bellard | gen_op_cmp_gt_T0_T1(); |
522 | fdf9b3e8 | bellard | return;
|
523 | fdf9b3e8 | bellard | case 0x3006: /* cmp/hi Rm,Rn */ |
524 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
525 | fdf9b3e8 | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
526 | fdf9b3e8 | bellard | gen_op_cmp_hi_T0_T1(); |
527 | fdf9b3e8 | bellard | return;
|
528 | fdf9b3e8 | bellard | case 0x3002: /* cmp/hs Rm,Rn */ |
529 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
530 | fdf9b3e8 | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
531 | fdf9b3e8 | bellard | gen_op_cmp_hs_T0_T1(); |
532 | fdf9b3e8 | bellard | return;
|
533 | fdf9b3e8 | bellard | case 0x200c: /* cmp/str Rm,Rn */ |
534 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
535 | fdf9b3e8 | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
536 | fdf9b3e8 | bellard | gen_op_cmp_str_T0_T1(); |
537 | fdf9b3e8 | bellard | return;
|
538 | fdf9b3e8 | bellard | case 0x2007: /* div0s Rm,Rn */ |
539 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
540 | fdf9b3e8 | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
541 | fdf9b3e8 | bellard | gen_op_div0s_T0_T1(); |
542 | fdf9b3e8 | bellard | return;
|
543 | fdf9b3e8 | bellard | case 0x3004: /* div1 Rm,Rn */ |
544 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
545 | fdf9b3e8 | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
546 | fdf9b3e8 | bellard | gen_op_div1_T0_T1(); |
547 | fdf9b3e8 | bellard | gen_op_movl_T1_rN(REG(B11_8)); |
548 | fdf9b3e8 | bellard | return;
|
549 | fdf9b3e8 | bellard | case 0x300d: /* dmuls.l Rm,Rn */ |
550 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
551 | fdf9b3e8 | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
552 | fdf9b3e8 | bellard | gen_op_dmulsl_T0_T1(); |
553 | fdf9b3e8 | bellard | return;
|
554 | fdf9b3e8 | bellard | case 0x3005: /* dmulu.l Rm,Rn */ |
555 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
556 | fdf9b3e8 | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
557 | fdf9b3e8 | bellard | gen_op_dmulul_T0_T1(); |
558 | fdf9b3e8 | bellard | return;
|
559 | fdf9b3e8 | bellard | case 0x600e: /* exts.b Rm,Rn */ |
560 | fdf9b3e8 | bellard | gen_op_movb_rN_T0(REG(B7_4)); |
561 | fdf9b3e8 | bellard | gen_op_movl_T0_rN(REG(B11_8)); |
562 | fdf9b3e8 | bellard | return;
|
563 | fdf9b3e8 | bellard | case 0x600f: /* exts.w Rm,Rn */ |
564 | fdf9b3e8 | bellard | gen_op_movw_rN_T0(REG(B7_4)); |
565 | fdf9b3e8 | bellard | gen_op_movl_T0_rN(REG(B11_8)); |
566 | fdf9b3e8 | bellard | return;
|
567 | fdf9b3e8 | bellard | case 0x600c: /* extu.b Rm,Rn */ |
568 | fdf9b3e8 | bellard | gen_op_movub_rN_T0(REG(B7_4)); |
569 | fdf9b3e8 | bellard | gen_op_movl_T0_rN(REG(B11_8)); |
570 | fdf9b3e8 | bellard | return;
|
571 | fdf9b3e8 | bellard | case 0x600d: /* extu.w Rm,Rn */ |
572 | fdf9b3e8 | bellard | gen_op_movuw_rN_T0(REG(B7_4)); |
573 | fdf9b3e8 | bellard | gen_op_movl_T0_rN(REG(B11_8)); |
574 | fdf9b3e8 | bellard | return;
|
575 | 24988dc2 | aurel32 | case 0x000f: /* mac.l @Rm+,@Rn+ */ |
576 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B11_8)); |
577 | fdf9b3e8 | bellard | gen_op_ldl_T0_T0(ctx); |
578 | fdf9b3e8 | bellard | gen_op_movl_T0_T1(); |
579 | 24988dc2 | aurel32 | gen_op_movl_rN_T0(REG(B7_4)); |
580 | fdf9b3e8 | bellard | gen_op_ldl_T0_T0(ctx); |
581 | fdf9b3e8 | bellard | gen_op_macl_T0_T1(); |
582 | 7da76bce | aurel32 | gen_op_inc4_rN(REG(B11_8)); |
583 | fdf9b3e8 | bellard | gen_op_inc4_rN(REG(B7_4)); |
584 | fdf9b3e8 | bellard | return;
|
585 | fdf9b3e8 | bellard | case 0x400f: /* mac.w @Rm+,@Rn+ */ |
586 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B11_8)); |
587 | fdf9b3e8 | bellard | gen_op_ldl_T0_T0(ctx); |
588 | fdf9b3e8 | bellard | gen_op_movl_T0_T1(); |
589 | 24988dc2 | aurel32 | gen_op_movl_rN_T0(REG(B7_4)); |
590 | fdf9b3e8 | bellard | gen_op_ldl_T0_T0(ctx); |
591 | fdf9b3e8 | bellard | gen_op_macw_T0_T1(); |
592 | 7da76bce | aurel32 | gen_op_inc2_rN(REG(B11_8)); |
593 | fdf9b3e8 | bellard | gen_op_inc2_rN(REG(B7_4)); |
594 | fdf9b3e8 | bellard | return;
|
595 | fdf9b3e8 | bellard | case 0x0007: /* mul.l Rm,Rn */ |
596 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
597 | fdf9b3e8 | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
598 | fdf9b3e8 | bellard | gen_op_mull_T0_T1(); |
599 | fdf9b3e8 | bellard | return;
|
600 | fdf9b3e8 | bellard | case 0x200f: /* muls.w Rm,Rn */ |
601 | fdf9b3e8 | bellard | gen_op_movw_rN_T0(REG(B7_4)); |
602 | fdf9b3e8 | bellard | gen_op_movw_rN_T1(REG(B11_8)); |
603 | fdf9b3e8 | bellard | gen_op_mulsw_T0_T1(); |
604 | fdf9b3e8 | bellard | return;
|
605 | fdf9b3e8 | bellard | case 0x200e: /* mulu.w Rm,Rn */ |
606 | fdf9b3e8 | bellard | gen_op_movuw_rN_T0(REG(B7_4)); |
607 | fdf9b3e8 | bellard | gen_op_movuw_rN_T1(REG(B11_8)); |
608 | fdf9b3e8 | bellard | gen_op_muluw_T0_T1(); |
609 | fdf9b3e8 | bellard | return;
|
610 | fdf9b3e8 | bellard | case 0x600b: /* neg Rm,Rn */ |
611 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
612 | fdf9b3e8 | bellard | gen_op_neg_T0(); |
613 | fdf9b3e8 | bellard | gen_op_movl_T0_rN(REG(B11_8)); |
614 | fdf9b3e8 | bellard | return;
|
615 | fdf9b3e8 | bellard | case 0x600a: /* negc Rm,Rn */ |
616 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
617 | fdf9b3e8 | bellard | gen_op_negc_T0(); |
618 | fdf9b3e8 | bellard | gen_op_movl_T0_rN(REG(B11_8)); |
619 | fdf9b3e8 | bellard | return;
|
620 | fdf9b3e8 | bellard | case 0x6007: /* not Rm,Rn */ |
621 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
622 | fdf9b3e8 | bellard | gen_op_not_T0(); |
623 | fdf9b3e8 | bellard | gen_op_movl_T0_rN(REG(B11_8)); |
624 | fdf9b3e8 | bellard | return;
|
625 | fdf9b3e8 | bellard | case 0x200b: /* or Rm,Rn */ |
626 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
627 | fdf9b3e8 | bellard | gen_op_or_T0_rN(REG(B11_8)); |
628 | fdf9b3e8 | bellard | return;
|
629 | fdf9b3e8 | bellard | case 0x400c: /* shad Rm,Rn */ |
630 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
631 | fdf9b3e8 | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
632 | fdf9b3e8 | bellard | gen_op_shad_T0_T1(); |
633 | fdf9b3e8 | bellard | gen_op_movl_T1_rN(REG(B11_8)); |
634 | fdf9b3e8 | bellard | return;
|
635 | fdf9b3e8 | bellard | case 0x400d: /* shld Rm,Rn */ |
636 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
637 | fdf9b3e8 | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
638 | fdf9b3e8 | bellard | gen_op_shld_T0_T1(); |
639 | fdf9b3e8 | bellard | gen_op_movl_T1_rN(REG(B11_8)); |
640 | fdf9b3e8 | bellard | return;
|
641 | fdf9b3e8 | bellard | case 0x3008: /* sub Rm,Rn */ |
642 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
643 | fdf9b3e8 | bellard | gen_op_sub_T0_rN(REG(B11_8)); |
644 | fdf9b3e8 | bellard | return;
|
645 | fdf9b3e8 | bellard | case 0x300a: /* subc Rm,Rn */ |
646 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
647 | fdf9b3e8 | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
648 | fdf9b3e8 | bellard | gen_op_subc_T0_T1(); |
649 | fdf9b3e8 | bellard | gen_op_movl_T1_rN(REG(B11_8)); |
650 | fdf9b3e8 | bellard | return;
|
651 | fdf9b3e8 | bellard | case 0x300b: /* subv Rm,Rn */ |
652 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
653 | fdf9b3e8 | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
654 | fdf9b3e8 | bellard | gen_op_subv_T0_T1(); |
655 | fdf9b3e8 | bellard | gen_op_movl_T1_rN(REG(B11_8)); |
656 | fdf9b3e8 | bellard | return;
|
657 | fdf9b3e8 | bellard | case 0x2008: /* tst Rm,Rn */ |
658 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
659 | fdf9b3e8 | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
660 | fdf9b3e8 | bellard | gen_op_tst_T0_T1(); |
661 | fdf9b3e8 | bellard | return;
|
662 | fdf9b3e8 | bellard | case 0x200a: /* xor Rm,Rn */ |
663 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
664 | fdf9b3e8 | bellard | gen_op_xor_T0_rN(REG(B11_8)); |
665 | fdf9b3e8 | bellard | return;
|
666 | e67888a7 | ths | case 0xf00c: /* fmov {F,D,X}Rm,{F,D,X}Rn - FPSCR: Nothing */ |
667 | 022a22c7 | ths | if (ctx->fpscr & FPSCR_SZ) {
|
668 | 24988dc2 | aurel32 | gen_op_fmov_drN_DT0(XREG(B7_4)); |
669 | 24988dc2 | aurel32 | gen_op_fmov_DT0_drN(XREG(B11_8)); |
670 | eda9b09b | bellard | } else {
|
671 | eda9b09b | bellard | gen_op_fmov_frN_FT0(FREG(B7_4)); |
672 | eda9b09b | bellard | gen_op_fmov_FT0_frN(FREG(B11_8)); |
673 | eda9b09b | bellard | } |
674 | eda9b09b | bellard | return;
|
675 | e67888a7 | ths | case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */ |
676 | 022a22c7 | ths | if (ctx->fpscr & FPSCR_SZ) {
|
677 | 24988dc2 | aurel32 | gen_op_fmov_drN_DT0(XREG(B7_4)); |
678 | eda9b09b | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
679 | eda9b09b | bellard | gen_op_stfq_DT0_T1(ctx); |
680 | eda9b09b | bellard | } else {
|
681 | eda9b09b | bellard | gen_op_fmov_frN_FT0(FREG(B7_4)); |
682 | eda9b09b | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
683 | eda9b09b | bellard | gen_op_stfl_FT0_T1(ctx); |
684 | eda9b09b | bellard | } |
685 | eda9b09b | bellard | return;
|
686 | e67888a7 | ths | case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */ |
687 | 022a22c7 | ths | if (ctx->fpscr & FPSCR_SZ) {
|
688 | eda9b09b | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
689 | eda9b09b | bellard | gen_op_ldfq_T0_DT0(ctx); |
690 | 24988dc2 | aurel32 | gen_op_fmov_DT0_drN(XREG(B11_8)); |
691 | eda9b09b | bellard | } else {
|
692 | eda9b09b | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
693 | eda9b09b | bellard | gen_op_ldfl_T0_FT0(ctx); |
694 | f09111e0 | ths | gen_op_fmov_FT0_frN(FREG(B11_8)); |
695 | eda9b09b | bellard | } |
696 | eda9b09b | bellard | return;
|
697 | e67888a7 | ths | case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */ |
698 | 022a22c7 | ths | if (ctx->fpscr & FPSCR_SZ) {
|
699 | eda9b09b | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
700 | eda9b09b | bellard | gen_op_ldfq_T0_DT0(ctx); |
701 | 24988dc2 | aurel32 | gen_op_fmov_DT0_drN(XREG(B11_8)); |
702 | eda9b09b | bellard | gen_op_inc8_rN(REG(B7_4)); |
703 | eda9b09b | bellard | } else {
|
704 | eda9b09b | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
705 | eda9b09b | bellard | gen_op_ldfl_T0_FT0(ctx); |
706 | f09111e0 | ths | gen_op_fmov_FT0_frN(FREG(B11_8)); |
707 | eda9b09b | bellard | gen_op_inc4_rN(REG(B7_4)); |
708 | eda9b09b | bellard | } |
709 | eda9b09b | bellard | return;
|
710 | e67888a7 | ths | case 0xf00b: /* fmov {F,D,X}Rm,@-Rn - FPSCR: Nothing */ |
711 | 022a22c7 | ths | if (ctx->fpscr & FPSCR_SZ) {
|
712 | eda9b09b | bellard | gen_op_dec8_rN(REG(B11_8)); |
713 | 24988dc2 | aurel32 | gen_op_fmov_drN_DT0(XREG(B7_4)); |
714 | eda9b09b | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
715 | 7da76bce | aurel32 | gen_op_inc8_rN(REG(B11_8)); |
716 | eda9b09b | bellard | gen_op_stfq_DT0_T1(ctx); |
717 | 7da76bce | aurel32 | gen_op_dec8_rN(REG(B11_8)); |
718 | eda9b09b | bellard | } else {
|
719 | eda9b09b | bellard | gen_op_dec4_rN(REG(B11_8)); |
720 | eda9b09b | bellard | gen_op_fmov_frN_FT0(FREG(B7_4)); |
721 | eda9b09b | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
722 | 7da76bce | aurel32 | gen_op_inc4_rN(REG(B11_8)); |
723 | eda9b09b | bellard | gen_op_stfl_FT0_T1(ctx); |
724 | 7da76bce | aurel32 | gen_op_dec4_rN(REG(B11_8)); |
725 | eda9b09b | bellard | } |
726 | eda9b09b | bellard | return;
|
727 | e67888a7 | ths | case 0xf006: /* fmov @(R0,Rm),{F,D,X}Rm - FPSCR: Nothing */ |
728 | 022a22c7 | ths | if (ctx->fpscr & FPSCR_SZ) {
|
729 | eda9b09b | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
730 | eda9b09b | bellard | gen_op_add_rN_T0(REG(0));
|
731 | eda9b09b | bellard | gen_op_ldfq_T0_DT0(ctx); |
732 | 24988dc2 | aurel32 | gen_op_fmov_DT0_drN(XREG(B11_8)); |
733 | eda9b09b | bellard | } else {
|
734 | eda9b09b | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
735 | eda9b09b | bellard | gen_op_add_rN_T0(REG(0));
|
736 | eda9b09b | bellard | gen_op_ldfl_T0_FT0(ctx); |
737 | f09111e0 | ths | gen_op_fmov_FT0_frN(FREG(B11_8)); |
738 | eda9b09b | bellard | } |
739 | eda9b09b | bellard | return;
|
740 | e67888a7 | ths | case 0xf007: /* fmov {F,D,X}Rn,@(R0,Rn) - FPSCR: Nothing */ |
741 | 022a22c7 | ths | if (ctx->fpscr & FPSCR_SZ) {
|
742 | 24988dc2 | aurel32 | gen_op_fmov_drN_DT0(XREG(B7_4)); |
743 | eda9b09b | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
744 | eda9b09b | bellard | gen_op_add_rN_T1(REG(0));
|
745 | eda9b09b | bellard | gen_op_stfq_DT0_T1(ctx); |
746 | eda9b09b | bellard | } else {
|
747 | eda9b09b | bellard | gen_op_fmov_frN_FT0(FREG(B7_4)); |
748 | eda9b09b | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
749 | eda9b09b | bellard | gen_op_add_rN_T1(REG(0));
|
750 | eda9b09b | bellard | gen_op_stfl_FT0_T1(ctx); |
751 | eda9b09b | bellard | } |
752 | eda9b09b | bellard | return;
|
753 | e67888a7 | ths | case 0xf000: /* fadd Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */ |
754 | e67888a7 | ths | case 0xf001: /* fsub Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */ |
755 | e67888a7 | ths | case 0xf002: /* fmul Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */ |
756 | e67888a7 | ths | case 0xf003: /* fdiv Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */ |
757 | e67888a7 | ths | case 0xf004: /* fcmp/eq Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */ |
758 | e67888a7 | ths | case 0xf005: /* fcmp/gt Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */ |
759 | ea6cf6be | ths | if (ctx->fpscr & FPSCR_PR) {
|
760 | ea6cf6be | ths | if (ctx->opcode & 0x0110) |
761 | ea6cf6be | ths | break; /* illegal instruction */ |
762 | ea6cf6be | ths | gen_op_fmov_drN_DT1(DREG(B7_4)); |
763 | ea6cf6be | ths | gen_op_fmov_drN_DT0(DREG(B11_8)); |
764 | ea6cf6be | ths | } |
765 | ea6cf6be | ths | else {
|
766 | ea6cf6be | ths | gen_op_fmov_frN_FT1(FREG(B7_4)); |
767 | ea6cf6be | ths | gen_op_fmov_frN_FT0(FREG(B11_8)); |
768 | ea6cf6be | ths | } |
769 | ea6cf6be | ths | |
770 | ea6cf6be | ths | switch (ctx->opcode & 0xf00f) { |
771 | ea6cf6be | ths | case 0xf000: /* fadd Rm,Rn */ |
772 | ea6cf6be | ths | ctx->fpscr & FPSCR_PR ? gen_op_fadd_DT() : gen_op_fadd_FT(); |
773 | ea6cf6be | ths | break;
|
774 | ea6cf6be | ths | case 0xf001: /* fsub Rm,Rn */ |
775 | ea6cf6be | ths | ctx->fpscr & FPSCR_PR ? gen_op_fsub_DT() : gen_op_fsub_FT(); |
776 | ea6cf6be | ths | break;
|
777 | ea6cf6be | ths | case 0xf002: /* fmul Rm,Rn */ |
778 | ea6cf6be | ths | ctx->fpscr & FPSCR_PR ? gen_op_fmul_DT() : gen_op_fmul_FT(); |
779 | ea6cf6be | ths | break;
|
780 | ea6cf6be | ths | case 0xf003: /* fdiv Rm,Rn */ |
781 | ea6cf6be | ths | ctx->fpscr & FPSCR_PR ? gen_op_fdiv_DT() : gen_op_fdiv_FT(); |
782 | ea6cf6be | ths | break;
|
783 | ea6cf6be | ths | case 0xf004: /* fcmp/eq Rm,Rn */ |
784 | 24988dc2 | aurel32 | ctx->fpscr & FPSCR_PR ? gen_op_fcmp_eq_DT() : gen_op_fcmp_eq_FT(); |
785 | ea6cf6be | ths | return;
|
786 | ea6cf6be | ths | case 0xf005: /* fcmp/gt Rm,Rn */ |
787 | 24988dc2 | aurel32 | ctx->fpscr & FPSCR_PR ? gen_op_fcmp_gt_DT() : gen_op_fcmp_gt_FT(); |
788 | ea6cf6be | ths | return;
|
789 | ea6cf6be | ths | } |
790 | ea6cf6be | ths | |
791 | ea6cf6be | ths | if (ctx->fpscr & FPSCR_PR) {
|
792 | ea6cf6be | ths | gen_op_fmov_DT0_drN(DREG(B11_8)); |
793 | ea6cf6be | ths | } |
794 | ea6cf6be | ths | else {
|
795 | ea6cf6be | ths | gen_op_fmov_FT0_frN(FREG(B11_8)); |
796 | ea6cf6be | ths | } |
797 | ea6cf6be | ths | return;
|
798 | fdf9b3e8 | bellard | } |
799 | fdf9b3e8 | bellard | |
800 | fdf9b3e8 | bellard | switch (ctx->opcode & 0xff00) { |
801 | fdf9b3e8 | bellard | case 0xc900: /* and #imm,R0 */ |
802 | fdf9b3e8 | bellard | gen_op_and_imm_rN(B7_0, REG(0));
|
803 | fdf9b3e8 | bellard | return;
|
804 | 24988dc2 | aurel32 | case 0xcd00: /* and.b #imm,@(R0,GBR) */ |
805 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(0));
|
806 | fdf9b3e8 | bellard | gen_op_addl_GBR_T0(); |
807 | fdf9b3e8 | bellard | gen_op_movl_T0_T1(); |
808 | 24988dc2 | aurel32 | gen_op_ldub_T0_T0(ctx); |
809 | fdf9b3e8 | bellard | gen_op_and_imm_T0(B7_0); |
810 | fdf9b3e8 | bellard | gen_op_stb_T0_T1(ctx); |
811 | fdf9b3e8 | bellard | return;
|
812 | fdf9b3e8 | bellard | case 0x8b00: /* bf label */ |
813 | fdf9b3e8 | bellard | CHECK_NOT_DELAY_SLOT |
814 | fdf9b3e8 | bellard | gen_conditional_jump(ctx, ctx->pc + 2,
|
815 | fdf9b3e8 | bellard | ctx->pc + 4 + B7_0s * 2); |
816 | 823029f9 | ths | ctx->bstate = BS_BRANCH; |
817 | fdf9b3e8 | bellard | return;
|
818 | fdf9b3e8 | bellard | case 0x8f00: /* bf/s label */ |
819 | fdf9b3e8 | bellard | CHECK_NOT_DELAY_SLOT |
820 | fdf9b3e8 | bellard | gen_op_bf_s(ctx->delayed_pc = ctx->pc + 4 + B7_0s * 2); |
821 | fdf9b3e8 | bellard | ctx->flags |= DELAY_SLOT_CONDITIONAL; |
822 | fdf9b3e8 | bellard | return;
|
823 | fdf9b3e8 | bellard | case 0x8900: /* bt label */ |
824 | fdf9b3e8 | bellard | CHECK_NOT_DELAY_SLOT |
825 | fdf9b3e8 | bellard | gen_conditional_jump(ctx, ctx->pc + 4 + B7_0s * 2, |
826 | fdf9b3e8 | bellard | ctx->pc + 2);
|
827 | 823029f9 | ths | ctx->bstate = BS_BRANCH; |
828 | fdf9b3e8 | bellard | return;
|
829 | fdf9b3e8 | bellard | case 0x8d00: /* bt/s label */ |
830 | fdf9b3e8 | bellard | CHECK_NOT_DELAY_SLOT |
831 | fdf9b3e8 | bellard | gen_op_bt_s(ctx->delayed_pc = ctx->pc + 4 + B7_0s * 2); |
832 | fdf9b3e8 | bellard | ctx->flags |= DELAY_SLOT_CONDITIONAL; |
833 | fdf9b3e8 | bellard | return;
|
834 | fdf9b3e8 | bellard | case 0x8800: /* cmp/eq #imm,R0 */ |
835 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(0));
|
836 | fdf9b3e8 | bellard | gen_op_cmp_eq_imm_T0(B7_0s); |
837 | fdf9b3e8 | bellard | return;
|
838 | fdf9b3e8 | bellard | case 0xc400: /* mov.b @(disp,GBR),R0 */ |
839 | fdf9b3e8 | bellard | gen_op_stc_gbr_T0(); |
840 | fdf9b3e8 | bellard | gen_op_addl_imm_T0(B7_0); |
841 | fdf9b3e8 | bellard | gen_op_ldb_T0_T0(ctx); |
842 | fdf9b3e8 | bellard | gen_op_movl_T0_rN(REG(0));
|
843 | fdf9b3e8 | bellard | return;
|
844 | fdf9b3e8 | bellard | case 0xc500: /* mov.w @(disp,GBR),R0 */ |
845 | fdf9b3e8 | bellard | gen_op_stc_gbr_T0(); |
846 | 24988dc2 | aurel32 | gen_op_addl_imm_T0(B7_0 * 2);
|
847 | fdf9b3e8 | bellard | gen_op_ldw_T0_T0(ctx); |
848 | fdf9b3e8 | bellard | gen_op_movl_T0_rN(REG(0));
|
849 | fdf9b3e8 | bellard | return;
|
850 | fdf9b3e8 | bellard | case 0xc600: /* mov.l @(disp,GBR),R0 */ |
851 | fdf9b3e8 | bellard | gen_op_stc_gbr_T0(); |
852 | 24988dc2 | aurel32 | gen_op_addl_imm_T0(B7_0 * 4);
|
853 | fdf9b3e8 | bellard | gen_op_ldl_T0_T0(ctx); |
854 | fdf9b3e8 | bellard | gen_op_movl_T0_rN(REG(0));
|
855 | fdf9b3e8 | bellard | return;
|
856 | fdf9b3e8 | bellard | case 0xc000: /* mov.b R0,@(disp,GBR) */ |
857 | fdf9b3e8 | bellard | gen_op_stc_gbr_T0(); |
858 | fdf9b3e8 | bellard | gen_op_addl_imm_T0(B7_0); |
859 | fdf9b3e8 | bellard | gen_op_movl_T0_T1(); |
860 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(0));
|
861 | fdf9b3e8 | bellard | gen_op_stb_T0_T1(ctx); |
862 | fdf9b3e8 | bellard | return;
|
863 | fdf9b3e8 | bellard | case 0xc100: /* mov.w R0,@(disp,GBR) */ |
864 | fdf9b3e8 | bellard | gen_op_stc_gbr_T0(); |
865 | 24988dc2 | aurel32 | gen_op_addl_imm_T0(B7_0 * 2);
|
866 | fdf9b3e8 | bellard | gen_op_movl_T0_T1(); |
867 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(0));
|
868 | fdf9b3e8 | bellard | gen_op_stw_T0_T1(ctx); |
869 | fdf9b3e8 | bellard | return;
|
870 | fdf9b3e8 | bellard | case 0xc200: /* mov.l R0,@(disp,GBR) */ |
871 | fdf9b3e8 | bellard | gen_op_stc_gbr_T0(); |
872 | 24988dc2 | aurel32 | gen_op_addl_imm_T0(B7_0 * 4);
|
873 | fdf9b3e8 | bellard | gen_op_movl_T0_T1(); |
874 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(0));
|
875 | fdf9b3e8 | bellard | gen_op_stl_T0_T1(ctx); |
876 | fdf9b3e8 | bellard | return;
|
877 | fdf9b3e8 | bellard | case 0x8000: /* mov.b R0,@(disp,Rn) */ |
878 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(0));
|
879 | fdf9b3e8 | bellard | gen_op_movl_rN_T1(REG(B7_4)); |
880 | fdf9b3e8 | bellard | gen_op_addl_imm_T1(B3_0); |
881 | fdf9b3e8 | bellard | gen_op_stb_T0_T1(ctx); |
882 | fdf9b3e8 | bellard | return;
|
883 | fdf9b3e8 | bellard | case 0x8100: /* mov.w R0,@(disp,Rn) */ |
884 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(0));
|
885 | fdf9b3e8 | bellard | gen_op_movl_rN_T1(REG(B7_4)); |
886 | fdf9b3e8 | bellard | gen_op_addl_imm_T1(B3_0 * 2);
|
887 | fdf9b3e8 | bellard | gen_op_stw_T0_T1(ctx); |
888 | fdf9b3e8 | bellard | return;
|
889 | fdf9b3e8 | bellard | case 0x8400: /* mov.b @(disp,Rn),R0 */ |
890 | 8c2cc7ce | ths | gen_op_movl_rN_T0(REG(B7_4)); |
891 | 8c2cc7ce | ths | gen_op_addl_imm_T0(B3_0); |
892 | 8c2cc7ce | ths | gen_op_ldb_T0_T0(ctx); |
893 | 8c2cc7ce | ths | gen_op_movl_T0_rN(REG(0));
|
894 | fdf9b3e8 | bellard | return;
|
895 | fdf9b3e8 | bellard | case 0x8500: /* mov.w @(disp,Rn),R0 */ |
896 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B7_4)); |
897 | fdf9b3e8 | bellard | gen_op_addl_imm_T0(B3_0 * 2);
|
898 | fdf9b3e8 | bellard | gen_op_ldw_T0_T0(ctx); |
899 | fdf9b3e8 | bellard | gen_op_movl_T0_rN(REG(0));
|
900 | fdf9b3e8 | bellard | return;
|
901 | fdf9b3e8 | bellard | case 0xc700: /* mova @(disp,PC),R0 */ |
902 | fdf9b3e8 | bellard | gen_op_movl_imm_rN(((ctx->pc & 0xfffffffc) + 4 + B7_0 * 4) & ~3, |
903 | fdf9b3e8 | bellard | REG(0));
|
904 | fdf9b3e8 | bellard | return;
|
905 | fdf9b3e8 | bellard | case 0xcb00: /* or #imm,R0 */ |
906 | fdf9b3e8 | bellard | gen_op_or_imm_rN(B7_0, REG(0));
|
907 | fdf9b3e8 | bellard | return;
|
908 | 24988dc2 | aurel32 | case 0xcf00: /* or.b #imm,@(R0,GBR) */ |
909 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(0));
|
910 | fdf9b3e8 | bellard | gen_op_addl_GBR_T0(); |
911 | fdf9b3e8 | bellard | gen_op_movl_T0_T1(); |
912 | 24988dc2 | aurel32 | gen_op_ldub_T0_T0(ctx); |
913 | fdf9b3e8 | bellard | gen_op_or_imm_T0(B7_0); |
914 | fdf9b3e8 | bellard | gen_op_stb_T0_T1(ctx); |
915 | fdf9b3e8 | bellard | return;
|
916 | fdf9b3e8 | bellard | case 0xc300: /* trapa #imm */ |
917 | fdf9b3e8 | bellard | CHECK_NOT_DELAY_SLOT gen_op_movl_imm_PC(ctx->pc); |
918 | fdf9b3e8 | bellard | gen_op_trapa(B7_0); |
919 | 823029f9 | ths | ctx->bstate = BS_BRANCH; |
920 | fdf9b3e8 | bellard | return;
|
921 | fdf9b3e8 | bellard | case 0xc800: /* tst #imm,R0 */ |
922 | fdf9b3e8 | bellard | gen_op_tst_imm_rN(B7_0, REG(0));
|
923 | fdf9b3e8 | bellard | return;
|
924 | 24988dc2 | aurel32 | case 0xcc00: /* tst.b #imm,@(R0,GBR) */ |
925 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(0));
|
926 | fdf9b3e8 | bellard | gen_op_addl_GBR_T0(); |
927 | 24988dc2 | aurel32 | gen_op_ldub_T0_T0(ctx); |
928 | fdf9b3e8 | bellard | gen_op_tst_imm_T0(B7_0); |
929 | fdf9b3e8 | bellard | return;
|
930 | fdf9b3e8 | bellard | case 0xca00: /* xor #imm,R0 */ |
931 | fdf9b3e8 | bellard | gen_op_xor_imm_rN(B7_0, REG(0));
|
932 | fdf9b3e8 | bellard | return;
|
933 | 24988dc2 | aurel32 | case 0xce00: /* xor.b #imm,@(R0,GBR) */ |
934 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(0));
|
935 | fdf9b3e8 | bellard | gen_op_addl_GBR_T0(); |
936 | fdf9b3e8 | bellard | gen_op_movl_T0_T1(); |
937 | 24988dc2 | aurel32 | gen_op_ldub_T0_T0(ctx); |
938 | fdf9b3e8 | bellard | gen_op_xor_imm_T0(B7_0); |
939 | fdf9b3e8 | bellard | gen_op_stb_T0_T1(ctx); |
940 | fdf9b3e8 | bellard | return;
|
941 | fdf9b3e8 | bellard | } |
942 | fdf9b3e8 | bellard | |
943 | fdf9b3e8 | bellard | switch (ctx->opcode & 0xf08f) { |
944 | fdf9b3e8 | bellard | case 0x408e: /* ldc Rm,Rn_BANK */ |
945 | fdf9b3e8 | bellard | gen_op_movl_rN_rN(REG(B11_8), ALTREG(B6_4)); |
946 | fdf9b3e8 | bellard | return;
|
947 | fdf9b3e8 | bellard | case 0x4087: /* ldc.l @Rm+,Rn_BANK */ |
948 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B11_8)); |
949 | fdf9b3e8 | bellard | gen_op_ldl_T0_T0(ctx); |
950 | fdf9b3e8 | bellard | gen_op_movl_T0_rN(ALTREG(B6_4)); |
951 | fdf9b3e8 | bellard | gen_op_inc4_rN(REG(B11_8)); |
952 | fdf9b3e8 | bellard | return;
|
953 | fdf9b3e8 | bellard | case 0x0082: /* stc Rm_BANK,Rn */ |
954 | fdf9b3e8 | bellard | gen_op_movl_rN_rN(ALTREG(B6_4), REG(B11_8)); |
955 | fdf9b3e8 | bellard | return;
|
956 | fdf9b3e8 | bellard | case 0x4083: /* stc.l Rm_BANK,@-Rn */ |
957 | fdf9b3e8 | bellard | gen_op_dec4_rN(REG(B11_8)); |
958 | fdf9b3e8 | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
959 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(ALTREG(B6_4)); |
960 | 7da76bce | aurel32 | gen_op_inc4_rN(REG(B11_8)); |
961 | fdf9b3e8 | bellard | gen_op_stl_T0_T1(ctx); |
962 | 7da76bce | aurel32 | gen_op_dec4_rN(REG(B11_8)); |
963 | fdf9b3e8 | bellard | return;
|
964 | fdf9b3e8 | bellard | } |
965 | fdf9b3e8 | bellard | |
966 | fdf9b3e8 | bellard | switch (ctx->opcode & 0xf0ff) { |
967 | fdf9b3e8 | bellard | case 0x0023: /* braf Rn */ |
968 | fdf9b3e8 | bellard | CHECK_NOT_DELAY_SLOT gen_op_movl_rN_T0(REG(B11_8)); |
969 | fdf9b3e8 | bellard | gen_op_braf_T0(ctx->pc + 4);
|
970 | fdf9b3e8 | bellard | ctx->flags |= DELAY_SLOT; |
971 | fdf9b3e8 | bellard | ctx->delayed_pc = (uint32_t) - 1;
|
972 | fdf9b3e8 | bellard | return;
|
973 | fdf9b3e8 | bellard | case 0x0003: /* bsrf Rn */ |
974 | fdf9b3e8 | bellard | CHECK_NOT_DELAY_SLOT gen_op_movl_rN_T0(REG(B11_8)); |
975 | fdf9b3e8 | bellard | gen_op_bsrf_T0(ctx->pc + 4);
|
976 | fdf9b3e8 | bellard | ctx->flags |= DELAY_SLOT; |
977 | fdf9b3e8 | bellard | ctx->delayed_pc = (uint32_t) - 1;
|
978 | fdf9b3e8 | bellard | return;
|
979 | fdf9b3e8 | bellard | case 0x4015: /* cmp/pl Rn */ |
980 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B11_8)); |
981 | fdf9b3e8 | bellard | gen_op_cmp_pl_T0(); |
982 | fdf9b3e8 | bellard | return;
|
983 | fdf9b3e8 | bellard | case 0x4011: /* cmp/pz Rn */ |
984 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B11_8)); |
985 | fdf9b3e8 | bellard | gen_op_cmp_pz_T0(); |
986 | fdf9b3e8 | bellard | return;
|
987 | fdf9b3e8 | bellard | case 0x4010: /* dt Rn */ |
988 | fdf9b3e8 | bellard | gen_op_dt_rN(REG(B11_8)); |
989 | fdf9b3e8 | bellard | return;
|
990 | fdf9b3e8 | bellard | case 0x402b: /* jmp @Rn */ |
991 | fdf9b3e8 | bellard | CHECK_NOT_DELAY_SLOT gen_op_movl_rN_T0(REG(B11_8)); |
992 | fdf9b3e8 | bellard | gen_op_jmp_T0(); |
993 | fdf9b3e8 | bellard | ctx->flags |= DELAY_SLOT; |
994 | fdf9b3e8 | bellard | ctx->delayed_pc = (uint32_t) - 1;
|
995 | fdf9b3e8 | bellard | return;
|
996 | fdf9b3e8 | bellard | case 0x400b: /* jsr @Rn */ |
997 | fdf9b3e8 | bellard | CHECK_NOT_DELAY_SLOT gen_op_movl_rN_T0(REG(B11_8)); |
998 | fdf9b3e8 | bellard | gen_op_jsr_T0(ctx->pc + 4);
|
999 | fdf9b3e8 | bellard | ctx->flags |= DELAY_SLOT; |
1000 | fdf9b3e8 | bellard | ctx->delayed_pc = (uint32_t) - 1;
|
1001 | fdf9b3e8 | bellard | return;
|
1002 | fdf9b3e8 | bellard | #define LDST(reg,ldnum,ldpnum,ldop,stnum,stpnum,stop,extrald) \
|
1003 | fdf9b3e8 | bellard | case ldnum: \
|
1004 | fdf9b3e8 | bellard | gen_op_movl_rN_T0 (REG(B11_8)); \ |
1005 | fdf9b3e8 | bellard | gen_op_##ldop##_T0_##reg (); \ |
1006 | fdf9b3e8 | bellard | extrald \ |
1007 | fdf9b3e8 | bellard | return; \
|
1008 | fdf9b3e8 | bellard | case ldpnum: \
|
1009 | fdf9b3e8 | bellard | gen_op_movl_rN_T0 (REG(B11_8)); \ |
1010 | fdf9b3e8 | bellard | gen_op_ldl_T0_T0 (ctx); \ |
1011 | fdf9b3e8 | bellard | gen_op_inc4_rN (REG(B11_8)); \ |
1012 | fdf9b3e8 | bellard | gen_op_##ldop##_T0_##reg (); \ |
1013 | fdf9b3e8 | bellard | extrald \ |
1014 | fdf9b3e8 | bellard | return; \
|
1015 | fdf9b3e8 | bellard | case stnum: \
|
1016 | fdf9b3e8 | bellard | gen_op_##stop##_##reg##_T0 (); \ |
1017 | fdf9b3e8 | bellard | gen_op_movl_T0_rN (REG(B11_8)); \ |
1018 | fdf9b3e8 | bellard | return; \
|
1019 | fdf9b3e8 | bellard | case stpnum: \
|
1020 | fdf9b3e8 | bellard | gen_op_##stop##_##reg##_T0 (); \ |
1021 | fdf9b3e8 | bellard | gen_op_dec4_rN (REG(B11_8)); \ |
1022 | fdf9b3e8 | bellard | gen_op_movl_rN_T1 (REG(B11_8)); \ |
1023 | 7da76bce | aurel32 | gen_op_inc4_rN (REG(B11_8)); \ |
1024 | fdf9b3e8 | bellard | gen_op_stl_T0_T1 (ctx); \ |
1025 | 7da76bce | aurel32 | gen_op_dec4_rN (REG(B11_8)); \ |
1026 | fdf9b3e8 | bellard | return;
|
1027 | 823029f9 | ths | LDST(sr, 0x400e, 0x4007, ldc, 0x0002, 0x4003, stc, ctx->bstate = |
1028 | 823029f9 | ths | BS_STOP;) |
1029 | eda9b09b | bellard | LDST(gbr, 0x401e, 0x4017, ldc, 0x0012, 0x4013, stc,) |
1030 | eda9b09b | bellard | LDST(vbr, 0x402e, 0x4027, ldc, 0x0022, 0x4023, stc,) |
1031 | eda9b09b | bellard | LDST(ssr, 0x403e, 0x4037, ldc, 0x0032, 0x4033, stc,) |
1032 | eda9b09b | bellard | LDST(spc, 0x404e, 0x4047, ldc, 0x0042, 0x4043, stc,) |
1033 | eda9b09b | bellard | LDST(dbr, 0x40fa, 0x40f6, ldc, 0x00fa, 0x40f2, stc,) |
1034 | eda9b09b | bellard | LDST(mach, 0x400a, 0x4006, lds, 0x000a, 0x4002, sts,) |
1035 | eda9b09b | bellard | LDST(macl, 0x401a, 0x4016, lds, 0x001a, 0x4012, sts,) |
1036 | eda9b09b | bellard | LDST(pr, 0x402a, 0x4026, lds, 0x002a, 0x4022, sts,) |
1037 | 8bf5a804 | ths | LDST(fpul, 0x405a, 0x4056, lds, 0x005a, 0x4052, sts,) |
1038 | 823029f9 | ths | LDST(fpscr, 0x406a, 0x4066, lds, 0x006a, 0x4062, sts, ctx->bstate = |
1039 | 823029f9 | ths | BS_STOP;) |
1040 | fdf9b3e8 | bellard | case 0x00c3: /* movca.l R0,@Rm */ |
1041 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(0));
|
1042 | fdf9b3e8 | bellard | gen_op_movl_rN_T1(REG(B11_8)); |
1043 | fdf9b3e8 | bellard | gen_op_stl_T0_T1(ctx); |
1044 | fdf9b3e8 | bellard | return;
|
1045 | fdf9b3e8 | bellard | case 0x0029: /* movt Rn */ |
1046 | fdf9b3e8 | bellard | gen_op_movt_rN(REG(B11_8)); |
1047 | fdf9b3e8 | bellard | return;
|
1048 | fdf9b3e8 | bellard | case 0x0093: /* ocbi @Rn */ |
1049 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B11_8)); |
1050 | fdf9b3e8 | bellard | gen_op_ldl_T0_T0(ctx); |
1051 | fdf9b3e8 | bellard | return;
|
1052 | 24988dc2 | aurel32 | case 0x00a3: /* ocbp @Rn */ |
1053 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B11_8)); |
1054 | fdf9b3e8 | bellard | gen_op_ldl_T0_T0(ctx); |
1055 | fdf9b3e8 | bellard | return;
|
1056 | fdf9b3e8 | bellard | case 0x00b3: /* ocbwb @Rn */ |
1057 | fdf9b3e8 | bellard | gen_op_movl_rN_T0(REG(B11_8)); |
1058 | fdf9b3e8 | bellard | gen_op_ldl_T0_T0(ctx); |
1059 | fdf9b3e8 | bellard | return;
|
1060 | fdf9b3e8 | bellard | case 0x0083: /* pref @Rn */ |
1061 | fdf9b3e8 | bellard | return;
|
1062 | fdf9b3e8 | bellard | case 0x4024: /* rotcl Rn */ |
1063 | fdf9b3e8 | bellard | gen_op_rotcl_Rn(REG(B11_8)); |
1064 | fdf9b3e8 | bellard | return;
|
1065 | fdf9b3e8 | bellard | case 0x4025: /* rotcr Rn */ |
1066 | fdf9b3e8 | bellard | gen_op_rotcr_Rn(REG(B11_8)); |
1067 | fdf9b3e8 | bellard | return;
|
1068 | fdf9b3e8 | bellard | case 0x4004: /* rotl Rn */ |
1069 | fdf9b3e8 | bellard | gen_op_rotl_Rn(REG(B11_8)); |
1070 | fdf9b3e8 | bellard | return;
|
1071 | fdf9b3e8 | bellard | case 0x4005: /* rotr Rn */ |
1072 | fdf9b3e8 | bellard | gen_op_rotr_Rn(REG(B11_8)); |
1073 | fdf9b3e8 | bellard | return;
|
1074 | fdf9b3e8 | bellard | case 0x4000: /* shll Rn */ |
1075 | fdf9b3e8 | bellard | case 0x4020: /* shal Rn */ |
1076 | fdf9b3e8 | bellard | gen_op_shal_Rn(REG(B11_8)); |
1077 | fdf9b3e8 | bellard | return;
|
1078 | fdf9b3e8 | bellard | case 0x4021: /* shar Rn */ |
1079 | fdf9b3e8 | bellard | gen_op_shar_Rn(REG(B11_8)); |
1080 | fdf9b3e8 | bellard | return;
|
1081 | fdf9b3e8 | bellard | case 0x4001: /* shlr Rn */ |
1082 | fdf9b3e8 | bellard | gen_op_shlr_Rn(REG(B11_8)); |
1083 | fdf9b3e8 | bellard | return;
|
1084 | fdf9b3e8 | bellard | case 0x4008: /* shll2 Rn */ |
1085 | fdf9b3e8 | bellard | gen_op_shll2_Rn(REG(B11_8)); |
1086 | fdf9b3e8 | bellard | return;
|
1087 | fdf9b3e8 | bellard | case 0x4018: /* shll8 Rn */ |
1088 | fdf9b3e8 | bellard | gen_op_shll8_Rn(REG(B11_8)); |
1089 | fdf9b3e8 | bellard | return;
|
1090 | fdf9b3e8 | bellard | case 0x4028: /* shll16 Rn */ |
1091 | fdf9b3e8 | bellard | gen_op_shll16_Rn(REG(B11_8)); |
1092 | fdf9b3e8 | bellard | return;
|
1093 | fdf9b3e8 | bellard | case 0x4009: /* shlr2 Rn */ |
1094 | fdf9b3e8 | bellard | gen_op_shlr2_Rn(REG(B11_8)); |
1095 | fdf9b3e8 | bellard | return;
|
1096 | fdf9b3e8 | bellard | case 0x4019: /* shlr8 Rn */ |
1097 | fdf9b3e8 | bellard | gen_op_shlr8_Rn(REG(B11_8)); |
1098 | fdf9b3e8 | bellard | return;
|
1099 | fdf9b3e8 | bellard | case 0x4029: /* shlr16 Rn */ |
1100 | fdf9b3e8 | bellard | gen_op_shlr16_Rn(REG(B11_8)); |
1101 | fdf9b3e8 | bellard | return;
|
1102 | fdf9b3e8 | bellard | case 0x401b: /* tas.b @Rn */ |
1103 | fdf9b3e8 | bellard | gen_op_tasb_rN(REG(B11_8)); |
1104 | fdf9b3e8 | bellard | return;
|
1105 | e67888a7 | ths | case 0xf00d: /* fsts FPUL,FRn - FPSCR: Nothing */ |
1106 | eda9b09b | bellard | gen_op_movl_fpul_FT0(); |
1107 | eda9b09b | bellard | gen_op_fmov_FT0_frN(FREG(B11_8)); |
1108 | eda9b09b | bellard | return;
|
1109 | e67888a7 | ths | case 0xf01d: /* flds FRm,FPUL - FPSCR: Nothing */ |
1110 | eda9b09b | bellard | gen_op_fmov_frN_FT0(FREG(B11_8)); |
1111 | eda9b09b | bellard | gen_op_movl_FT0_fpul(); |
1112 | eda9b09b | bellard | return;
|
1113 | e67888a7 | ths | case 0xf02d: /* float FPUL,FRn/DRn - FPSCR: R[PR,Enable.I]/W[Cause,Flag] */ |
1114 | ea6cf6be | ths | if (ctx->fpscr & FPSCR_PR) {
|
1115 | ea6cf6be | ths | if (ctx->opcode & 0x0100) |
1116 | ea6cf6be | ths | break; /* illegal instruction */ |
1117 | ea6cf6be | ths | gen_op_float_DT(); |
1118 | ea6cf6be | ths | gen_op_fmov_DT0_drN(DREG(B11_8)); |
1119 | ea6cf6be | ths | } |
1120 | ea6cf6be | ths | else {
|
1121 | ea6cf6be | ths | gen_op_float_FT(); |
1122 | ea6cf6be | ths | gen_op_fmov_FT0_frN(FREG(B11_8)); |
1123 | ea6cf6be | ths | } |
1124 | ea6cf6be | ths | return;
|
1125 | e67888a7 | ths | case 0xf03d: /* ftrc FRm/DRm,FPUL - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */ |
1126 | ea6cf6be | ths | if (ctx->fpscr & FPSCR_PR) {
|
1127 | ea6cf6be | ths | if (ctx->opcode & 0x0100) |
1128 | ea6cf6be | ths | break; /* illegal instruction */ |
1129 | ea6cf6be | ths | gen_op_fmov_drN_DT0(DREG(B11_8)); |
1130 | ea6cf6be | ths | gen_op_ftrc_DT(); |
1131 | ea6cf6be | ths | } |
1132 | ea6cf6be | ths | else {
|
1133 | ea6cf6be | ths | gen_op_fmov_frN_FT0(FREG(B11_8)); |
1134 | ea6cf6be | ths | gen_op_ftrc_FT(); |
1135 | ea6cf6be | ths | } |
1136 | ea6cf6be | ths | return;
|
1137 | 24988dc2 | aurel32 | case 0xf04d: /* fneg FRn/DRn - FPSCR: Nothing */ |
1138 | 24988dc2 | aurel32 | gen_op_fneg_frN(FREG(B11_8)); |
1139 | 24988dc2 | aurel32 | return;
|
1140 | 24988dc2 | aurel32 | case 0xf05d: /* fabs FRn/DRn */ |
1141 | 24988dc2 | aurel32 | if (ctx->fpscr & FPSCR_PR) {
|
1142 | 24988dc2 | aurel32 | if (ctx->opcode & 0x0100) |
1143 | 24988dc2 | aurel32 | break; /* illegal instruction */ |
1144 | 24988dc2 | aurel32 | gen_op_fmov_drN_DT0(DREG(B11_8)); |
1145 | 24988dc2 | aurel32 | gen_op_fabs_DT(); |
1146 | 24988dc2 | aurel32 | gen_op_fmov_DT0_drN(DREG(B11_8)); |
1147 | 24988dc2 | aurel32 | } else {
|
1148 | 24988dc2 | aurel32 | gen_op_fmov_frN_FT0(FREG(B11_8)); |
1149 | 24988dc2 | aurel32 | gen_op_fabs_FT(); |
1150 | 24988dc2 | aurel32 | gen_op_fmov_FT0_frN(FREG(B11_8)); |
1151 | 24988dc2 | aurel32 | } |
1152 | 24988dc2 | aurel32 | return;
|
1153 | 24988dc2 | aurel32 | case 0xf06d: /* fsqrt FRn */ |
1154 | 24988dc2 | aurel32 | if (ctx->fpscr & FPSCR_PR) {
|
1155 | 24988dc2 | aurel32 | if (ctx->opcode & 0x0100) |
1156 | 24988dc2 | aurel32 | break; /* illegal instruction */ |
1157 | 24988dc2 | aurel32 | gen_op_fmov_drN_DT0(FREG(B11_8)); |
1158 | 24988dc2 | aurel32 | gen_op_fsqrt_DT(); |
1159 | 24988dc2 | aurel32 | gen_op_fmov_DT0_drN(FREG(B11_8)); |
1160 | 24988dc2 | aurel32 | } else {
|
1161 | 24988dc2 | aurel32 | gen_op_fmov_frN_FT0(FREG(B11_8)); |
1162 | 24988dc2 | aurel32 | gen_op_fsqrt_FT(); |
1163 | 24988dc2 | aurel32 | gen_op_fmov_FT0_frN(FREG(B11_8)); |
1164 | 24988dc2 | aurel32 | } |
1165 | 24988dc2 | aurel32 | return;
|
1166 | 24988dc2 | aurel32 | case 0xf07d: /* fsrra FRn */ |
1167 | 24988dc2 | aurel32 | break;
|
1168 | e67888a7 | ths | case 0xf08d: /* fldi0 FRn - FPSCR: R[PR] */ |
1169 | ea6cf6be | ths | if (!(ctx->fpscr & FPSCR_PR)) {
|
1170 | ea6cf6be | ths | gen_op_movl_imm_T0(0);
|
1171 | ea6cf6be | ths | gen_op_fmov_T0_frN(FREG(B11_8)); |
1172 | ea6cf6be | ths | return;
|
1173 | ea6cf6be | ths | } |
1174 | ea6cf6be | ths | break;
|
1175 | e67888a7 | ths | case 0xf09d: /* fldi1 FRn - FPSCR: R[PR] */ |
1176 | ea6cf6be | ths | if (!(ctx->fpscr & FPSCR_PR)) {
|
1177 | ea6cf6be | ths | gen_op_movl_imm_T0(0x3f800000);
|
1178 | ea6cf6be | ths | gen_op_fmov_T0_frN(FREG(B11_8)); |
1179 | ea6cf6be | ths | return;
|
1180 | ea6cf6be | ths | } |
1181 | ea6cf6be | ths | break;
|
1182 | 24988dc2 | aurel32 | case 0xf0ad: /* fcnvsd FPUL,DRn */ |
1183 | 24988dc2 | aurel32 | gen_op_movl_fpul_FT0(); |
1184 | 24988dc2 | aurel32 | gen_op_fcnvsd_FT_DT(); |
1185 | 24988dc2 | aurel32 | gen_op_fmov_DT0_drN(DREG(B11_8)); |
1186 | 24988dc2 | aurel32 | return;
|
1187 | 24988dc2 | aurel32 | case 0xf0bd: /* fcnvds DRn,FPUL */ |
1188 | 24988dc2 | aurel32 | gen_op_fmov_drN_DT0(DREG(B11_8)); |
1189 | 24988dc2 | aurel32 | gen_op_fcnvds_DT_FT(); |
1190 | 24988dc2 | aurel32 | gen_op_movl_FT0_fpul(); |
1191 | 24988dc2 | aurel32 | return;
|
1192 | fdf9b3e8 | bellard | } |
1193 | fdf9b3e8 | bellard | |
1194 | fdf9b3e8 | bellard | fprintf(stderr, "unknown instruction 0x%04x at pc 0x%08x\n",
|
1195 | fdf9b3e8 | bellard | ctx->opcode, ctx->pc); |
1196 | fdf9b3e8 | bellard | gen_op_raise_illegal_instruction(); |
1197 | 823029f9 | ths | ctx->bstate = BS_EXCP; |
1198 | 823029f9 | ths | } |
1199 | 823029f9 | ths | |
1200 | 823029f9 | ths | void decode_opc(DisasContext * ctx)
|
1201 | 823029f9 | ths | { |
1202 | 823029f9 | ths | uint32_t old_flags = ctx->flags; |
1203 | 823029f9 | ths | |
1204 | 823029f9 | ths | _decode_opc(ctx); |
1205 | 823029f9 | ths | |
1206 | 823029f9 | ths | if (old_flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) {
|
1207 | 823029f9 | ths | if (ctx->flags & DELAY_SLOT_CLEARME) {
|
1208 | 823029f9 | ths | gen_op_store_flags(0);
|
1209 | 274a9e70 | aurel32 | } else {
|
1210 | 274a9e70 | aurel32 | /* go out of the delay slot */
|
1211 | 274a9e70 | aurel32 | uint32_t new_flags = ctx->flags; |
1212 | 274a9e70 | aurel32 | new_flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL); |
1213 | 274a9e70 | aurel32 | gen_op_store_flags(new_flags); |
1214 | 823029f9 | ths | } |
1215 | 823029f9 | ths | ctx->flags = 0;
|
1216 | 823029f9 | ths | ctx->bstate = BS_BRANCH; |
1217 | 823029f9 | ths | if (old_flags & DELAY_SLOT_CONDITIONAL) {
|
1218 | 823029f9 | ths | gen_delayed_conditional_jump(ctx); |
1219 | 823029f9 | ths | } else if (old_flags & DELAY_SLOT) { |
1220 | 823029f9 | ths | gen_jump(ctx); |
1221 | 823029f9 | ths | } |
1222 | 823029f9 | ths | |
1223 | 823029f9 | ths | } |
1224 | 274a9e70 | aurel32 | |
1225 | 274a9e70 | aurel32 | /* go into a delay slot */
|
1226 | 274a9e70 | aurel32 | if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL))
|
1227 | 274a9e70 | aurel32 | gen_op_store_flags(ctx->flags); |
1228 | fdf9b3e8 | bellard | } |
1229 | fdf9b3e8 | bellard | |
1230 | 2cfc5f17 | ths | static inline void |
1231 | 820e00f2 | ths | gen_intermediate_code_internal(CPUState * env, TranslationBlock * tb, |
1232 | 820e00f2 | ths | int search_pc)
|
1233 | fdf9b3e8 | bellard | { |
1234 | fdf9b3e8 | bellard | DisasContext ctx; |
1235 | fdf9b3e8 | bellard | target_ulong pc_start; |
1236 | fdf9b3e8 | bellard | static uint16_t *gen_opc_end;
|
1237 | 355fb23d | pbrook | int i, ii;
|
1238 | 2e70f6ef | pbrook | int num_insns;
|
1239 | 2e70f6ef | pbrook | int max_insns;
|
1240 | fdf9b3e8 | bellard | |
1241 | fdf9b3e8 | bellard | pc_start = tb->pc; |
1242 | fdf9b3e8 | bellard | gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; |
1243 | fdf9b3e8 | bellard | ctx.pc = pc_start; |
1244 | 823029f9 | ths | ctx.flags = (uint32_t)tb->flags; |
1245 | 823029f9 | ths | ctx.bstate = BS_NONE; |
1246 | fdf9b3e8 | bellard | ctx.sr = env->sr; |
1247 | eda9b09b | bellard | ctx.fpscr = env->fpscr; |
1248 | fdf9b3e8 | bellard | ctx.memidx = (env->sr & SR_MD) ? 1 : 0; |
1249 | 9854bc46 | pbrook | /* We don't know if the delayed pc came from a dynamic or static branch,
|
1250 | 9854bc46 | pbrook | so assume it is a dynamic branch. */
|
1251 | 823029f9 | ths | ctx.delayed_pc = -1; /* use delayed pc from env pointer */ |
1252 | fdf9b3e8 | bellard | ctx.tb = tb; |
1253 | fdf9b3e8 | bellard | ctx.singlestep_enabled = env->singlestep_enabled; |
1254 | fdf9b3e8 | bellard | |
1255 | fdf9b3e8 | bellard | #ifdef DEBUG_DISAS
|
1256 | fdf9b3e8 | bellard | if (loglevel & CPU_LOG_TB_CPU) {
|
1257 | fdf9b3e8 | bellard | fprintf(logfile, |
1258 | fdf9b3e8 | bellard | "------------------------------------------------\n");
|
1259 | fdf9b3e8 | bellard | cpu_dump_state(env, logfile, fprintf, 0);
|
1260 | fdf9b3e8 | bellard | } |
1261 | fdf9b3e8 | bellard | #endif
|
1262 | fdf9b3e8 | bellard | |
1263 | 355fb23d | pbrook | ii = -1;
|
1264 | 2e70f6ef | pbrook | num_insns = 0;
|
1265 | 2e70f6ef | pbrook | max_insns = tb->cflags & CF_COUNT_MASK; |
1266 | 2e70f6ef | pbrook | if (max_insns == 0) |
1267 | 2e70f6ef | pbrook | max_insns = CF_COUNT_MASK; |
1268 | 2e70f6ef | pbrook | gen_icount_start(); |
1269 | 823029f9 | ths | while (ctx.bstate == BS_NONE && gen_opc_ptr < gen_opc_end) {
|
1270 | fdf9b3e8 | bellard | if (env->nb_breakpoints > 0) { |
1271 | fdf9b3e8 | bellard | for (i = 0; i < env->nb_breakpoints; i++) { |
1272 | fdf9b3e8 | bellard | if (ctx.pc == env->breakpoints[i]) {
|
1273 | fdf9b3e8 | bellard | /* We have hit a breakpoint - make sure PC is up-to-date */
|
1274 | fdf9b3e8 | bellard | gen_op_movl_imm_PC(ctx.pc); |
1275 | fdf9b3e8 | bellard | gen_op_debug(); |
1276 | 823029f9 | ths | ctx.bstate = BS_EXCP; |
1277 | fdf9b3e8 | bellard | break;
|
1278 | fdf9b3e8 | bellard | } |
1279 | fdf9b3e8 | bellard | } |
1280 | fdf9b3e8 | bellard | } |
1281 | 355fb23d | pbrook | if (search_pc) {
|
1282 | 355fb23d | pbrook | i = gen_opc_ptr - gen_opc_buf; |
1283 | 355fb23d | pbrook | if (ii < i) {
|
1284 | 355fb23d | pbrook | ii++; |
1285 | 355fb23d | pbrook | while (ii < i)
|
1286 | 355fb23d | pbrook | gen_opc_instr_start[ii++] = 0;
|
1287 | 355fb23d | pbrook | } |
1288 | 355fb23d | pbrook | gen_opc_pc[ii] = ctx.pc; |
1289 | 823029f9 | ths | gen_opc_hflags[ii] = ctx.flags; |
1290 | 355fb23d | pbrook | gen_opc_instr_start[ii] = 1;
|
1291 | 2e70f6ef | pbrook | gen_opc_icount[ii] = num_insns; |
1292 | 355fb23d | pbrook | } |
1293 | 2e70f6ef | pbrook | if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) |
1294 | 2e70f6ef | pbrook | gen_io_start(); |
1295 | fdf9b3e8 | bellard | #if 0
|
1296 | fdf9b3e8 | bellard | fprintf(stderr, "Loading opcode at address 0x%08x\n", ctx.pc);
|
1297 | fdf9b3e8 | bellard | fflush(stderr);
|
1298 | fdf9b3e8 | bellard | #endif
|
1299 | fdf9b3e8 | bellard | ctx.opcode = lduw_code(ctx.pc); |
1300 | fdf9b3e8 | bellard | decode_opc(&ctx); |
1301 | 2e70f6ef | pbrook | num_insns++; |
1302 | fdf9b3e8 | bellard | ctx.pc += 2;
|
1303 | fdf9b3e8 | bellard | if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0) |
1304 | fdf9b3e8 | bellard | break;
|
1305 | fdf9b3e8 | bellard | if (env->singlestep_enabled)
|
1306 | fdf9b3e8 | bellard | break;
|
1307 | 2e70f6ef | pbrook | if (num_insns >= max_insns)
|
1308 | 2e70f6ef | pbrook | break;
|
1309 | fdf9b3e8 | bellard | #ifdef SH4_SINGLE_STEP
|
1310 | fdf9b3e8 | bellard | break;
|
1311 | fdf9b3e8 | bellard | #endif
|
1312 | fdf9b3e8 | bellard | } |
1313 | 2e70f6ef | pbrook | if (tb->cflags & CF_LAST_IO)
|
1314 | 2e70f6ef | pbrook | gen_io_end(); |
1315 | fdf9b3e8 | bellard | if (env->singlestep_enabled) {
|
1316 | 823029f9 | ths | gen_op_debug(); |
1317 | 823029f9 | ths | } else {
|
1318 | 823029f9 | ths | switch (ctx.bstate) {
|
1319 | 823029f9 | ths | case BS_STOP:
|
1320 | 823029f9 | ths | /* gen_op_interrupt_restart(); */
|
1321 | 823029f9 | ths | /* fall through */
|
1322 | 823029f9 | ths | case BS_NONE:
|
1323 | 823029f9 | ths | if (ctx.flags) {
|
1324 | 823029f9 | ths | gen_op_store_flags(ctx.flags | DELAY_SLOT_CLEARME); |
1325 | 823029f9 | ths | } |
1326 | 823029f9 | ths | gen_goto_tb(&ctx, 0, ctx.pc);
|
1327 | 823029f9 | ths | break;
|
1328 | 823029f9 | ths | case BS_EXCP:
|
1329 | 823029f9 | ths | /* gen_op_interrupt_restart(); */
|
1330 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
1331 | 823029f9 | ths | break;
|
1332 | 823029f9 | ths | case BS_BRANCH:
|
1333 | 823029f9 | ths | default:
|
1334 | 823029f9 | ths | break;
|
1335 | 823029f9 | ths | } |
1336 | fdf9b3e8 | bellard | } |
1337 | 823029f9 | ths | |
1338 | 2e70f6ef | pbrook | gen_icount_end(tb, num_insns); |
1339 | fdf9b3e8 | bellard | *gen_opc_ptr = INDEX_op_end; |
1340 | 355fb23d | pbrook | if (search_pc) {
|
1341 | 355fb23d | pbrook | i = gen_opc_ptr - gen_opc_buf; |
1342 | 355fb23d | pbrook | ii++; |
1343 | 355fb23d | pbrook | while (ii <= i)
|
1344 | 355fb23d | pbrook | gen_opc_instr_start[ii++] = 0;
|
1345 | 355fb23d | pbrook | } else {
|
1346 | 355fb23d | pbrook | tb->size = ctx.pc - pc_start; |
1347 | 2e70f6ef | pbrook | tb->icount = num_insns; |
1348 | 355fb23d | pbrook | } |
1349 | fdf9b3e8 | bellard | |
1350 | fdf9b3e8 | bellard | #ifdef DEBUG_DISAS
|
1351 | fdf9b3e8 | bellard | #ifdef SH4_DEBUG_DISAS
|
1352 | fdf9b3e8 | bellard | if (loglevel & CPU_LOG_TB_IN_ASM)
|
1353 | fdf9b3e8 | bellard | fprintf(logfile, "\n");
|
1354 | fdf9b3e8 | bellard | #endif
|
1355 | fdf9b3e8 | bellard | if (loglevel & CPU_LOG_TB_IN_ASM) {
|
1356 | fdf9b3e8 | bellard | fprintf(logfile, "IN:\n"); /* , lookup_symbol(pc_start)); */ |
1357 | fdf9b3e8 | bellard | target_disas(logfile, pc_start, ctx.pc - pc_start, 0);
|
1358 | fdf9b3e8 | bellard | fprintf(logfile, "\n");
|
1359 | fdf9b3e8 | bellard | } |
1360 | fdf9b3e8 | bellard | #endif
|
1361 | fdf9b3e8 | bellard | } |
1362 | fdf9b3e8 | bellard | |
1363 | 2cfc5f17 | ths | void gen_intermediate_code(CPUState * env, struct TranslationBlock *tb) |
1364 | fdf9b3e8 | bellard | { |
1365 | 2cfc5f17 | ths | gen_intermediate_code_internal(env, tb, 0);
|
1366 | fdf9b3e8 | bellard | } |
1367 | fdf9b3e8 | bellard | |
1368 | 2cfc5f17 | ths | void gen_intermediate_code_pc(CPUState * env, struct TranslationBlock *tb) |
1369 | fdf9b3e8 | bellard | { |
1370 | 2cfc5f17 | ths | gen_intermediate_code_internal(env, tb, 1);
|
1371 | fdf9b3e8 | bellard | } |
1372 | d2856f1a | aurel32 | |
1373 | d2856f1a | aurel32 | void gen_pc_load(CPUState *env, TranslationBlock *tb,
|
1374 | d2856f1a | aurel32 | unsigned long searched_pc, int pc_pos, void *puc) |
1375 | d2856f1a | aurel32 | { |
1376 | d2856f1a | aurel32 | env->pc = gen_opc_pc[pc_pos]; |
1377 | d2856f1a | aurel32 | env->flags = gen_opc_hflags[pc_pos]; |
1378 | d2856f1a | aurel32 | } |