Revision 7da845b0

b/target-arm/cpu.c
91 91 
        env->aarch64 = 1;
92 92 
#if defined(CONFIG_USER_ONLY)
93 93 
        env->pstate = PSTATE_MODE_EL0t;
94 
        /* Userspace expects access to CTL_EL0 */
95 
        env->cp15.c1_sys |= SCTLR_UCT;
94 96 
#else
95 97 
        env->pstate = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F
96 98 
            | PSTATE_MODE_EL1h;
b/target-arm/cpu.h
166 166 
    /* System control coprocessor (cp15) */
167 167 
    struct {
168 168 
        uint32_t c0_cpuid;
169 
        uint32_t c0_cssel; /* Cache size selection.  */
169 
        uint64_t c0_cssel; /* Cache size selection.  */
170 170 
        uint32_t c1_sys; /* System control register.  */
171 171 
        uint32_t c1_coproc; /* Coprocessor access register.  */
172 172 
        uint32_t c1_xscaleauxcr; /* XScale auxiliary control register.  */
b/target-arm/cpu64.c
45 45 
    set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
46 46 
    set_feature(&cpu->env, ARM_FEATURE_V7MP);
47 47 
    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
48 
    cpu->ctr = 0x80030003; /* 32 byte I and D cacheline size, VIPT icache */
48 49 
}
49 50 
#endif
50 51 

  		












  

    
      b/target-arm/helper.c
    
  






  629
  629
  
    
    { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,


  		





  630
  630
  
    
      .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr),


  		





  631
  631
  
    
      .resetvalue = 0, },


  		





  632
  
  
    
    { .name = "CCSIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,


  		





  
  632
  
    
    { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,


  		





  
  633
  
    
      .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,


  		





  633
  634
  
    
      .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_MIGRATE },


  		





  634
  
  
    
    { .name = "CSSELR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,


  		





  
  635
  
    
    { .name = "CSSELR", .state = ARM_CP_STATE_BOTH,


  		





  
  636
  
    
      .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,


  		





  635
  637
  
    
      .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c0_cssel),


  		





  636
  638
  
    
      .writefn = csselr_write, .resetvalue = 0 },


  		





  637
  639
  
    
    /* Auxiliary ID register: this actually has an IMPDEF value but for now


  		





  ......




  1524
  1526
  
    
    { .name = "FPSR", .state = ARM_CP_STATE_AA64,


  		





  1525
  1527
  
    
      .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4,


  		





  1526
  1528
  
    
      .access = PL0_RW, .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write },


  		





  1527
  
  
    
    /* This claims a 32 byte cacheline size for icache and dcache, VIPT icache.


  		





  1528
  
  
    
     * It will eventually need to have a CPU-specified reset value.


  		





  1529
  
  
    
     */


  		





  1530
  
  
    
    { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64,


  		





  1531
  
  
    
      .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0,


  		





  1532
  
  
    
      .access = PL0_R, .type = ARM_CP_CONST,


  		





  1533
  
  
    
      .resetvalue = 0x80030003 },


  		





  1534
  1529
  
    
    /* Prohibit use of DC ZVA. OPTME: implement DC ZVA and allow its use.


  		





  1535
  1530
  
    
     * For system mode the DZP bit here will need to be computed, not constant.


  		





  1536
  1531
  
    
     */


  		





  ......




  1550
  1545
  
    
    tlb_flush(env, 1);


  		





  1551
  1546
  
    
}


  		





  1552
  1547
  
    

  		





  
  1548
  
    
static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri)


  		





  
  1549
  
    
{


  		





  
  1550
  
    
    /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64,


  		





  
  1551
  
    
     * but the AArch32 CTR has its own reginfo struct)


  		





  
  1552
  
    
     */


  		





  
  1553
  
    
    if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UCT)) {


  		





  
  1554
  
    
        return CP_ACCESS_TRAP;


  		





  
  1555
  
    
    }


  		





  
  1556
  
    
    return CP_ACCESS_OK;


  		





  
  1557
  
    
}


  		





  
  1558
  
    

  		





  1553
  1559
  
    
void register_cp_regs_for_features(ARMCPU *cpu)


  		





  1554
  1560
  
    
{


  		





  1555
  1561
  
    
    /* Register all the coprocessor registers based on feature bits */


  		





  ......




  1634
  1640
  
    
            .raw_writefn = raw_write,


  		





  1635
  1641
  
    
        };


  		





  1636
  1642
  
    
        ARMCPRegInfo clidr = {


  		





  1637
  
  
    
            .name = "CLIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,


  		





  
  1643
  
    
            .name = "CLIDR", .state = ARM_CP_STATE_BOTH,


  		





  
  1644
  
    
            .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,


  		





  1638
  1645
  
    
            .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr


  		





  1639
  1646
  
    
        };


  		





  1640
  1647
  
    
        define_one_arm_cp_reg(cpu, &pmcr);


  		





  ......




  1713
  1720
  
    
            { .name = "CTR",


  		





  1714
  1721
  
    
              .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1,


  		





  1715
  1722
  
    
              .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr },


  		





  
  1723
  
    
            { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64,


  		





  
  1724
  
    
              .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0,


  		





  
  1725
  
    
              .access = PL0_R, .accessfn = ctr_el0_access,


  		





  
  1726
  
    
              .type = ARM_CP_CONST, .resetvalue = cpu->ctr },


  		





  1716
  1727
  
    
            { .name = "TCMTR",


  		





  1717
  1728
  
    
              .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2,


  		





  1718
  1729
  
    
              .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },


  		












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