root / hw / flash.h @ 7e0a9247
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/* NOR flash devices */
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#include "memory.h" |
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typedef struct pflash_t pflash_t; |
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/* pflash_cfi01.c */
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pflash_t *pflash_cfi01_register(hwaddr base, |
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DeviceState *qdev, const char *name, |
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hwaddr size, |
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BlockDriverState *bs, |
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uint32_t sector_len, int nb_blocs, int width, |
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uint16_t id0, uint16_t id1, |
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uint16_t id2, uint16_t id3, int be);
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/* pflash_cfi02.c */
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pflash_t *pflash_cfi02_register(hwaddr base, |
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DeviceState *qdev, const char *name, |
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hwaddr size, |
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BlockDriverState *bs, uint32_t sector_len, |
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int nb_blocs, int nb_mappings, int width, |
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uint16_t id0, uint16_t id1, |
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uint16_t id2, uint16_t id3, |
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uint16_t unlock_addr0, uint16_t unlock_addr1, |
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int be);
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MemoryRegion *pflash_cfi01_get_memory(pflash_t *fl); |
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/* nand.c */
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DeviceState *nand_init(BlockDriverState *bdrv, int manf_id, int chip_id); |
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void nand_setpins(DeviceState *dev, uint8_t cle, uint8_t ale,
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uint8_t ce, uint8_t wp, uint8_t gnd); |
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void nand_getpins(DeviceState *dev, int *rb); |
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void nand_setio(DeviceState *dev, uint32_t value);
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uint32_t nand_getio(DeviceState *dev); |
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uint32_t nand_getbuswidth(DeviceState *dev); |
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#define NAND_MFR_TOSHIBA 0x98 |
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#define NAND_MFR_SAMSUNG 0xec |
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#define NAND_MFR_FUJITSU 0x04 |
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#define NAND_MFR_NATIONAL 0x8f |
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#define NAND_MFR_RENESAS 0x07 |
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#define NAND_MFR_STMICRO 0x20 |
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#define NAND_MFR_HYNIX 0xad |
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#define NAND_MFR_MICRON 0x2c |
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/* onenand.c */
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void *onenand_raw_otp(DeviceState *onenand_device);
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/* ecc.c */
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typedef struct { |
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uint8_t cp; /* Column parity */
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uint16_t lp[2]; /* Line parity */ |
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uint16_t count; |
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} ECCState; |
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uint8_t ecc_digest(ECCState *s, uint8_t sample); |
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void ecc_reset(ECCState *s);
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extern VMStateDescription vmstate_ecc_state;
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