root / hw / pci_host.c @ 7e0a9247
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/*
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* pci_host.c
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*
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* Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
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* VA Linux Systems Japan K.K.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "pci.h" |
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#include "pci_host.h" |
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/* debug PCI */
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//#define DEBUG_PCI
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#ifdef DEBUG_PCI
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#define PCI_DPRINTF(fmt, ...) \
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do { printf("pci_host_data: " fmt , ## __VA_ARGS__); } while (0) |
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#else
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#define PCI_DPRINTF(fmt, ...)
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#endif
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/*
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* PCI address
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* bit 16 - 24: bus number
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* bit 8 - 15: devfun number
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* bit 0 - 7: offset in configuration space of a given pci device
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*/
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/* the helper functio to get a PCIDeice* for a given pci address */
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static inline PCIDevice *pci_dev_find_by_addr(PCIBus *bus, uint32_t addr) |
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{ |
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uint8_t bus_num = addr >> 16;
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uint8_t devfn = addr >> 8;
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return pci_find_device(bus, bus_num, devfn);
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} |
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void pci_host_config_write_common(PCIDevice *pci_dev, uint32_t addr,
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uint32_t limit, uint32_t val, uint32_t len) |
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{ |
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assert(len <= 4);
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pci_dev->config_write(pci_dev, addr, val, MIN(len, limit - addr)); |
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} |
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uint32_t pci_host_config_read_common(PCIDevice *pci_dev, uint32_t addr, |
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uint32_t limit, uint32_t len) |
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{ |
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assert(len <= 4);
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return pci_dev->config_read(pci_dev, addr, MIN(len, limit - addr));
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} |
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void pci_data_write(PCIBus *s, uint32_t addr, uint32_t val, int len) |
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{ |
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PCIDevice *pci_dev = pci_dev_find_by_addr(s, addr); |
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uint32_t config_addr = addr & (PCI_CONFIG_SPACE_SIZE - 1);
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if (!pci_dev) {
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return;
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} |
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PCI_DPRINTF("%s: %s: addr=%02" PRIx32 " val=%08" PRIx32 " len=%d\n", |
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__func__, pci_dev->name, config_addr, val, len); |
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pci_host_config_write_common(pci_dev, config_addr, PCI_CONFIG_SPACE_SIZE, |
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val, len); |
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} |
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uint32_t pci_data_read(PCIBus *s, uint32_t addr, int len)
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{ |
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PCIDevice *pci_dev = pci_dev_find_by_addr(s, addr); |
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uint32_t config_addr = addr & (PCI_CONFIG_SPACE_SIZE - 1);
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uint32_t val; |
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if (!pci_dev) {
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return ~0x0; |
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} |
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val = pci_host_config_read_common(pci_dev, config_addr, |
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PCI_CONFIG_SPACE_SIZE, len); |
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PCI_DPRINTF("%s: %s: addr=%02"PRIx32" val=%08"PRIx32" len=%d\n", |
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__func__, pci_dev->name, config_addr, val, len); |
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return val;
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} |
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static void pci_host_config_write(void *opaque, hwaddr addr, |
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uint64_t val, unsigned len)
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{ |
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PCIHostState *s = opaque; |
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PCI_DPRINTF("%s addr " TARGET_FMT_plx " len %d val %"PRIx64"\n", |
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__func__, addr, len, val); |
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if (addr != 0 || len != 4) { |
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return;
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} |
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s->config_reg = val; |
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} |
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static uint64_t pci_host_config_read(void *opaque, hwaddr addr, |
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unsigned len)
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{ |
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PCIHostState *s = opaque; |
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uint32_t val = s->config_reg; |
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PCI_DPRINTF("%s addr " TARGET_FMT_plx " len %d val %"PRIx32"\n", |
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__func__, addr, len, val); |
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return val;
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} |
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static void pci_host_data_write(void *opaque, hwaddr addr, |
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uint64_t val, unsigned len)
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{ |
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PCIHostState *s = opaque; |
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PCI_DPRINTF("write addr " TARGET_FMT_plx " len %d val %x\n", |
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addr, len, (unsigned)val);
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if (s->config_reg & (1u << 31)) |
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pci_data_write(s->bus, s->config_reg | (addr & 3), val, len);
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} |
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static uint64_t pci_host_data_read(void *opaque, |
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hwaddr addr, unsigned len)
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{ |
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PCIHostState *s = opaque; |
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uint32_t val; |
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if (!(s->config_reg & (1 << 31))) |
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return 0xffffffff; |
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val = pci_data_read(s->bus, s->config_reg | (addr & 3), len);
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PCI_DPRINTF("read addr " TARGET_FMT_plx " len %d val %x\n", |
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addr, len, val); |
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return val;
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} |
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const MemoryRegionOps pci_host_conf_le_ops = {
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.read = pci_host_config_read, |
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.write = pci_host_config_write, |
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.endianness = DEVICE_LITTLE_ENDIAN, |
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}; |
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const MemoryRegionOps pci_host_conf_be_ops = {
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.read = pci_host_config_read, |
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.write = pci_host_config_write, |
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.endianness = DEVICE_BIG_ENDIAN, |
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}; |
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const MemoryRegionOps pci_host_data_le_ops = {
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.read = pci_host_data_read, |
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.write = pci_host_data_write, |
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.endianness = DEVICE_LITTLE_ENDIAN, |
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}; |
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const MemoryRegionOps pci_host_data_be_ops = {
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.read = pci_host_data_read, |
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.write = pci_host_data_write, |
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.endianness = DEVICE_BIG_ENDIAN, |
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}; |
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static const TypeInfo pci_host_type_info = { |
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.name = TYPE_PCI_HOST_BRIDGE, |
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.parent = TYPE_SYS_BUS_DEVICE, |
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.abstract = true,
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.instance_size = sizeof(PCIHostState),
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}; |
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static void pci_host_register_types(void) |
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{ |
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type_register_static(&pci_host_type_info); |
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} |
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type_init(pci_host_register_types) |