root / vl.h @ 7e1543c2
History | View | Annotate | Download (53.7 kB)
1 | fc01f7e7 | bellard | /*
|
---|---|---|---|
2 | fc01f7e7 | bellard | * QEMU System Emulator header
|
3 | fc01f7e7 | bellard | *
|
4 | fc01f7e7 | bellard | * Copyright (c) 2003 Fabrice Bellard
|
5 | fc01f7e7 | bellard | *
|
6 | fc01f7e7 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
|
7 | fc01f7e7 | bellard | * of this software and associated documentation files (the "Software"), to deal
|
8 | fc01f7e7 | bellard | * in the Software without restriction, including without limitation the rights
|
9 | fc01f7e7 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
10 | fc01f7e7 | bellard | * copies of the Software, and to permit persons to whom the Software is
|
11 | fc01f7e7 | bellard | * furnished to do so, subject to the following conditions:
|
12 | fc01f7e7 | bellard | *
|
13 | fc01f7e7 | bellard | * The above copyright notice and this permission notice shall be included in
|
14 | fc01f7e7 | bellard | * all copies or substantial portions of the Software.
|
15 | fc01f7e7 | bellard | *
|
16 | fc01f7e7 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
17 | fc01f7e7 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
18 | fc01f7e7 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
19 | fc01f7e7 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
20 | fc01f7e7 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
21 | fc01f7e7 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
22 | fc01f7e7 | bellard | * THE SOFTWARE.
|
23 | fc01f7e7 | bellard | */
|
24 | fc01f7e7 | bellard | #ifndef VL_H
|
25 | fc01f7e7 | bellard | #define VL_H
|
26 | fc01f7e7 | bellard | |
27 | 67b915a5 | bellard | /* we put basic includes here to avoid repeating them in device drivers */
|
28 | 67b915a5 | bellard | #include <stdlib.h> |
29 | 67b915a5 | bellard | #include <stdio.h> |
30 | 67b915a5 | bellard | #include <stdarg.h> |
31 | 67b915a5 | bellard | #include <string.h> |
32 | 67b915a5 | bellard | #include <inttypes.h> |
33 | 85571bc7 | bellard | #include <limits.h> |
34 | 8a7ddc38 | bellard | #include <time.h> |
35 | 67b915a5 | bellard | #include <ctype.h> |
36 | 67b915a5 | bellard | #include <errno.h> |
37 | 67b915a5 | bellard | #include <unistd.h> |
38 | 67b915a5 | bellard | #include <fcntl.h> |
39 | 7d3505c5 | bellard | #include <sys/stat.h> |
40 | 67b915a5 | bellard | |
41 | 67b915a5 | bellard | #ifndef O_LARGEFILE
|
42 | 67b915a5 | bellard | #define O_LARGEFILE 0 |
43 | 67b915a5 | bellard | #endif
|
44 | 40c3bac3 | bellard | #ifndef O_BINARY
|
45 | 40c3bac3 | bellard | #define O_BINARY 0 |
46 | 40c3bac3 | bellard | #endif
|
47 | 67b915a5 | bellard | |
48 | 71c2fd5c | ths | #ifndef ENOMEDIUM
|
49 | 71c2fd5c | ths | #define ENOMEDIUM ENODEV
|
50 | 71c2fd5c | ths | #endif
|
51 | 2e9671da | ths | |
52 | 67b915a5 | bellard | #ifdef _WIN32
|
53 | a18e524a | bellard | #include <windows.h> |
54 | ac62f715 | pbrook | #define fsync _commit
|
55 | 57d1a2b6 | bellard | #define lseek _lseeki64
|
56 | 57d1a2b6 | bellard | #define ENOTSUP 4096 |
57 | beac80cd | bellard | extern int qemu_ftruncate64(int, int64_t); |
58 | beac80cd | bellard | #define ftruncate qemu_ftruncate64
|
59 | beac80cd | bellard | |
60 | 57d1a2b6 | bellard | |
61 | 57d1a2b6 | bellard | static inline char *realpath(const char *path, char *resolved_path) |
62 | 57d1a2b6 | bellard | { |
63 | 57d1a2b6 | bellard | _fullpath(resolved_path, path, _MAX_PATH); |
64 | 57d1a2b6 | bellard | return resolved_path;
|
65 | 57d1a2b6 | bellard | } |
66 | ec3757de | bellard | |
67 | ec3757de | bellard | #define PRId64 "I64d" |
68 | 26a76461 | bellard | #define PRIx64 "I64x" |
69 | 26a76461 | bellard | #define PRIu64 "I64u" |
70 | 26a76461 | bellard | #define PRIo64 "I64o" |
71 | 67b915a5 | bellard | #endif
|
72 | 8a7ddc38 | bellard | |
73 | ea2384d3 | bellard | #ifdef QEMU_TOOL
|
74 | ea2384d3 | bellard | |
75 | ea2384d3 | bellard | /* we use QEMU_TOOL in the command line tools which do not depend on
|
76 | ea2384d3 | bellard | the target CPU type */
|
77 | ea2384d3 | bellard | #include "config-host.h" |
78 | ea2384d3 | bellard | #include <setjmp.h> |
79 | ea2384d3 | bellard | #include "osdep.h" |
80 | ea2384d3 | bellard | #include "bswap.h" |
81 | ea2384d3 | bellard | |
82 | ea2384d3 | bellard | #else
|
83 | ea2384d3 | bellard | |
84 | 4f209290 | pbrook | #include "audio/audio.h" |
85 | 16f62432 | bellard | #include "cpu.h" |
86 | 16f62432 | bellard | |
87 | ea2384d3 | bellard | #endif /* !defined(QEMU_TOOL) */ |
88 | ea2384d3 | bellard | |
89 | 67b915a5 | bellard | #ifndef glue
|
90 | 67b915a5 | bellard | #define xglue(x, y) x ## y |
91 | 67b915a5 | bellard | #define glue(x, y) xglue(x, y)
|
92 | 67b915a5 | bellard | #define stringify(s) tostring(s)
|
93 | 67b915a5 | bellard | #define tostring(s) #s |
94 | 67b915a5 | bellard | #endif
|
95 | 67b915a5 | bellard | |
96 | 24236869 | bellard | #ifndef MIN
|
97 | 24236869 | bellard | #define MIN(a, b) (((a) < (b)) ? (a) : (b))
|
98 | 24236869 | bellard | #endif
|
99 | 24236869 | bellard | #ifndef MAX
|
100 | 24236869 | bellard | #define MAX(a, b) (((a) > (b)) ? (a) : (b))
|
101 | 24236869 | bellard | #endif
|
102 | 24236869 | bellard | |
103 | 18607dcb | bellard | /* cutils.c */
|
104 | 18607dcb | bellard | void pstrcpy(char *buf, int buf_size, const char *str); |
105 | 18607dcb | bellard | char *pstrcat(char *buf, int buf_size, const char *s); |
106 | 18607dcb | bellard | int strstart(const char *str, const char *val, const char **ptr); |
107 | 18607dcb | bellard | int stristart(const char *str, const char *val, const char **ptr); |
108 | 18607dcb | bellard | |
109 | 33e3963e | bellard | /* vl.c */
|
110 | 80cabfad | bellard | uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c); |
111 | 313aa567 | bellard | |
112 | 80cabfad | bellard | void hw_error(const char *fmt, ...); |
113 | 80cabfad | bellard | |
114 | 80cabfad | bellard | extern const char *bios_dir; |
115 | 80cabfad | bellard | |
116 | 8a7ddc38 | bellard | extern int vm_running; |
117 | c35734b2 | ths | extern const char *qemu_name; |
118 | 8a7ddc38 | bellard | |
119 | 0bd48850 | bellard | typedef struct vm_change_state_entry VMChangeStateEntry; |
120 | 0bd48850 | bellard | typedef void VMChangeStateHandler(void *opaque, int running); |
121 | 8a7ddc38 | bellard | typedef void VMStopHandler(void *opaque, int reason); |
122 | 8a7ddc38 | bellard | |
123 | 0bd48850 | bellard | VMChangeStateEntry *qemu_add_vm_change_state_handler(VMChangeStateHandler *cb, |
124 | 0bd48850 | bellard | void *opaque);
|
125 | 0bd48850 | bellard | void qemu_del_vm_change_state_handler(VMChangeStateEntry *e);
|
126 | 0bd48850 | bellard | |
127 | 8a7ddc38 | bellard | int qemu_add_vm_stop_handler(VMStopHandler *cb, void *opaque); |
128 | 8a7ddc38 | bellard | void qemu_del_vm_stop_handler(VMStopHandler *cb, void *opaque); |
129 | 8a7ddc38 | bellard | |
130 | 8a7ddc38 | bellard | void vm_start(void); |
131 | 8a7ddc38 | bellard | void vm_stop(int reason); |
132 | 8a7ddc38 | bellard | |
133 | bb0c6722 | bellard | typedef void QEMUResetHandler(void *opaque); |
134 | bb0c6722 | bellard | |
135 | bb0c6722 | bellard | void qemu_register_reset(QEMUResetHandler *func, void *opaque); |
136 | bb0c6722 | bellard | void qemu_system_reset_request(void); |
137 | bb0c6722 | bellard | void qemu_system_shutdown_request(void); |
138 | 3475187d | bellard | void qemu_system_powerdown_request(void); |
139 | 3475187d | bellard | #if !defined(TARGET_SPARC)
|
140 | 3475187d | bellard | // Please implement a power failure function to signal the OS
|
141 | 3475187d | bellard | #define qemu_system_powerdown() do{}while(0) |
142 | 3475187d | bellard | #else
|
143 | 3475187d | bellard | void qemu_system_powerdown(void); |
144 | 3475187d | bellard | #endif
|
145 | bb0c6722 | bellard | |
146 | ea2384d3 | bellard | void main_loop_wait(int timeout); |
147 | ea2384d3 | bellard | |
148 | 0ced6589 | bellard | extern int ram_size; |
149 | 0ced6589 | bellard | extern int bios_size; |
150 | ee22c2f7 | bellard | extern int rtc_utc; |
151 | 1f04275e | bellard | extern int cirrus_vga_enabled; |
152 | d34cab9f | ths | extern int vmsvga_enabled; |
153 | 28b9b5af | bellard | extern int graphic_width; |
154 | 28b9b5af | bellard | extern int graphic_height; |
155 | 28b9b5af | bellard | extern int graphic_depth; |
156 | 3d11d0eb | bellard | extern const char *keyboard_layout; |
157 | d993e026 | bellard | extern int kqemu_allowed; |
158 | a09db21f | bellard | extern int win2k_install_hack; |
159 | 3780e197 | ths | extern int alt_grab; |
160 | bb36d470 | bellard | extern int usb_enabled; |
161 | 6a00d601 | bellard | extern int smp_cpus; |
162 | 9467cd46 | balrog | extern int cursor_hide; |
163 | a171fe39 | balrog | extern int graphic_rotate; |
164 | 667accab | ths | extern int no_quit; |
165 | 8e71621f | pbrook | extern int semihosting_enabled; |
166 | 3c07f8e8 | pbrook | extern int autostart; |
167 | 47d5d01a | ths | extern const char *bootp_filename; |
168 | 0ced6589 | bellard | |
169 | 9ae02555 | ths | #define MAX_OPTION_ROMS 16 |
170 | 9ae02555 | ths | extern const char *option_rom[MAX_OPTION_ROMS]; |
171 | 9ae02555 | ths | extern int nb_option_roms; |
172 | 9ae02555 | ths | |
173 | 66508601 | blueswir1 | #ifdef TARGET_SPARC
|
174 | 66508601 | blueswir1 | #define MAX_PROM_ENVS 128 |
175 | 66508601 | blueswir1 | extern const char *prom_envs[MAX_PROM_ENVS]; |
176 | 66508601 | blueswir1 | extern unsigned int nb_prom_envs; |
177 | 66508601 | blueswir1 | #endif
|
178 | 66508601 | blueswir1 | |
179 | 0ced6589 | bellard | /* XXX: make it dynamic */
|
180 | 970ac5a3 | bellard | #define MAX_BIOS_SIZE (4 * 1024 * 1024) |
181 | 75956cf0 | pbrook | #if defined (TARGET_PPC) || defined (TARGET_SPARC64)
|
182 | d5295253 | bellard | #define BIOS_SIZE ((512 + 32) * 1024) |
183 | 6af0bf9c | bellard | #elif defined(TARGET_MIPS)
|
184 | 567daa49 | ths | #define BIOS_SIZE (4 * 1024 * 1024) |
185 | 0ced6589 | bellard | #endif
|
186 | aaaa7df6 | bellard | |
187 | 63066f4f | bellard | /* keyboard/mouse support */
|
188 | 63066f4f | bellard | |
189 | 63066f4f | bellard | #define MOUSE_EVENT_LBUTTON 0x01 |
190 | 63066f4f | bellard | #define MOUSE_EVENT_RBUTTON 0x02 |
191 | 63066f4f | bellard | #define MOUSE_EVENT_MBUTTON 0x04 |
192 | 63066f4f | bellard | |
193 | 63066f4f | bellard | typedef void QEMUPutKBDEvent(void *opaque, int keycode); |
194 | 63066f4f | bellard | typedef void QEMUPutMouseEvent(void *opaque, int dx, int dy, int dz, int buttons_state); |
195 | 63066f4f | bellard | |
196 | 455204eb | ths | typedef struct QEMUPutMouseEntry { |
197 | 455204eb | ths | QEMUPutMouseEvent *qemu_put_mouse_event; |
198 | 455204eb | ths | void *qemu_put_mouse_event_opaque;
|
199 | 455204eb | ths | int qemu_put_mouse_event_absolute;
|
200 | 455204eb | ths | char *qemu_put_mouse_event_name;
|
201 | 455204eb | ths | |
202 | 455204eb | ths | /* used internally by qemu for handling mice */
|
203 | 455204eb | ths | struct QEMUPutMouseEntry *next;
|
204 | 455204eb | ths | } QEMUPutMouseEntry; |
205 | 455204eb | ths | |
206 | 63066f4f | bellard | void qemu_add_kbd_event_handler(QEMUPutKBDEvent *func, void *opaque); |
207 | 455204eb | ths | QEMUPutMouseEntry *qemu_add_mouse_event_handler(QEMUPutMouseEvent *func, |
208 | 455204eb | ths | void *opaque, int absolute, |
209 | 455204eb | ths | const char *name); |
210 | 455204eb | ths | void qemu_remove_mouse_event_handler(QEMUPutMouseEntry *entry);
|
211 | 63066f4f | bellard | |
212 | 63066f4f | bellard | void kbd_put_keycode(int keycode); |
213 | 63066f4f | bellard | void kbd_mouse_event(int dx, int dy, int dz, int buttons_state); |
214 | 09b26c5e | bellard | int kbd_mouse_is_absolute(void); |
215 | 63066f4f | bellard | |
216 | 455204eb | ths | void do_info_mice(void); |
217 | 455204eb | ths | void do_mouse_set(int index); |
218 | 455204eb | ths | |
219 | 82c643ff | bellard | /* keysym is a unicode code except for special keys (see QEMU_KEY_xxx
|
220 | 82c643ff | bellard | constants) */
|
221 | 82c643ff | bellard | #define QEMU_KEY_ESC1(c) ((c) | 0xe100) |
222 | 82c643ff | bellard | #define QEMU_KEY_BACKSPACE 0x007f |
223 | 82c643ff | bellard | #define QEMU_KEY_UP QEMU_KEY_ESC1('A') |
224 | 82c643ff | bellard | #define QEMU_KEY_DOWN QEMU_KEY_ESC1('B') |
225 | 82c643ff | bellard | #define QEMU_KEY_RIGHT QEMU_KEY_ESC1('C') |
226 | 82c643ff | bellard | #define QEMU_KEY_LEFT QEMU_KEY_ESC1('D') |
227 | 82c643ff | bellard | #define QEMU_KEY_HOME QEMU_KEY_ESC1(1) |
228 | 82c643ff | bellard | #define QEMU_KEY_END QEMU_KEY_ESC1(4) |
229 | 82c643ff | bellard | #define QEMU_KEY_PAGEUP QEMU_KEY_ESC1(5) |
230 | 82c643ff | bellard | #define QEMU_KEY_PAGEDOWN QEMU_KEY_ESC1(6) |
231 | 82c643ff | bellard | #define QEMU_KEY_DELETE QEMU_KEY_ESC1(3) |
232 | 82c643ff | bellard | |
233 | 82c643ff | bellard | #define QEMU_KEY_CTRL_UP 0xe400 |
234 | 82c643ff | bellard | #define QEMU_KEY_CTRL_DOWN 0xe401 |
235 | 82c643ff | bellard | #define QEMU_KEY_CTRL_LEFT 0xe402 |
236 | 82c643ff | bellard | #define QEMU_KEY_CTRL_RIGHT 0xe403 |
237 | 82c643ff | bellard | #define QEMU_KEY_CTRL_HOME 0xe404 |
238 | 82c643ff | bellard | #define QEMU_KEY_CTRL_END 0xe405 |
239 | 82c643ff | bellard | #define QEMU_KEY_CTRL_PAGEUP 0xe406 |
240 | 82c643ff | bellard | #define QEMU_KEY_CTRL_PAGEDOWN 0xe407 |
241 | 82c643ff | bellard | |
242 | 82c643ff | bellard | void kbd_put_keysym(int keysym); |
243 | 82c643ff | bellard | |
244 | c20709aa | bellard | /* async I/O support */
|
245 | c20709aa | bellard | |
246 | c20709aa | bellard | typedef void IOReadHandler(void *opaque, const uint8_t *buf, int size); |
247 | c20709aa | bellard | typedef int IOCanRWHandler(void *opaque); |
248 | 7c9d8e07 | bellard | typedef void IOHandler(void *opaque); |
249 | c20709aa | bellard | |
250 | 7c9d8e07 | bellard | int qemu_set_fd_handler2(int fd, |
251 | 7c9d8e07 | bellard | IOCanRWHandler *fd_read_poll, |
252 | 7c9d8e07 | bellard | IOHandler *fd_read, |
253 | 7c9d8e07 | bellard | IOHandler *fd_write, |
254 | 7c9d8e07 | bellard | void *opaque);
|
255 | 7c9d8e07 | bellard | int qemu_set_fd_handler(int fd, |
256 | 7c9d8e07 | bellard | IOHandler *fd_read, |
257 | 7c9d8e07 | bellard | IOHandler *fd_write, |
258 | 7c9d8e07 | bellard | void *opaque);
|
259 | c20709aa | bellard | |
260 | f331110f | bellard | /* Polling handling */
|
261 | f331110f | bellard | |
262 | f331110f | bellard | /* return TRUE if no sleep should be done afterwards */
|
263 | f331110f | bellard | typedef int PollingFunc(void *opaque); |
264 | f331110f | bellard | |
265 | f331110f | bellard | int qemu_add_polling_cb(PollingFunc *func, void *opaque); |
266 | f331110f | bellard | void qemu_del_polling_cb(PollingFunc *func, void *opaque); |
267 | f331110f | bellard | |
268 | a18e524a | bellard | #ifdef _WIN32
|
269 | a18e524a | bellard | /* Wait objects handling */
|
270 | a18e524a | bellard | typedef void WaitObjectFunc(void *opaque); |
271 | a18e524a | bellard | |
272 | a18e524a | bellard | int qemu_add_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque); |
273 | a18e524a | bellard | void qemu_del_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque); |
274 | a18e524a | bellard | #endif
|
275 | a18e524a | bellard | |
276 | 86e94dea | ths | typedef struct QEMUBH QEMUBH; |
277 | 86e94dea | ths | |
278 | 82c643ff | bellard | /* character device */
|
279 | 82c643ff | bellard | |
280 | 82c643ff | bellard | #define CHR_EVENT_BREAK 0 /* serial break char */ |
281 | ea2384d3 | bellard | #define CHR_EVENT_FOCUS 1 /* focus to this terminal (modal input needed) */ |
282 | 86e94dea | ths | #define CHR_EVENT_RESET 2 /* new connection established */ |
283 | 2122c51a | bellard | |
284 | 2122c51a | bellard | |
285 | 2122c51a | bellard | #define CHR_IOCTL_SERIAL_SET_PARAMS 1 |
286 | 2122c51a | bellard | typedef struct { |
287 | 2122c51a | bellard | int speed;
|
288 | 2122c51a | bellard | int parity;
|
289 | 2122c51a | bellard | int data_bits;
|
290 | 2122c51a | bellard | int stop_bits;
|
291 | 2122c51a | bellard | } QEMUSerialSetParams; |
292 | 2122c51a | bellard | |
293 | 2122c51a | bellard | #define CHR_IOCTL_SERIAL_SET_BREAK 2 |
294 | 2122c51a | bellard | |
295 | 2122c51a | bellard | #define CHR_IOCTL_PP_READ_DATA 3 |
296 | 2122c51a | bellard | #define CHR_IOCTL_PP_WRITE_DATA 4 |
297 | 2122c51a | bellard | #define CHR_IOCTL_PP_READ_CONTROL 5 |
298 | 2122c51a | bellard | #define CHR_IOCTL_PP_WRITE_CONTROL 6 |
299 | 2122c51a | bellard | #define CHR_IOCTL_PP_READ_STATUS 7 |
300 | 5867c88a | ths | #define CHR_IOCTL_PP_EPP_READ_ADDR 8 |
301 | 5867c88a | ths | #define CHR_IOCTL_PP_EPP_READ 9 |
302 | 5867c88a | ths | #define CHR_IOCTL_PP_EPP_WRITE_ADDR 10 |
303 | 5867c88a | ths | #define CHR_IOCTL_PP_EPP_WRITE 11 |
304 | 2122c51a | bellard | |
305 | 82c643ff | bellard | typedef void IOEventHandler(void *opaque, int event); |
306 | 82c643ff | bellard | |
307 | 82c643ff | bellard | typedef struct CharDriverState { |
308 | 82c643ff | bellard | int (*chr_write)(struct CharDriverState *s, const uint8_t *buf, int len); |
309 | e5b0bc44 | pbrook | void (*chr_update_read_handler)(struct CharDriverState *s); |
310 | 2122c51a | bellard | int (*chr_ioctl)(struct CharDriverState *s, int cmd, void *arg); |
311 | 82c643ff | bellard | IOEventHandler *chr_event; |
312 | e5b0bc44 | pbrook | IOCanRWHandler *chr_can_read; |
313 | e5b0bc44 | pbrook | IOReadHandler *chr_read; |
314 | e5b0bc44 | pbrook | void *handler_opaque;
|
315 | eb45f5fe | bellard | void (*chr_send_event)(struct CharDriverState *chr, int event); |
316 | f331110f | bellard | void (*chr_close)(struct CharDriverState *chr); |
317 | 82c643ff | bellard | void *opaque;
|
318 | 20d8a3ed | ths | int focus;
|
319 | 86e94dea | ths | QEMUBH *bh; |
320 | 82c643ff | bellard | } CharDriverState; |
321 | 82c643ff | bellard | |
322 | 5856de80 | ths | CharDriverState *qemu_chr_open(const char *filename); |
323 | 82c643ff | bellard | void qemu_chr_printf(CharDriverState *s, const char *fmt, ...); |
324 | 82c643ff | bellard | int qemu_chr_write(CharDriverState *s, const uint8_t *buf, int len); |
325 | ea2384d3 | bellard | void qemu_chr_send_event(CharDriverState *s, int event); |
326 | e5b0bc44 | pbrook | void qemu_chr_add_handlers(CharDriverState *s,
|
327 | e5b0bc44 | pbrook | IOCanRWHandler *fd_can_read, |
328 | e5b0bc44 | pbrook | IOReadHandler *fd_read, |
329 | e5b0bc44 | pbrook | IOEventHandler *fd_event, |
330 | e5b0bc44 | pbrook | void *opaque);
|
331 | 2122c51a | bellard | int qemu_chr_ioctl(CharDriverState *s, int cmd, void *arg); |
332 | 86e94dea | ths | void qemu_chr_reset(CharDriverState *s);
|
333 | e5b0bc44 | pbrook | int qemu_chr_can_read(CharDriverState *s);
|
334 | e5b0bc44 | pbrook | void qemu_chr_read(CharDriverState *s, uint8_t *buf, int len); |
335 | f8d179e3 | bellard | |
336 | 82c643ff | bellard | /* consoles */
|
337 | 82c643ff | bellard | |
338 | 82c643ff | bellard | typedef struct DisplayState DisplayState; |
339 | 82c643ff | bellard | typedef struct TextConsole TextConsole; |
340 | 82c643ff | bellard | |
341 | 95219897 | pbrook | typedef void (*vga_hw_update_ptr)(void *); |
342 | 95219897 | pbrook | typedef void (*vga_hw_invalidate_ptr)(void *); |
343 | 95219897 | pbrook | typedef void (*vga_hw_screen_dump_ptr)(void *, const char *); |
344 | 95219897 | pbrook | |
345 | 95219897 | pbrook | TextConsole *graphic_console_init(DisplayState *ds, vga_hw_update_ptr update, |
346 | 95219897 | pbrook | vga_hw_invalidate_ptr invalidate, |
347 | 95219897 | pbrook | vga_hw_screen_dump_ptr screen_dump, |
348 | 95219897 | pbrook | void *opaque);
|
349 | 95219897 | pbrook | void vga_hw_update(void); |
350 | 95219897 | pbrook | void vga_hw_invalidate(void); |
351 | 95219897 | pbrook | void vga_hw_screen_dump(const char *filename); |
352 | 95219897 | pbrook | |
353 | 95219897 | pbrook | int is_graphic_console(void); |
354 | 82c643ff | bellard | CharDriverState *text_console_init(DisplayState *ds); |
355 | 82c643ff | bellard | void console_select(unsigned int index); |
356 | 82c643ff | bellard | |
357 | 8d11df9e | bellard | /* serial ports */
|
358 | 8d11df9e | bellard | |
359 | 8d11df9e | bellard | #define MAX_SERIAL_PORTS 4 |
360 | 8d11df9e | bellard | |
361 | 8d11df9e | bellard | extern CharDriverState *serial_hds[MAX_SERIAL_PORTS];
|
362 | 8d11df9e | bellard | |
363 | 6508fe59 | bellard | /* parallel ports */
|
364 | 6508fe59 | bellard | |
365 | 6508fe59 | bellard | #define MAX_PARALLEL_PORTS 3 |
366 | 6508fe59 | bellard | |
367 | 6508fe59 | bellard | extern CharDriverState *parallel_hds[MAX_PARALLEL_PORTS];
|
368 | 6508fe59 | bellard | |
369 | 5867c88a | ths | struct ParallelIOArg {
|
370 | 5867c88a | ths | void *buffer;
|
371 | 5867c88a | ths | int count;
|
372 | 5867c88a | ths | }; |
373 | 5867c88a | ths | |
374 | 7c9d8e07 | bellard | /* VLANs support */
|
375 | 7c9d8e07 | bellard | |
376 | 7c9d8e07 | bellard | typedef struct VLANClientState VLANClientState; |
377 | 7c9d8e07 | bellard | |
378 | 7c9d8e07 | bellard | struct VLANClientState {
|
379 | 7c9d8e07 | bellard | IOReadHandler *fd_read; |
380 | d861b05e | pbrook | /* Packets may still be sent if this returns zero. It's used to
|
381 | d861b05e | pbrook | rate-limit the slirp code. */
|
382 | d861b05e | pbrook | IOCanRWHandler *fd_can_read; |
383 | 7c9d8e07 | bellard | void *opaque;
|
384 | 7c9d8e07 | bellard | struct VLANClientState *next;
|
385 | 7c9d8e07 | bellard | struct VLANState *vlan;
|
386 | 7c9d8e07 | bellard | char info_str[256]; |
387 | 7c9d8e07 | bellard | }; |
388 | 7c9d8e07 | bellard | |
389 | 7c9d8e07 | bellard | typedef struct VLANState { |
390 | 7c9d8e07 | bellard | int id;
|
391 | 7c9d8e07 | bellard | VLANClientState *first_client; |
392 | 7c9d8e07 | bellard | struct VLANState *next;
|
393 | 833c7174 | blueswir1 | unsigned int nb_guest_devs, nb_host_devs; |
394 | 7c9d8e07 | bellard | } VLANState; |
395 | 7c9d8e07 | bellard | |
396 | 7c9d8e07 | bellard | VLANState *qemu_find_vlan(int id);
|
397 | 7c9d8e07 | bellard | VLANClientState *qemu_new_vlan_client(VLANState *vlan, |
398 | d861b05e | pbrook | IOReadHandler *fd_read, |
399 | d861b05e | pbrook | IOCanRWHandler *fd_can_read, |
400 | d861b05e | pbrook | void *opaque);
|
401 | d861b05e | pbrook | int qemu_can_send_packet(VLANClientState *vc);
|
402 | 7c9d8e07 | bellard | void qemu_send_packet(VLANClientState *vc, const uint8_t *buf, int size); |
403 | d861b05e | pbrook | void qemu_handler_true(void *opaque); |
404 | 7c9d8e07 | bellard | |
405 | 7c9d8e07 | bellard | void do_info_network(void); |
406 | 7c9d8e07 | bellard | |
407 | 7fb843f8 | bellard | /* TAP win32 */
|
408 | 7fb843f8 | bellard | int tap_win32_init(VLANState *vlan, const char *ifname); |
409 | 7fb843f8 | bellard | |
410 | 7c9d8e07 | bellard | /* NIC info */
|
411 | c4b1fcc0 | bellard | |
412 | c4b1fcc0 | bellard | #define MAX_NICS 8 |
413 | c4b1fcc0 | bellard | |
414 | 7c9d8e07 | bellard | typedef struct NICInfo { |
415 | c4b1fcc0 | bellard | uint8_t macaddr[6];
|
416 | a41b2ff2 | pbrook | const char *model; |
417 | 7c9d8e07 | bellard | VLANState *vlan; |
418 | 7c9d8e07 | bellard | } NICInfo; |
419 | c4b1fcc0 | bellard | |
420 | c4b1fcc0 | bellard | extern int nb_nics; |
421 | 7c9d8e07 | bellard | extern NICInfo nd_table[MAX_NICS];
|
422 | 8a7ddc38 | bellard | |
423 | 8a7ddc38 | bellard | /* timers */
|
424 | 8a7ddc38 | bellard | |
425 | 8a7ddc38 | bellard | typedef struct QEMUClock QEMUClock; |
426 | 8a7ddc38 | bellard | typedef struct QEMUTimer QEMUTimer; |
427 | 8a7ddc38 | bellard | typedef void QEMUTimerCB(void *opaque); |
428 | 8a7ddc38 | bellard | |
429 | 8a7ddc38 | bellard | /* The real time clock should be used only for stuff which does not
|
430 | 8a7ddc38 | bellard | change the virtual machine state, as it is run even if the virtual
|
431 | 69b91039 | bellard | machine is stopped. The real time clock has a frequency of 1000
|
432 | 8a7ddc38 | bellard | Hz. */
|
433 | 8a7ddc38 | bellard | extern QEMUClock *rt_clock;
|
434 | 8a7ddc38 | bellard | |
435 | e80cfcfc | bellard | /* The virtual clock is only run during the emulation. It is stopped
|
436 | 8a7ddc38 | bellard | when the virtual machine is stopped. Virtual timers use a high
|
437 | 8a7ddc38 | bellard | precision clock, usually cpu cycles (use ticks_per_sec). */
|
438 | 8a7ddc38 | bellard | extern QEMUClock *vm_clock;
|
439 | 8a7ddc38 | bellard | |
440 | 8a7ddc38 | bellard | int64_t qemu_get_clock(QEMUClock *clock); |
441 | 8a7ddc38 | bellard | |
442 | 8a7ddc38 | bellard | QEMUTimer *qemu_new_timer(QEMUClock *clock, QEMUTimerCB *cb, void *opaque);
|
443 | 8a7ddc38 | bellard | void qemu_free_timer(QEMUTimer *ts);
|
444 | 8a7ddc38 | bellard | void qemu_del_timer(QEMUTimer *ts);
|
445 | 8a7ddc38 | bellard | void qemu_mod_timer(QEMUTimer *ts, int64_t expire_time);
|
446 | 8a7ddc38 | bellard | int qemu_timer_pending(QEMUTimer *ts);
|
447 | 8a7ddc38 | bellard | |
448 | 8a7ddc38 | bellard | extern int64_t ticks_per_sec;
|
449 | 8a7ddc38 | bellard | extern int pit_min_timer_count; |
450 | 8a7ddc38 | bellard | |
451 | 1dce7c3c | bellard | int64_t cpu_get_ticks(void);
|
452 | 8a7ddc38 | bellard | void cpu_enable_ticks(void); |
453 | 8a7ddc38 | bellard | void cpu_disable_ticks(void); |
454 | 8a7ddc38 | bellard | |
455 | 8a7ddc38 | bellard | /* VM Load/Save */
|
456 | 8a7ddc38 | bellard | |
457 | faea38e7 | bellard | typedef struct QEMUFile QEMUFile; |
458 | 8a7ddc38 | bellard | |
459 | faea38e7 | bellard | QEMUFile *qemu_fopen(const char *filename, const char *mode); |
460 | faea38e7 | bellard | void qemu_fflush(QEMUFile *f);
|
461 | faea38e7 | bellard | void qemu_fclose(QEMUFile *f);
|
462 | 8a7ddc38 | bellard | void qemu_put_buffer(QEMUFile *f, const uint8_t *buf, int size); |
463 | 8a7ddc38 | bellard | void qemu_put_byte(QEMUFile *f, int v); |
464 | 8a7ddc38 | bellard | void qemu_put_be16(QEMUFile *f, unsigned int v); |
465 | 8a7ddc38 | bellard | void qemu_put_be32(QEMUFile *f, unsigned int v); |
466 | 8a7ddc38 | bellard | void qemu_put_be64(QEMUFile *f, uint64_t v);
|
467 | 8a7ddc38 | bellard | int qemu_get_buffer(QEMUFile *f, uint8_t *buf, int size); |
468 | 8a7ddc38 | bellard | int qemu_get_byte(QEMUFile *f);
|
469 | 8a7ddc38 | bellard | unsigned int qemu_get_be16(QEMUFile *f); |
470 | 8a7ddc38 | bellard | unsigned int qemu_get_be32(QEMUFile *f); |
471 | 8a7ddc38 | bellard | uint64_t qemu_get_be64(QEMUFile *f); |
472 | 8a7ddc38 | bellard | |
473 | 8a7ddc38 | bellard | static inline void qemu_put_be64s(QEMUFile *f, const uint64_t *pv) |
474 | 8a7ddc38 | bellard | { |
475 | 8a7ddc38 | bellard | qemu_put_be64(f, *pv); |
476 | 8a7ddc38 | bellard | } |
477 | 8a7ddc38 | bellard | |
478 | 8a7ddc38 | bellard | static inline void qemu_put_be32s(QEMUFile *f, const uint32_t *pv) |
479 | 8a7ddc38 | bellard | { |
480 | 8a7ddc38 | bellard | qemu_put_be32(f, *pv); |
481 | 8a7ddc38 | bellard | } |
482 | 8a7ddc38 | bellard | |
483 | 8a7ddc38 | bellard | static inline void qemu_put_be16s(QEMUFile *f, const uint16_t *pv) |
484 | 8a7ddc38 | bellard | { |
485 | 8a7ddc38 | bellard | qemu_put_be16(f, *pv); |
486 | 8a7ddc38 | bellard | } |
487 | 8a7ddc38 | bellard | |
488 | 8a7ddc38 | bellard | static inline void qemu_put_8s(QEMUFile *f, const uint8_t *pv) |
489 | 8a7ddc38 | bellard | { |
490 | 8a7ddc38 | bellard | qemu_put_byte(f, *pv); |
491 | 8a7ddc38 | bellard | } |
492 | 8a7ddc38 | bellard | |
493 | 8a7ddc38 | bellard | static inline void qemu_get_be64s(QEMUFile *f, uint64_t *pv) |
494 | 8a7ddc38 | bellard | { |
495 | 8a7ddc38 | bellard | *pv = qemu_get_be64(f); |
496 | 8a7ddc38 | bellard | } |
497 | 8a7ddc38 | bellard | |
498 | 8a7ddc38 | bellard | static inline void qemu_get_be32s(QEMUFile *f, uint32_t *pv) |
499 | 8a7ddc38 | bellard | { |
500 | 8a7ddc38 | bellard | *pv = qemu_get_be32(f); |
501 | 8a7ddc38 | bellard | } |
502 | 8a7ddc38 | bellard | |
503 | 8a7ddc38 | bellard | static inline void qemu_get_be16s(QEMUFile *f, uint16_t *pv) |
504 | 8a7ddc38 | bellard | { |
505 | 8a7ddc38 | bellard | *pv = qemu_get_be16(f); |
506 | 8a7ddc38 | bellard | } |
507 | 8a7ddc38 | bellard | |
508 | 8a7ddc38 | bellard | static inline void qemu_get_8s(QEMUFile *f, uint8_t *pv) |
509 | 8a7ddc38 | bellard | { |
510 | 8a7ddc38 | bellard | *pv = qemu_get_byte(f); |
511 | 8a7ddc38 | bellard | } |
512 | 8a7ddc38 | bellard | |
513 | c27004ec | bellard | #if TARGET_LONG_BITS == 64 |
514 | c27004ec | bellard | #define qemu_put_betl qemu_put_be64
|
515 | c27004ec | bellard | #define qemu_get_betl qemu_get_be64
|
516 | c27004ec | bellard | #define qemu_put_betls qemu_put_be64s
|
517 | c27004ec | bellard | #define qemu_get_betls qemu_get_be64s
|
518 | c27004ec | bellard | #else
|
519 | c27004ec | bellard | #define qemu_put_betl qemu_put_be32
|
520 | c27004ec | bellard | #define qemu_get_betl qemu_get_be32
|
521 | c27004ec | bellard | #define qemu_put_betls qemu_put_be32s
|
522 | c27004ec | bellard | #define qemu_get_betls qemu_get_be32s
|
523 | c27004ec | bellard | #endif
|
524 | c27004ec | bellard | |
525 | 8a7ddc38 | bellard | int64_t qemu_ftell(QEMUFile *f); |
526 | 8a7ddc38 | bellard | int64_t qemu_fseek(QEMUFile *f, int64_t pos, int whence);
|
527 | 8a7ddc38 | bellard | |
528 | 8a7ddc38 | bellard | typedef void SaveStateHandler(QEMUFile *f, void *opaque); |
529 | 8a7ddc38 | bellard | typedef int LoadStateHandler(QEMUFile *f, void *opaque, int version_id); |
530 | 8a7ddc38 | bellard | |
531 | 8a7ddc38 | bellard | int register_savevm(const char *idstr, |
532 | 8a7ddc38 | bellard | int instance_id,
|
533 | 8a7ddc38 | bellard | int version_id,
|
534 | 8a7ddc38 | bellard | SaveStateHandler *save_state, |
535 | 8a7ddc38 | bellard | LoadStateHandler *load_state, |
536 | 8a7ddc38 | bellard | void *opaque);
|
537 | 8a7ddc38 | bellard | void qemu_get_timer(QEMUFile *f, QEMUTimer *ts);
|
538 | 8a7ddc38 | bellard | void qemu_put_timer(QEMUFile *f, QEMUTimer *ts);
|
539 | c4b1fcc0 | bellard | |
540 | 6a00d601 | bellard | void cpu_save(QEMUFile *f, void *opaque); |
541 | 6a00d601 | bellard | int cpu_load(QEMUFile *f, void *opaque, int version_id); |
542 | 6a00d601 | bellard | |
543 | faea38e7 | bellard | void do_savevm(const char *name); |
544 | faea38e7 | bellard | void do_loadvm(const char *name); |
545 | faea38e7 | bellard | void do_delvm(const char *name); |
546 | faea38e7 | bellard | void do_info_snapshots(void); |
547 | faea38e7 | bellard | |
548 | 83f64091 | bellard | /* bottom halves */
|
549 | 83f64091 | bellard | typedef void QEMUBHFunc(void *opaque); |
550 | 83f64091 | bellard | |
551 | 83f64091 | bellard | QEMUBH *qemu_bh_new(QEMUBHFunc *cb, void *opaque);
|
552 | 83f64091 | bellard | void qemu_bh_schedule(QEMUBH *bh);
|
553 | 83f64091 | bellard | void qemu_bh_cancel(QEMUBH *bh);
|
554 | 83f64091 | bellard | void qemu_bh_delete(QEMUBH *bh);
|
555 | 6eb5733a | bellard | int qemu_bh_poll(void); |
556 | 83f64091 | bellard | |
557 | fc01f7e7 | bellard | /* block.c */
|
558 | fc01f7e7 | bellard | typedef struct BlockDriverState BlockDriverState; |
559 | ea2384d3 | bellard | typedef struct BlockDriver BlockDriver; |
560 | ea2384d3 | bellard | |
561 | ea2384d3 | bellard | extern BlockDriver bdrv_raw;
|
562 | 19cb3738 | bellard | extern BlockDriver bdrv_host_device;
|
563 | ea2384d3 | bellard | extern BlockDriver bdrv_cow;
|
564 | ea2384d3 | bellard | extern BlockDriver bdrv_qcow;
|
565 | ea2384d3 | bellard | extern BlockDriver bdrv_vmdk;
|
566 | 3c56521b | bellard | extern BlockDriver bdrv_cloop;
|
567 | 585d0ed9 | bellard | extern BlockDriver bdrv_dmg;
|
568 | a8753c34 | bellard | extern BlockDriver bdrv_bochs;
|
569 | 6a0f9e82 | bellard | extern BlockDriver bdrv_vpc;
|
570 | de167e41 | bellard | extern BlockDriver bdrv_vvfat;
|
571 | faea38e7 | bellard | extern BlockDriver bdrv_qcow2;
|
572 | faea38e7 | bellard | |
573 | faea38e7 | bellard | typedef struct BlockDriverInfo { |
574 | faea38e7 | bellard | /* in bytes, 0 if irrelevant */
|
575 | faea38e7 | bellard | int cluster_size;
|
576 | faea38e7 | bellard | /* offset at which the VM state can be saved (0 if not possible) */
|
577 | faea38e7 | bellard | int64_t vm_state_offset; |
578 | faea38e7 | bellard | } BlockDriverInfo; |
579 | faea38e7 | bellard | |
580 | faea38e7 | bellard | typedef struct QEMUSnapshotInfo { |
581 | faea38e7 | bellard | char id_str[128]; /* unique snapshot id */ |
582 | faea38e7 | bellard | /* the following fields are informative. They are not needed for
|
583 | faea38e7 | bellard | the consistency of the snapshot */
|
584 | faea38e7 | bellard | char name[256]; /* user choosen name */ |
585 | faea38e7 | bellard | uint32_t vm_state_size; /* VM state info size */
|
586 | faea38e7 | bellard | uint32_t date_sec; /* UTC date of the snapshot */
|
587 | faea38e7 | bellard | uint32_t date_nsec; |
588 | faea38e7 | bellard | uint64_t vm_clock_nsec; /* VM clock relative to boot */
|
589 | faea38e7 | bellard | } QEMUSnapshotInfo; |
590 | ea2384d3 | bellard | |
591 | 83f64091 | bellard | #define BDRV_O_RDONLY 0x0000 |
592 | 83f64091 | bellard | #define BDRV_O_RDWR 0x0002 |
593 | 83f64091 | bellard | #define BDRV_O_ACCESS 0x0003 |
594 | 83f64091 | bellard | #define BDRV_O_CREAT 0x0004 /* create an empty file */ |
595 | 83f64091 | bellard | #define BDRV_O_SNAPSHOT 0x0008 /* open the file read only and save writes in a snapshot */ |
596 | 83f64091 | bellard | #define BDRV_O_FILE 0x0010 /* open as a raw file (do not try to |
597 | 83f64091 | bellard | use a disk image format on top of
|
598 | 83f64091 | bellard | it (default for
|
599 | 83f64091 | bellard | bdrv_file_open()) */
|
600 | 83f64091 | bellard | |
601 | ea2384d3 | bellard | void bdrv_init(void); |
602 | ea2384d3 | bellard | BlockDriver *bdrv_find_format(const char *format_name); |
603 | ea2384d3 | bellard | int bdrv_create(BlockDriver *drv,
|
604 | ea2384d3 | bellard | const char *filename, int64_t size_in_sectors, |
605 | ea2384d3 | bellard | const char *backing_file, int flags); |
606 | c4b1fcc0 | bellard | BlockDriverState *bdrv_new(const char *device_name); |
607 | c4b1fcc0 | bellard | void bdrv_delete(BlockDriverState *bs);
|
608 | 83f64091 | bellard | int bdrv_file_open(BlockDriverState **pbs, const char *filename, int flags); |
609 | 83f64091 | bellard | int bdrv_open(BlockDriverState *bs, const char *filename, int flags); |
610 | 83f64091 | bellard | int bdrv_open2(BlockDriverState *bs, const char *filename, int flags, |
611 | ea2384d3 | bellard | BlockDriver *drv); |
612 | fc01f7e7 | bellard | void bdrv_close(BlockDriverState *bs);
|
613 | fc01f7e7 | bellard | int bdrv_read(BlockDriverState *bs, int64_t sector_num,
|
614 | fc01f7e7 | bellard | uint8_t *buf, int nb_sectors);
|
615 | fc01f7e7 | bellard | int bdrv_write(BlockDriverState *bs, int64_t sector_num,
|
616 | fc01f7e7 | bellard | const uint8_t *buf, int nb_sectors); |
617 | 83f64091 | bellard | int bdrv_pread(BlockDriverState *bs, int64_t offset,
|
618 | 83f64091 | bellard | void *buf, int count); |
619 | 83f64091 | bellard | int bdrv_pwrite(BlockDriverState *bs, int64_t offset,
|
620 | 83f64091 | bellard | const void *buf, int count); |
621 | 83f64091 | bellard | int bdrv_truncate(BlockDriverState *bs, int64_t offset);
|
622 | 83f64091 | bellard | int64_t bdrv_getlength(BlockDriverState *bs); |
623 | fc01f7e7 | bellard | void bdrv_get_geometry(BlockDriverState *bs, int64_t *nb_sectors_ptr);
|
624 | 33e3963e | bellard | int bdrv_commit(BlockDriverState *bs);
|
625 | 77fef8c1 | bellard | void bdrv_set_boot_sector(BlockDriverState *bs, const uint8_t *data, int size); |
626 | 83f64091 | bellard | /* async block I/O */
|
627 | 83f64091 | bellard | typedef struct BlockDriverAIOCB BlockDriverAIOCB; |
628 | 83f64091 | bellard | typedef void BlockDriverCompletionFunc(void *opaque, int ret); |
629 | 83f64091 | bellard | |
630 | ce1a14dc | pbrook | BlockDriverAIOCB *bdrv_aio_read(BlockDriverState *bs, int64_t sector_num, |
631 | ce1a14dc | pbrook | uint8_t *buf, int nb_sectors,
|
632 | ce1a14dc | pbrook | BlockDriverCompletionFunc *cb, void *opaque);
|
633 | ce1a14dc | pbrook | BlockDriverAIOCB *bdrv_aio_write(BlockDriverState *bs, int64_t sector_num, |
634 | ce1a14dc | pbrook | const uint8_t *buf, int nb_sectors, |
635 | ce1a14dc | pbrook | BlockDriverCompletionFunc *cb, void *opaque);
|
636 | 83f64091 | bellard | void bdrv_aio_cancel(BlockDriverAIOCB *acb);
|
637 | 83f64091 | bellard | |
638 | 83f64091 | bellard | void qemu_aio_init(void); |
639 | 83f64091 | bellard | void qemu_aio_poll(void); |
640 | 6192bc37 | pbrook | void qemu_aio_flush(void); |
641 | 83f64091 | bellard | void qemu_aio_wait_start(void); |
642 | 83f64091 | bellard | void qemu_aio_wait(void); |
643 | 83f64091 | bellard | void qemu_aio_wait_end(void); |
644 | 83f64091 | bellard | |
645 | 2bac6019 | balrog | int qemu_key_check(BlockDriverState *bs, const char *name); |
646 | 2bac6019 | balrog | |
647 | 7a6cba61 | pbrook | /* Ensure contents are flushed to disk. */
|
648 | 7a6cba61 | pbrook | void bdrv_flush(BlockDriverState *bs);
|
649 | 33e3963e | bellard | |
650 | c4b1fcc0 | bellard | #define BDRV_TYPE_HD 0 |
651 | c4b1fcc0 | bellard | #define BDRV_TYPE_CDROM 1 |
652 | c4b1fcc0 | bellard | #define BDRV_TYPE_FLOPPY 2 |
653 | 4dbb0f50 | ths | #define BIOS_ATA_TRANSLATION_AUTO 0 |
654 | 4dbb0f50 | ths | #define BIOS_ATA_TRANSLATION_NONE 1 |
655 | 4dbb0f50 | ths | #define BIOS_ATA_TRANSLATION_LBA 2 |
656 | 4dbb0f50 | ths | #define BIOS_ATA_TRANSLATION_LARGE 3 |
657 | 4dbb0f50 | ths | #define BIOS_ATA_TRANSLATION_RECHS 4 |
658 | c4b1fcc0 | bellard | |
659 | c4b1fcc0 | bellard | void bdrv_set_geometry_hint(BlockDriverState *bs,
|
660 | c4b1fcc0 | bellard | int cyls, int heads, int secs); |
661 | c4b1fcc0 | bellard | void bdrv_set_type_hint(BlockDriverState *bs, int type); |
662 | 46d4767d | bellard | void bdrv_set_translation_hint(BlockDriverState *bs, int translation); |
663 | c4b1fcc0 | bellard | void bdrv_get_geometry_hint(BlockDriverState *bs,
|
664 | c4b1fcc0 | bellard | int *pcyls, int *pheads, int *psecs); |
665 | c4b1fcc0 | bellard | int bdrv_get_type_hint(BlockDriverState *bs);
|
666 | 46d4767d | bellard | int bdrv_get_translation_hint(BlockDriverState *bs);
|
667 | c4b1fcc0 | bellard | int bdrv_is_removable(BlockDriverState *bs);
|
668 | c4b1fcc0 | bellard | int bdrv_is_read_only(BlockDriverState *bs);
|
669 | c4b1fcc0 | bellard | int bdrv_is_inserted(BlockDriverState *bs);
|
670 | 19cb3738 | bellard | int bdrv_media_changed(BlockDriverState *bs);
|
671 | c4b1fcc0 | bellard | int bdrv_is_locked(BlockDriverState *bs);
|
672 | c4b1fcc0 | bellard | void bdrv_set_locked(BlockDriverState *bs, int locked); |
673 | 19cb3738 | bellard | void bdrv_eject(BlockDriverState *bs, int eject_flag); |
674 | c4b1fcc0 | bellard | void bdrv_set_change_cb(BlockDriverState *bs,
|
675 | c4b1fcc0 | bellard | void (*change_cb)(void *opaque), void *opaque); |
676 | ea2384d3 | bellard | void bdrv_get_format(BlockDriverState *bs, char *buf, int buf_size); |
677 | c4b1fcc0 | bellard | void bdrv_info(void); |
678 | c4b1fcc0 | bellard | BlockDriverState *bdrv_find(const char *name); |
679 | 82c643ff | bellard | void bdrv_iterate(void (*it)(void *opaque, const char *name), void *opaque); |
680 | ea2384d3 | bellard | int bdrv_is_encrypted(BlockDriverState *bs);
|
681 | ea2384d3 | bellard | int bdrv_set_key(BlockDriverState *bs, const char *key); |
682 | ea2384d3 | bellard | void bdrv_iterate_format(void (*it)(void *opaque, const char *name), |
683 | ea2384d3 | bellard | void *opaque);
|
684 | ea2384d3 | bellard | const char *bdrv_get_device_name(BlockDriverState *bs); |
685 | faea38e7 | bellard | int bdrv_write_compressed(BlockDriverState *bs, int64_t sector_num,
|
686 | faea38e7 | bellard | const uint8_t *buf, int nb_sectors); |
687 | faea38e7 | bellard | int bdrv_get_info(BlockDriverState *bs, BlockDriverInfo *bdi);
|
688 | c4b1fcc0 | bellard | |
689 | 83f64091 | bellard | void bdrv_get_backing_filename(BlockDriverState *bs,
|
690 | 83f64091 | bellard | char *filename, int filename_size); |
691 | faea38e7 | bellard | int bdrv_snapshot_create(BlockDriverState *bs,
|
692 | faea38e7 | bellard | QEMUSnapshotInfo *sn_info); |
693 | faea38e7 | bellard | int bdrv_snapshot_goto(BlockDriverState *bs,
|
694 | faea38e7 | bellard | const char *snapshot_id); |
695 | faea38e7 | bellard | int bdrv_snapshot_delete(BlockDriverState *bs, const char *snapshot_id); |
696 | faea38e7 | bellard | int bdrv_snapshot_list(BlockDriverState *bs,
|
697 | faea38e7 | bellard | QEMUSnapshotInfo **psn_info); |
698 | faea38e7 | bellard | char *bdrv_snapshot_dump(char *buf, int buf_size, QEMUSnapshotInfo *sn); |
699 | faea38e7 | bellard | |
700 | faea38e7 | bellard | char *get_human_readable_size(char *buf, int buf_size, int64_t size); |
701 | 83f64091 | bellard | int path_is_absolute(const char *path); |
702 | 83f64091 | bellard | void path_combine(char *dest, int dest_size, |
703 | 83f64091 | bellard | const char *base_path, |
704 | 83f64091 | bellard | const char *filename); |
705 | ea2384d3 | bellard | |
706 | ea2384d3 | bellard | #ifndef QEMU_TOOL
|
707 | 54fa5af5 | bellard | |
708 | 54fa5af5 | bellard | typedef void QEMUMachineInitFunc(int ram_size, int vga_ram_size, |
709 | 54fa5af5 | bellard | int boot_device,
|
710 | 54fa5af5 | bellard | DisplayState *ds, const char **fd_filename, int snapshot, |
711 | 54fa5af5 | bellard | const char *kernel_filename, const char *kernel_cmdline, |
712 | 94fc95cd | j_mayer | const char *initrd_filename, const char *cpu_model); |
713 | 54fa5af5 | bellard | |
714 | 54fa5af5 | bellard | typedef struct QEMUMachine { |
715 | 54fa5af5 | bellard | const char *name; |
716 | 54fa5af5 | bellard | const char *desc; |
717 | 54fa5af5 | bellard | QEMUMachineInitFunc *init; |
718 | 54fa5af5 | bellard | struct QEMUMachine *next;
|
719 | 54fa5af5 | bellard | } QEMUMachine; |
720 | 54fa5af5 | bellard | |
721 | 54fa5af5 | bellard | int qemu_register_machine(QEMUMachine *m);
|
722 | 54fa5af5 | bellard | |
723 | 54fa5af5 | bellard | typedef void SetIRQFunc(void *opaque, int irq_num, int level); |
724 | 54fa5af5 | bellard | |
725 | 94fc95cd | j_mayer | #if defined(TARGET_PPC)
|
726 | 94fc95cd | j_mayer | void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)); |
727 | 94fc95cd | j_mayer | #endif
|
728 | 94fc95cd | j_mayer | |
729 | 33d68b5f | ths | #if defined(TARGET_MIPS)
|
730 | 33d68b5f | ths | void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)); |
731 | 33d68b5f | ths | #endif
|
732 | 33d68b5f | ths | |
733 | d537cf6c | pbrook | #include "hw/irq.h" |
734 | d537cf6c | pbrook | |
735 | 26aa7d72 | bellard | /* ISA bus */
|
736 | 26aa7d72 | bellard | |
737 | 26aa7d72 | bellard | extern target_phys_addr_t isa_mem_base;
|
738 | 26aa7d72 | bellard | |
739 | 26aa7d72 | bellard | typedef void (IOPortWriteFunc)(void *opaque, uint32_t address, uint32_t data); |
740 | 26aa7d72 | bellard | typedef uint32_t (IOPortReadFunc)(void *opaque, uint32_t address); |
741 | 26aa7d72 | bellard | |
742 | 26aa7d72 | bellard | int register_ioport_read(int start, int length, int size, |
743 | 26aa7d72 | bellard | IOPortReadFunc *func, void *opaque);
|
744 | 26aa7d72 | bellard | int register_ioport_write(int start, int length, int size, |
745 | 26aa7d72 | bellard | IOPortWriteFunc *func, void *opaque);
|
746 | 69b91039 | bellard | void isa_unassign_ioport(int start, int length); |
747 | 69b91039 | bellard | |
748 | aef445bd | pbrook | void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size);
|
749 | aef445bd | pbrook | |
750 | 69b91039 | bellard | /* PCI bus */
|
751 | 69b91039 | bellard | |
752 | 69b91039 | bellard | extern target_phys_addr_t pci_mem_base;
|
753 | 69b91039 | bellard | |
754 | 46e50e9d | bellard | typedef struct PCIBus PCIBus; |
755 | 69b91039 | bellard | typedef struct PCIDevice PCIDevice; |
756 | 69b91039 | bellard | |
757 | 69b91039 | bellard | typedef void PCIConfigWriteFunc(PCIDevice *pci_dev, |
758 | 69b91039 | bellard | uint32_t address, uint32_t data, int len);
|
759 | 69b91039 | bellard | typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
|
760 | 69b91039 | bellard | uint32_t address, int len);
|
761 | 69b91039 | bellard | typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num, |
762 | 69b91039 | bellard | uint32_t addr, uint32_t size, int type);
|
763 | 69b91039 | bellard | |
764 | 69b91039 | bellard | #define PCI_ADDRESS_SPACE_MEM 0x00 |
765 | 69b91039 | bellard | #define PCI_ADDRESS_SPACE_IO 0x01 |
766 | 69b91039 | bellard | #define PCI_ADDRESS_SPACE_MEM_PREFETCH 0x08 |
767 | 69b91039 | bellard | |
768 | 69b91039 | bellard | typedef struct PCIIORegion { |
769 | 5768f5ac | bellard | uint32_t addr; /* current PCI mapping address. -1 means not mapped */
|
770 | 69b91039 | bellard | uint32_t size; |
771 | 69b91039 | bellard | uint8_t type; |
772 | 69b91039 | bellard | PCIMapIORegionFunc *map_func; |
773 | 69b91039 | bellard | } PCIIORegion; |
774 | 69b91039 | bellard | |
775 | 8a8696a3 | bellard | #define PCI_ROM_SLOT 6 |
776 | 8a8696a3 | bellard | #define PCI_NUM_REGIONS 7 |
777 | 502a5395 | pbrook | |
778 | 502a5395 | pbrook | #define PCI_DEVICES_MAX 64 |
779 | 502a5395 | pbrook | |
780 | 502a5395 | pbrook | #define PCI_VENDOR_ID 0x00 /* 16 bits */ |
781 | 502a5395 | pbrook | #define PCI_DEVICE_ID 0x02 /* 16 bits */ |
782 | 502a5395 | pbrook | #define PCI_COMMAND 0x04 /* 16 bits */ |
783 | 502a5395 | pbrook | #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ |
784 | 502a5395 | pbrook | #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ |
785 | 502a5395 | pbrook | #define PCI_CLASS_DEVICE 0x0a /* Device class */ |
786 | 502a5395 | pbrook | #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ |
787 | 502a5395 | pbrook | #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */ |
788 | 502a5395 | pbrook | #define PCI_MIN_GNT 0x3e /* 8 bits */ |
789 | 502a5395 | pbrook | #define PCI_MAX_LAT 0x3f /* 8 bits */ |
790 | 502a5395 | pbrook | |
791 | 69b91039 | bellard | struct PCIDevice {
|
792 | 69b91039 | bellard | /* PCI config space */
|
793 | 69b91039 | bellard | uint8_t config[256];
|
794 | 69b91039 | bellard | |
795 | 69b91039 | bellard | /* the following fields are read only */
|
796 | 46e50e9d | bellard | PCIBus *bus; |
797 | 69b91039 | bellard | int devfn;
|
798 | 69b91039 | bellard | char name[64]; |
799 | 8a8696a3 | bellard | PCIIORegion io_regions[PCI_NUM_REGIONS]; |
800 | 69b91039 | bellard | |
801 | 69b91039 | bellard | /* do not access the following fields */
|
802 | 69b91039 | bellard | PCIConfigReadFunc *config_read; |
803 | 69b91039 | bellard | PCIConfigWriteFunc *config_write; |
804 | 502a5395 | pbrook | /* ??? This is a PC-specific hack, and should be removed. */
|
805 | 5768f5ac | bellard | int irq_index;
|
806 | d2b59317 | pbrook | |
807 | d537cf6c | pbrook | /* IRQ objects for the INTA-INTD pins. */
|
808 | d537cf6c | pbrook | qemu_irq *irq; |
809 | d537cf6c | pbrook | |
810 | d2b59317 | pbrook | /* Current IRQ levels. Used internally by the generic PCI code. */
|
811 | d2b59317 | pbrook | int irq_state[4]; |
812 | 69b91039 | bellard | }; |
813 | 69b91039 | bellard | |
814 | 46e50e9d | bellard | PCIDevice *pci_register_device(PCIBus *bus, const char *name, |
815 | 46e50e9d | bellard | int instance_size, int devfn, |
816 | 69b91039 | bellard | PCIConfigReadFunc *config_read, |
817 | 69b91039 | bellard | PCIConfigWriteFunc *config_write); |
818 | 69b91039 | bellard | |
819 | 69b91039 | bellard | void pci_register_io_region(PCIDevice *pci_dev, int region_num, |
820 | 69b91039 | bellard | uint32_t size, int type,
|
821 | 69b91039 | bellard | PCIMapIORegionFunc *map_func); |
822 | 69b91039 | bellard | |
823 | 5768f5ac | bellard | uint32_t pci_default_read_config(PCIDevice *d, |
824 | 5768f5ac | bellard | uint32_t address, int len);
|
825 | 5768f5ac | bellard | void pci_default_write_config(PCIDevice *d,
|
826 | 5768f5ac | bellard | uint32_t address, uint32_t val, int len);
|
827 | 89b6b508 | bellard | void pci_device_save(PCIDevice *s, QEMUFile *f);
|
828 | 89b6b508 | bellard | int pci_device_load(PCIDevice *s, QEMUFile *f);
|
829 | 5768f5ac | bellard | |
830 | d537cf6c | pbrook | typedef void (*pci_set_irq_fn)(qemu_irq *pic, int irq_num, int level); |
831 | d2b59317 | pbrook | typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num); |
832 | d2b59317 | pbrook | PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, |
833 | d537cf6c | pbrook | qemu_irq *pic, int devfn_min, int nirq); |
834 | 502a5395 | pbrook | |
835 | abcebc7e | ths | void pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn); |
836 | 502a5395 | pbrook | void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len); |
837 | 502a5395 | pbrook | uint32_t pci_data_read(void *opaque, uint32_t addr, int len); |
838 | 502a5395 | pbrook | int pci_bus_num(PCIBus *s);
|
839 | 80b3ada7 | pbrook | void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d)); |
840 | 9995c51f | bellard | |
841 | 5768f5ac | bellard | void pci_info(void); |
842 | 80b3ada7 | pbrook | PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint32_t id,
|
843 | 80b3ada7 | pbrook | pci_map_irq_fn map_irq, const char *name); |
844 | 26aa7d72 | bellard | |
845 | 502a5395 | pbrook | /* prep_pci.c */
|
846 | d537cf6c | pbrook | PCIBus *pci_prep_init(qemu_irq *pic); |
847 | 77d4bc34 | bellard | |
848 | 502a5395 | pbrook | /* grackle_pci.c */
|
849 | d537cf6c | pbrook | PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic); |
850 | 502a5395 | pbrook | |
851 | 502a5395 | pbrook | /* unin_pci.c */
|
852 | d537cf6c | pbrook | PCIBus *pci_pmac_init(qemu_irq *pic); |
853 | 502a5395 | pbrook | |
854 | 502a5395 | pbrook | /* apb_pci.c */
|
855 | 5b9693dc | blueswir1 | PCIBus *pci_apb_init(target_phys_addr_t special_base, target_phys_addr_t mem_base, |
856 | d537cf6c | pbrook | qemu_irq *pic); |
857 | 502a5395 | pbrook | |
858 | d537cf6c | pbrook | PCIBus *pci_vpb_init(qemu_irq *pic, int irq, int realview); |
859 | 502a5395 | pbrook | |
860 | 502a5395 | pbrook | /* piix_pci.c */
|
861 | d537cf6c | pbrook | PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic); |
862 | f00fc47c | bellard | void i440fx_set_smm(PCIDevice *d, int val); |
863 | 8f1c91d8 | ths | int piix3_init(PCIBus *bus, int devfn); |
864 | f00fc47c | bellard | void i440fx_init_memory_mappings(PCIDevice *d);
|
865 | a41b2ff2 | pbrook | |
866 | 5856de80 | ths | int piix4_init(PCIBus *bus, int devfn); |
867 | 5856de80 | ths | |
868 | 28b9b5af | bellard | /* openpic.c */
|
869 | e9df014c | j_mayer | /* OpenPIC have 5 outputs per CPU connected and one IRQ out single output */
|
870 | 47103572 | j_mayer | enum {
|
871 | e9df014c | j_mayer | OPENPIC_OUTPUT_INT = 0, /* IRQ */ |
872 | e9df014c | j_mayer | OPENPIC_OUTPUT_CINT, /* critical IRQ */
|
873 | e9df014c | j_mayer | OPENPIC_OUTPUT_MCK, /* Machine check event */
|
874 | e9df014c | j_mayer | OPENPIC_OUTPUT_DEBUG, /* Inconditional debug event */
|
875 | e9df014c | j_mayer | OPENPIC_OUTPUT_RESET, /* Core reset event */
|
876 | e9df014c | j_mayer | OPENPIC_OUTPUT_NB, |
877 | 47103572 | j_mayer | }; |
878 | e9df014c | j_mayer | qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus, |
879 | e9df014c | j_mayer | qemu_irq **irqs, qemu_irq irq_out); |
880 | 28b9b5af | bellard | |
881 | 54fa5af5 | bellard | /* heathrow_pic.c */
|
882 | d537cf6c | pbrook | qemu_irq *heathrow_pic_init(int *pmem_index);
|
883 | 54fa5af5 | bellard | |
884 | fde7d5bd | ths | /* gt64xxx.c */
|
885 | d537cf6c | pbrook | PCIBus *pci_gt64120_init(qemu_irq *pic); |
886 | fde7d5bd | ths | |
887 | 6a36d84e | bellard | #ifdef HAS_AUDIO
|
888 | 6a36d84e | bellard | struct soundhw {
|
889 | 6a36d84e | bellard | const char *name; |
890 | 6a36d84e | bellard | const char *descr; |
891 | 6a36d84e | bellard | int enabled;
|
892 | 6a36d84e | bellard | int isa;
|
893 | 6a36d84e | bellard | union {
|
894 | d537cf6c | pbrook | int (*init_isa) (AudioState *s, qemu_irq *pic);
|
895 | 6a36d84e | bellard | int (*init_pci) (PCIBus *bus, AudioState *s);
|
896 | 6a36d84e | bellard | } init; |
897 | 6a36d84e | bellard | }; |
898 | 6a36d84e | bellard | |
899 | 6a36d84e | bellard | extern struct soundhw soundhw[]; |
900 | 6a36d84e | bellard | #endif
|
901 | 6a36d84e | bellard | |
902 | 313aa567 | bellard | /* vga.c */
|
903 | 313aa567 | bellard | |
904 | eee0b836 | blueswir1 | #ifndef TARGET_SPARC
|
905 | 74a14f22 | bellard | #define VGA_RAM_SIZE (8192 * 1024) |
906 | eee0b836 | blueswir1 | #else
|
907 | eee0b836 | blueswir1 | #define VGA_RAM_SIZE (9 * 1024 * 1024) |
908 | eee0b836 | blueswir1 | #endif
|
909 | 313aa567 | bellard | |
910 | 82c643ff | bellard | struct DisplayState {
|
911 | 313aa567 | bellard | uint8_t *data; |
912 | 313aa567 | bellard | int linesize;
|
913 | 313aa567 | bellard | int depth;
|
914 | d3079cd2 | bellard | int bgr; /* BGR color order instead of RGB. Only valid for depth == 32 */ |
915 | 82c643ff | bellard | int width;
|
916 | 82c643ff | bellard | int height;
|
917 | 24236869 | bellard | void *opaque;
|
918 | 740733bb | ths | QEMUTimer *gui_timer; |
919 | 24236869 | bellard | |
920 | 313aa567 | bellard | void (*dpy_update)(struct DisplayState *s, int x, int y, int w, int h); |
921 | 313aa567 | bellard | void (*dpy_resize)(struct DisplayState *s, int w, int h); |
922 | 313aa567 | bellard | void (*dpy_refresh)(struct DisplayState *s); |
923 | d34cab9f | ths | void (*dpy_copy)(struct DisplayState *s, int src_x, int src_y, |
924 | d34cab9f | ths | int dst_x, int dst_y, int w, int h); |
925 | d34cab9f | ths | void (*dpy_fill)(struct DisplayState *s, int x, int y, |
926 | d34cab9f | ths | int w, int h, uint32_t c); |
927 | d34cab9f | ths | void (*mouse_set)(int x, int y, int on); |
928 | d34cab9f | ths | void (*cursor_define)(int width, int height, int bpp, int hot_x, int hot_y, |
929 | d34cab9f | ths | uint8_t *image, uint8_t *mask); |
930 | 82c643ff | bellard | }; |
931 | 313aa567 | bellard | |
932 | 313aa567 | bellard | static inline void dpy_update(DisplayState *s, int x, int y, int w, int h) |
933 | 313aa567 | bellard | { |
934 | 313aa567 | bellard | s->dpy_update(s, x, y, w, h); |
935 | 313aa567 | bellard | } |
936 | 313aa567 | bellard | |
937 | 313aa567 | bellard | static inline void dpy_resize(DisplayState *s, int w, int h) |
938 | 313aa567 | bellard | { |
939 | 313aa567 | bellard | s->dpy_resize(s, w, h); |
940 | 313aa567 | bellard | } |
941 | 313aa567 | bellard | |
942 | 89b6b508 | bellard | int isa_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
|
943 | 89b6b508 | bellard | unsigned long vga_ram_offset, int vga_ram_size); |
944 | 89b6b508 | bellard | int pci_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
|
945 | 89b6b508 | bellard | unsigned long vga_ram_offset, int vga_ram_size, |
946 | 89b6b508 | bellard | unsigned long vga_bios_offset, int vga_bios_size); |
947 | 2abec30b | ths | int isa_vga_mm_init(DisplayState *ds, uint8_t *vga_ram_base,
|
948 | 2abec30b | ths | unsigned long vga_ram_offset, int vga_ram_size, |
949 | 2abec30b | ths | target_phys_addr_t vram_base, target_phys_addr_t ctrl_base, |
950 | 2abec30b | ths | int it_shift);
|
951 | 313aa567 | bellard | |
952 | d6bfa22f | bellard | /* cirrus_vga.c */
|
953 | 46e50e9d | bellard | void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
|
954 | d6bfa22f | bellard | unsigned long vga_ram_offset, int vga_ram_size); |
955 | d6bfa22f | bellard | void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
|
956 | d6bfa22f | bellard | unsigned long vga_ram_offset, int vga_ram_size); |
957 | d6bfa22f | bellard | |
958 | d34cab9f | ths | /* vmware_vga.c */
|
959 | d34cab9f | ths | void pci_vmsvga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
|
960 | d34cab9f | ths | unsigned long vga_ram_offset, int vga_ram_size); |
961 | d34cab9f | ths | |
962 | 313aa567 | bellard | /* sdl.c */
|
963 | 43523e93 | ths | void sdl_display_init(DisplayState *ds, int full_screen, int no_frame); |
964 | 313aa567 | bellard | |
965 | da4dbf74 | bellard | /* cocoa.m */
|
966 | da4dbf74 | bellard | void cocoa_display_init(DisplayState *ds, int full_screen); |
967 | da4dbf74 | bellard | |
968 | 24236869 | bellard | /* vnc.c */
|
969 | 73fc9742 | ths | void vnc_display_init(DisplayState *ds, const char *display); |
970 | a9ce8590 | bellard | void do_info_vnc(void); |
971 | 24236869 | bellard | |
972 | 6070dd07 | ths | /* x_keymap.c */
|
973 | 6070dd07 | ths | extern uint8_t _translate_keycode(const int key); |
974 | 6070dd07 | ths | |
975 | 5391d806 | bellard | /* ide.c */
|
976 | 5391d806 | bellard | #define MAX_DISKS 4 |
977 | 5391d806 | bellard | |
978 | faea38e7 | bellard | extern BlockDriverState *bs_table[MAX_DISKS + 1]; |
979 | a1bb27b1 | pbrook | extern BlockDriverState *sd_bdrv;
|
980 | 3e3d5815 | balrog | extern BlockDriverState *mtd_bdrv;
|
981 | 5391d806 | bellard | |
982 | d537cf6c | pbrook | void isa_ide_init(int iobase, int iobase2, qemu_irq irq, |
983 | 69b91039 | bellard | BlockDriverState *hd0, BlockDriverState *hd1); |
984 | 54fa5af5 | bellard | void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
|
985 | 54fa5af5 | bellard | int secondary_ide_enabled);
|
986 | d537cf6c | pbrook | void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn, |
987 | d537cf6c | pbrook | qemu_irq *pic); |
988 | afcc3cdf | ths | void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn, |
989 | afcc3cdf | ths | qemu_irq *pic); |
990 | d537cf6c | pbrook | int pmac_ide_init (BlockDriverState **hd_table, qemu_irq irq);
|
991 | 5391d806 | bellard | |
992 | 2e5d83bb | pbrook | /* cdrom.c */
|
993 | 2e5d83bb | pbrook | int cdrom_read_toc(int nb_sectors, uint8_t *buf, int msf, int start_track); |
994 | 2e5d83bb | pbrook | int cdrom_read_toc_raw(int nb_sectors, uint8_t *buf, int msf, int session_num); |
995 | 2e5d83bb | pbrook | |
996 | 9542611a | ths | /* ds1225y.c */
|
997 | 9542611a | ths | typedef struct ds1225y_t ds1225y_t; |
998 | 71db710f | blueswir1 | ds1225y_t *ds1225y_init(target_phys_addr_t mem_base, const char *filename); |
999 | 9542611a | ths | |
1000 | 1d14ffa9 | bellard | /* es1370.c */
|
1001 | c0fe3827 | bellard | int es1370_init (PCIBus *bus, AudioState *s);
|
1002 | 1d14ffa9 | bellard | |
1003 | fb065187 | bellard | /* sb16.c */
|
1004 | d537cf6c | pbrook | int SB16_init (AudioState *s, qemu_irq *pic);
|
1005 | fb065187 | bellard | |
1006 | fb065187 | bellard | /* adlib.c */
|
1007 | d537cf6c | pbrook | int Adlib_init (AudioState *s, qemu_irq *pic);
|
1008 | fb065187 | bellard | |
1009 | fb065187 | bellard | /* gus.c */
|
1010 | d537cf6c | pbrook | int GUS_init (AudioState *s, qemu_irq *pic);
|
1011 | 27503323 | bellard | |
1012 | 27503323 | bellard | /* dma.c */
|
1013 | 85571bc7 | bellard | typedef int (*DMA_transfer_handler) (void *opaque, int nchan, int pos, int size); |
1014 | 27503323 | bellard | int DMA_get_channel_mode (int nchan); |
1015 | 85571bc7 | bellard | int DMA_read_memory (int nchan, void *buf, int pos, int size); |
1016 | 85571bc7 | bellard | int DMA_write_memory (int nchan, void *buf, int pos, int size); |
1017 | 27503323 | bellard | void DMA_hold_DREQ (int nchan); |
1018 | 27503323 | bellard | void DMA_release_DREQ (int nchan); |
1019 | 16f62432 | bellard | void DMA_schedule(int nchan); |
1020 | 27503323 | bellard | void DMA_run (void); |
1021 | 28b9b5af | bellard | void DMA_init (int high_page_enable); |
1022 | 27503323 | bellard | void DMA_register_channel (int nchan, |
1023 | 85571bc7 | bellard | DMA_transfer_handler transfer_handler, |
1024 | 85571bc7 | bellard | void *opaque);
|
1025 | 7138fcfb | bellard | /* fdc.c */
|
1026 | 7138fcfb | bellard | #define MAX_FD 2 |
1027 | 7138fcfb | bellard | extern BlockDriverState *fd_table[MAX_FD];
|
1028 | 7138fcfb | bellard | |
1029 | baca51fa | bellard | typedef struct fdctrl_t fdctrl_t; |
1030 | baca51fa | bellard | |
1031 | d537cf6c | pbrook | fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped, |
1032 | 5dcb6b91 | blueswir1 | target_phys_addr_t io_base, |
1033 | baca51fa | bellard | BlockDriverState **fds); |
1034 | baca51fa | bellard | int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num); |
1035 | 7138fcfb | bellard | |
1036 | 663e8e51 | ths | /* eepro100.c */
|
1037 | 663e8e51 | ths | |
1038 | 663e8e51 | ths | void pci_i82551_init(PCIBus *bus, NICInfo *nd, int devfn); |
1039 | 663e8e51 | ths | void pci_i82557b_init(PCIBus *bus, NICInfo *nd, int devfn); |
1040 | 663e8e51 | ths | void pci_i82559er_init(PCIBus *bus, NICInfo *nd, int devfn); |
1041 | 663e8e51 | ths | |
1042 | 80cabfad | bellard | /* ne2000.c */
|
1043 | 80cabfad | bellard | |
1044 | d537cf6c | pbrook | void isa_ne2000_init(int base, qemu_irq irq, NICInfo *nd); |
1045 | abcebc7e | ths | void pci_ne2000_init(PCIBus *bus, NICInfo *nd, int devfn); |
1046 | 80cabfad | bellard | |
1047 | a41b2ff2 | pbrook | /* rtl8139.c */
|
1048 | a41b2ff2 | pbrook | |
1049 | abcebc7e | ths | void pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn); |
1050 | a41b2ff2 | pbrook | |
1051 | e3c2613f | bellard | /* pcnet.c */
|
1052 | e3c2613f | bellard | |
1053 | abcebc7e | ths | void pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn); |
1054 | 70c0de96 | blueswir1 | void lance_init(NICInfo *nd, target_phys_addr_t leaddr, void *dma_opaque, |
1055 | 5dcb6b91 | blueswir1 | qemu_irq irq); |
1056 | 67e999be | bellard | |
1057 | 548df2ac | ths | /* vmmouse.c */
|
1058 | 548df2ac | ths | void *vmmouse_init(void *m); |
1059 | e3c2613f | bellard | |
1060 | 80cabfad | bellard | /* pckbd.c */
|
1061 | 80cabfad | bellard | |
1062 | b92bb99b | ths | void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
|
1063 | 71db710f | blueswir1 | void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
|
1064 | 71db710f | blueswir1 | target_phys_addr_t base, int it_shift);
|
1065 | 80cabfad | bellard | |
1066 | 80cabfad | bellard | /* mc146818rtc.c */
|
1067 | 80cabfad | bellard | |
1068 | 8a7ddc38 | bellard | typedef struct RTCState RTCState; |
1069 | 80cabfad | bellard | |
1070 | d537cf6c | pbrook | RTCState *rtc_init(int base, qemu_irq irq);
|
1071 | 18c6e2ff | ths | RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq);
|
1072 | 8a7ddc38 | bellard | void rtc_set_memory(RTCState *s, int addr, int val); |
1073 | 8a7ddc38 | bellard | void rtc_set_date(RTCState *s, const struct tm *tm); |
1074 | 80cabfad | bellard | |
1075 | 80cabfad | bellard | /* serial.c */
|
1076 | 80cabfad | bellard | |
1077 | c4b1fcc0 | bellard | typedef struct SerialState SerialState; |
1078 | d537cf6c | pbrook | SerialState *serial_init(int base, qemu_irq irq, CharDriverState *chr);
|
1079 | 71db710f | blueswir1 | SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
|
1080 | d537cf6c | pbrook | qemu_irq irq, CharDriverState *chr, |
1081 | a4bc3afc | ths | int ioregister);
|
1082 | a4bc3afc | ths | uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr);
|
1083 | a4bc3afc | ths | void serial_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value); |
1084 | a4bc3afc | ths | uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr);
|
1085 | a4bc3afc | ths | void serial_mm_writew (void *opaque, target_phys_addr_t addr, uint32_t value); |
1086 | a4bc3afc | ths | uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr);
|
1087 | a4bc3afc | ths | void serial_mm_writel (void *opaque, target_phys_addr_t addr, uint32_t value); |
1088 | 80cabfad | bellard | |
1089 | 6508fe59 | bellard | /* parallel.c */
|
1090 | 6508fe59 | bellard | |
1091 | 6508fe59 | bellard | typedef struct ParallelState ParallelState; |
1092 | d537cf6c | pbrook | ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr);
|
1093 | d60532ca | ths | ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState *chr);
|
1094 | 6508fe59 | bellard | |
1095 | 80cabfad | bellard | /* i8259.c */
|
1096 | 80cabfad | bellard | |
1097 | 3de388f6 | bellard | typedef struct PicState2 PicState2; |
1098 | 3de388f6 | bellard | extern PicState2 *isa_pic;
|
1099 | 80cabfad | bellard | void pic_set_irq(int irq, int level); |
1100 | 54fa5af5 | bellard | void pic_set_irq_new(void *opaque, int irq, int level); |
1101 | d537cf6c | pbrook | qemu_irq *i8259_init(qemu_irq parent_irq); |
1102 | d592d303 | bellard | void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func,
|
1103 | d592d303 | bellard | void *alt_irq_opaque);
|
1104 | 3de388f6 | bellard | int pic_read_irq(PicState2 *s);
|
1105 | 3de388f6 | bellard | void pic_update_irq(PicState2 *s);
|
1106 | 3de388f6 | bellard | uint32_t pic_intack_read(PicState2 *s); |
1107 | c20709aa | bellard | void pic_info(void); |
1108 | 4a0fb71e | bellard | void irq_info(void); |
1109 | 80cabfad | bellard | |
1110 | c27004ec | bellard | /* APIC */
|
1111 | d592d303 | bellard | typedef struct IOAPICState IOAPICState; |
1112 | d592d303 | bellard | |
1113 | c27004ec | bellard | int apic_init(CPUState *env);
|
1114 | c27004ec | bellard | int apic_get_interrupt(CPUState *env);
|
1115 | d592d303 | bellard | IOAPICState *ioapic_init(void);
|
1116 | d592d303 | bellard | void ioapic_set_irq(void *opaque, int vector, int level); |
1117 | c27004ec | bellard | |
1118 | 80cabfad | bellard | /* i8254.c */
|
1119 | 80cabfad | bellard | |
1120 | 80cabfad | bellard | #define PIT_FREQ 1193182 |
1121 | 80cabfad | bellard | |
1122 | ec844b96 | bellard | typedef struct PITState PITState; |
1123 | ec844b96 | bellard | |
1124 | d537cf6c | pbrook | PITState *pit_init(int base, qemu_irq irq);
|
1125 | ec844b96 | bellard | void pit_set_gate(PITState *pit, int channel, int val); |
1126 | ec844b96 | bellard | int pit_get_gate(PITState *pit, int channel); |
1127 | fd06c375 | bellard | int pit_get_initial_count(PITState *pit, int channel); |
1128 | fd06c375 | bellard | int pit_get_mode(PITState *pit, int channel); |
1129 | ec844b96 | bellard | int pit_get_out(PITState *pit, int channel, int64_t current_time); |
1130 | 80cabfad | bellard | |
1131 | 31211df1 | ths | /* jazz_led.c */
|
1132 | 31211df1 | ths | extern void jazz_led_init(DisplayState *ds, target_phys_addr_t base); |
1133 | 31211df1 | ths | |
1134 | fd06c375 | bellard | /* pcspk.c */
|
1135 | fd06c375 | bellard | void pcspk_init(PITState *);
|
1136 | d537cf6c | pbrook | int pcspk_audio_init(AudioState *, qemu_irq *pic);
|
1137 | fd06c375 | bellard | |
1138 | 0ff596d0 | pbrook | #include "hw/i2c.h" |
1139 | 0ff596d0 | pbrook | |
1140 | 3fffc223 | ths | #include "hw/smbus.h" |
1141 | 3fffc223 | ths | |
1142 | 6515b203 | bellard | /* acpi.c */
|
1143 | 6515b203 | bellard | extern int acpi_enabled; |
1144 | 7b717336 | ths | i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base);
|
1145 | 3fffc223 | ths | void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
|
1146 | 6515b203 | bellard | void acpi_bios_init(void); |
1147 | 6515b203 | bellard | |
1148 | 80cabfad | bellard | /* pc.c */
|
1149 | 54fa5af5 | bellard | extern QEMUMachine pc_machine;
|
1150 | 3dbbdc25 | bellard | extern QEMUMachine isapc_machine;
|
1151 | 52ca8d6a | bellard | extern int fd_bootchk; |
1152 | 80cabfad | bellard | |
1153 | 6a00d601 | bellard | void ioport_set_a20(int enable); |
1154 | 6a00d601 | bellard | int ioport_get_a20(void); |
1155 | 6a00d601 | bellard | |
1156 | 26aa7d72 | bellard | /* ppc.c */
|
1157 | 54fa5af5 | bellard | extern QEMUMachine prep_machine;
|
1158 | 54fa5af5 | bellard | extern QEMUMachine core99_machine;
|
1159 | 54fa5af5 | bellard | extern QEMUMachine heathrow_machine;
|
1160 | 1a6c0886 | j_mayer | extern QEMUMachine ref405ep_machine;
|
1161 | 1a6c0886 | j_mayer | extern QEMUMachine taihu_machine;
|
1162 | 54fa5af5 | bellard | |
1163 | 6af0bf9c | bellard | /* mips_r4k.c */
|
1164 | 6af0bf9c | bellard | extern QEMUMachine mips_machine;
|
1165 | 6af0bf9c | bellard | |
1166 | 5856de80 | ths | /* mips_malta.c */
|
1167 | 5856de80 | ths | extern QEMUMachine mips_malta_machine;
|
1168 | 5856de80 | ths | |
1169 | ad6fe1d2 | ths | /* mips_int.c */
|
1170 | d537cf6c | pbrook | extern void cpu_mips_irq_init_cpu(CPUState *env); |
1171 | 4de9b249 | ths | |
1172 | ad6fe1d2 | ths | /* mips_pica61.c */
|
1173 | ad6fe1d2 | ths | extern QEMUMachine mips_pica61_machine;
|
1174 | ad6fe1d2 | ths | |
1175 | e16fe40c | ths | /* mips_timer.c */
|
1176 | e16fe40c | ths | extern void cpu_mips_clock_init(CPUState *); |
1177 | e16fe40c | ths | extern void cpu_mips_irqctrl_init (void); |
1178 | e16fe40c | ths | |
1179 | 27c7ca7e | bellard | /* shix.c */
|
1180 | 27c7ca7e | bellard | extern QEMUMachine shix_machine;
|
1181 | 27c7ca7e | bellard | |
1182 | 8cc43fef | bellard | #ifdef TARGET_PPC
|
1183 | 47103572 | j_mayer | /* PowerPC hardware exceptions management helpers */
|
1184 | 8ecc7913 | j_mayer | typedef void (*clk_setup_cb)(void *opaque, uint32_t freq); |
1185 | 8ecc7913 | j_mayer | typedef struct clk_setup_t clk_setup_t; |
1186 | 8ecc7913 | j_mayer | struct clk_setup_t {
|
1187 | 8ecc7913 | j_mayer | clk_setup_cb cb; |
1188 | 8ecc7913 | j_mayer | void *opaque;
|
1189 | 8ecc7913 | j_mayer | }; |
1190 | 8ecc7913 | j_mayer | static inline void clk_setup (clk_setup_t *clk, uint32_t freq) |
1191 | 8ecc7913 | j_mayer | { |
1192 | 8ecc7913 | j_mayer | if (clk->cb != NULL) |
1193 | 8ecc7913 | j_mayer | (*clk->cb)(clk->opaque, freq); |
1194 | 8ecc7913 | j_mayer | } |
1195 | 8ecc7913 | j_mayer | |
1196 | 8ecc7913 | j_mayer | clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq); |
1197 | 2e719ba3 | j_mayer | /* Embedded PowerPC DCR management */
|
1198 | 2e719ba3 | j_mayer | typedef target_ulong (*dcr_read_cb)(void *opaque, int dcrn); |
1199 | 2e719ba3 | j_mayer | typedef void (*dcr_write_cb)(void *opaque, int dcrn, target_ulong val); |
1200 | 2e719ba3 | j_mayer | int ppc_dcr_init (CPUState *env, int (*dcr_read_error)(int dcrn), |
1201 | 2e719ba3 | j_mayer | int (*dcr_write_error)(int dcrn)); |
1202 | 2e719ba3 | j_mayer | int ppc_dcr_register (CPUState *env, int dcrn, void *opaque, |
1203 | 2e719ba3 | j_mayer | dcr_read_cb drc_read, dcr_write_cb dcr_write); |
1204 | 8ecc7913 | j_mayer | clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq); |
1205 | 4a057712 | j_mayer | /* Embedded PowerPC reset */
|
1206 | 4a057712 | j_mayer | void ppc40x_core_reset (CPUState *env);
|
1207 | 4a057712 | j_mayer | void ppc40x_chip_reset (CPUState *env);
|
1208 | 4a057712 | j_mayer | void ppc40x_system_reset (CPUState *env);
|
1209 | 8cc43fef | bellard | #endif
|
1210 | 64201201 | bellard | void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val); |
1211 | 77d4bc34 | bellard | |
1212 | 77d4bc34 | bellard | extern CPUWriteMemoryFunc *PPC_io_write[];
|
1213 | 77d4bc34 | bellard | extern CPUReadMemoryFunc *PPC_io_read[];
|
1214 | 54fa5af5 | bellard | void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val); |
1215 | 26aa7d72 | bellard | |
1216 | e95c8d51 | bellard | /* sun4m.c */
|
1217 | e0353fe2 | blueswir1 | extern QEMUMachine ss5_machine, ss10_machine;
|
1218 | e95c8d51 | bellard | |
1219 | e95c8d51 | bellard | /* iommu.c */
|
1220 | 5dcb6b91 | blueswir1 | void *iommu_init(target_phys_addr_t addr);
|
1221 | 67e999be | bellard | void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr, |
1222 | a917d384 | pbrook | uint8_t *buf, int len, int is_write); |
1223 | 67e999be | bellard | static inline void sparc_iommu_memory_read(void *opaque, |
1224 | 67e999be | bellard | target_phys_addr_t addr, |
1225 | 67e999be | bellard | uint8_t *buf, int len)
|
1226 | 67e999be | bellard | { |
1227 | 67e999be | bellard | sparc_iommu_memory_rw(opaque, addr, buf, len, 0);
|
1228 | 67e999be | bellard | } |
1229 | e95c8d51 | bellard | |
1230 | 67e999be | bellard | static inline void sparc_iommu_memory_write(void *opaque, |
1231 | 67e999be | bellard | target_phys_addr_t addr, |
1232 | 67e999be | bellard | uint8_t *buf, int len)
|
1233 | 67e999be | bellard | { |
1234 | 67e999be | bellard | sparc_iommu_memory_rw(opaque, addr, buf, len, 1);
|
1235 | 67e999be | bellard | } |
1236 | e95c8d51 | bellard | |
1237 | e95c8d51 | bellard | /* tcx.c */
|
1238 | 5dcb6b91 | blueswir1 | void tcx_init(DisplayState *ds, target_phys_addr_t addr, uint8_t *vram_base,
|
1239 | 5dcb6b91 | blueswir1 | unsigned long vram_offset, int vram_size, int width, int height, |
1240 | eee0b836 | blueswir1 | int depth);
|
1241 | e80cfcfc | bellard | |
1242 | e80cfcfc | bellard | /* slavio_intctl.c */
|
1243 | 5dcb6b91 | blueswir1 | void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg,
|
1244 | d537cf6c | pbrook | const uint32_t *intbit_to_level,
|
1245 | d7edfd27 | blueswir1 | qemu_irq **irq, qemu_irq **cpu_irq, |
1246 | b3a23197 | blueswir1 | qemu_irq **parent_irq, unsigned int cputimer); |
1247 | e80cfcfc | bellard | void slavio_pic_info(void *opaque); |
1248 | e80cfcfc | bellard | void slavio_irq_info(void *opaque); |
1249 | e95c8d51 | bellard | |
1250 | 5fe141fd | bellard | /* loader.c */
|
1251 | 5fe141fd | bellard | int get_image_size(const char *filename); |
1252 | 5fe141fd | bellard | int load_image(const char *filename, uint8_t *addr); |
1253 | 74287114 | ths | int load_elf(const char *filename, int64_t virt_to_phys_addend, |
1254 | 74287114 | ths | uint64_t *pentry, uint64_t *lowaddr, uint64_t *highaddr); |
1255 | e80cfcfc | bellard | int load_aout(const char *filename, uint8_t *addr); |
1256 | 1c7b3754 | pbrook | int load_uboot(const char *filename, target_ulong *ep, int *is_linux); |
1257 | e80cfcfc | bellard | |
1258 | e80cfcfc | bellard | /* slavio_timer.c */
|
1259 | d7edfd27 | blueswir1 | void slavio_timer_init(target_phys_addr_t addr, qemu_irq irq, int mode); |
1260 | 8d5f07fa | bellard | |
1261 | e80cfcfc | bellard | /* slavio_serial.c */
|
1262 | 5dcb6b91 | blueswir1 | SerialState *slavio_serial_init(target_phys_addr_t base, qemu_irq irq, |
1263 | 5dcb6b91 | blueswir1 | CharDriverState *chr1, CharDriverState *chr2); |
1264 | 5dcb6b91 | blueswir1 | void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq);
|
1265 | e95c8d51 | bellard | |
1266 | 3475187d | bellard | /* slavio_misc.c */
|
1267 | 5dcb6b91 | blueswir1 | void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base,
|
1268 | 5dcb6b91 | blueswir1 | qemu_irq irq); |
1269 | 3475187d | bellard | void slavio_set_power_fail(void *opaque, int power_failing); |
1270 | 3475187d | bellard | |
1271 | 6f7e9aec | bellard | /* esp.c */
|
1272 | fa1fb14c | ths | void esp_scsi_attach(void *opaque, BlockDriverState *bd, int id); |
1273 | 5dcb6b91 | blueswir1 | void *esp_init(BlockDriverState **bd, target_phys_addr_t espaddr,
|
1274 | 70c0de96 | blueswir1 | void *dma_opaque, qemu_irq irq);
|
1275 | 67e999be | bellard | |
1276 | 67e999be | bellard | /* sparc32_dma.c */
|
1277 | 70c0de96 | blueswir1 | void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
|
1278 | 70c0de96 | blueswir1 | void *iommu, qemu_irq **dev_irq);
|
1279 | 9b94dc32 | bellard | void ledma_memory_read(void *opaque, target_phys_addr_t addr, |
1280 | 9b94dc32 | bellard | uint8_t *buf, int len, int do_bswap); |
1281 | 9b94dc32 | bellard | void ledma_memory_write(void *opaque, target_phys_addr_t addr, |
1282 | 9b94dc32 | bellard | uint8_t *buf, int len, int do_bswap); |
1283 | 67e999be | bellard | void espdma_memory_read(void *opaque, uint8_t *buf, int len); |
1284 | 67e999be | bellard | void espdma_memory_write(void *opaque, uint8_t *buf, int len); |
1285 | 5aca8c3b | blueswir1 | void sparc32_dma_set_reset_data(void *opaque, void (*dev_reset)(void *opaque), |
1286 | 5aca8c3b | blueswir1 | void *dev_opaque);
|
1287 | 6f7e9aec | bellard | |
1288 | b8174937 | bellard | /* cs4231.c */
|
1289 | b8174937 | bellard | void cs_init(target_phys_addr_t base, int irq, void *intctl); |
1290 | b8174937 | bellard | |
1291 | 3475187d | bellard | /* sun4u.c */
|
1292 | 3475187d | bellard | extern QEMUMachine sun4u_machine;
|
1293 | 3475187d | bellard | |
1294 | 64201201 | bellard | /* NVRAM helpers */
|
1295 | 64201201 | bellard | #include "hw/m48t59.h" |
1296 | 64201201 | bellard | |
1297 | 64201201 | bellard | void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value);
|
1298 | 64201201 | bellard | uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr); |
1299 | 64201201 | bellard | void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value);
|
1300 | 64201201 | bellard | uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr); |
1301 | 64201201 | bellard | void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value);
|
1302 | 64201201 | bellard | uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr); |
1303 | 64201201 | bellard | void NVRAM_set_string (m48t59_t *nvram, uint32_t addr,
|
1304 | 64201201 | bellard | const unsigned char *str, uint32_t max); |
1305 | 64201201 | bellard | int NVRAM_get_string (m48t59_t *nvram, uint8_t *dst, uint16_t addr, int max); |
1306 | 64201201 | bellard | void NVRAM_set_crc (m48t59_t *nvram, uint32_t addr,
|
1307 | 64201201 | bellard | uint32_t start, uint32_t count); |
1308 | 64201201 | bellard | int PPC_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
|
1309 | 64201201 | bellard | const unsigned char *arch, |
1310 | 64201201 | bellard | uint32_t RAM_size, int boot_device,
|
1311 | 64201201 | bellard | uint32_t kernel_image, uint32_t kernel_size, |
1312 | 28b9b5af | bellard | const char *cmdline, |
1313 | 64201201 | bellard | uint32_t initrd_image, uint32_t initrd_size, |
1314 | 28b9b5af | bellard | uint32_t NVRAM_image, |
1315 | 28b9b5af | bellard | int width, int height, int depth); |
1316 | 64201201 | bellard | |
1317 | 63066f4f | bellard | /* adb.c */
|
1318 | 63066f4f | bellard | |
1319 | 63066f4f | bellard | #define MAX_ADB_DEVICES 16 |
1320 | 63066f4f | bellard | |
1321 | e2733d20 | bellard | #define ADB_MAX_OUT_LEN 16 |
1322 | 63066f4f | bellard | |
1323 | e2733d20 | bellard | typedef struct ADBDevice ADBDevice; |
1324 | 63066f4f | bellard | |
1325 | e2733d20 | bellard | /* buf = NULL means polling */
|
1326 | e2733d20 | bellard | typedef int ADBDeviceRequest(ADBDevice *d, uint8_t *buf_out, |
1327 | e2733d20 | bellard | const uint8_t *buf, int len); |
1328 | 12c28fed | bellard | typedef int ADBDeviceReset(ADBDevice *d); |
1329 | 12c28fed | bellard | |
1330 | 63066f4f | bellard | struct ADBDevice {
|
1331 | 63066f4f | bellard | struct ADBBusState *bus;
|
1332 | 63066f4f | bellard | int devaddr;
|
1333 | 63066f4f | bellard | int handler;
|
1334 | e2733d20 | bellard | ADBDeviceRequest *devreq; |
1335 | 12c28fed | bellard | ADBDeviceReset *devreset; |
1336 | 63066f4f | bellard | void *opaque;
|
1337 | 63066f4f | bellard | }; |
1338 | 63066f4f | bellard | |
1339 | 63066f4f | bellard | typedef struct ADBBusState { |
1340 | 63066f4f | bellard | ADBDevice devices[MAX_ADB_DEVICES]; |
1341 | 63066f4f | bellard | int nb_devices;
|
1342 | e2733d20 | bellard | int poll_index;
|
1343 | 63066f4f | bellard | } ADBBusState; |
1344 | 63066f4f | bellard | |
1345 | e2733d20 | bellard | int adb_request(ADBBusState *s, uint8_t *buf_out,
|
1346 | e2733d20 | bellard | const uint8_t *buf, int len); |
1347 | e2733d20 | bellard | int adb_poll(ADBBusState *s, uint8_t *buf_out);
|
1348 | 63066f4f | bellard | |
1349 | 63066f4f | bellard | ADBDevice *adb_register_device(ADBBusState *s, int devaddr,
|
1350 | e2733d20 | bellard | ADBDeviceRequest *devreq, |
1351 | 12c28fed | bellard | ADBDeviceReset *devreset, |
1352 | 63066f4f | bellard | void *opaque);
|
1353 | 63066f4f | bellard | void adb_kbd_init(ADBBusState *bus);
|
1354 | 63066f4f | bellard | void adb_mouse_init(ADBBusState *bus);
|
1355 | 63066f4f | bellard | |
1356 | 63066f4f | bellard | /* cuda.c */
|
1357 | 63066f4f | bellard | |
1358 | 63066f4f | bellard | extern ADBBusState adb_bus;
|
1359 | d537cf6c | pbrook | int cuda_init(qemu_irq irq);
|
1360 | 63066f4f | bellard | |
1361 | bb36d470 | bellard | #include "hw/usb.h" |
1362 | bb36d470 | bellard | |
1363 | a594cfbf | bellard | /* usb ports of the VM */
|
1364 | a594cfbf | bellard | |
1365 | 0d92ed30 | pbrook | void qemu_register_usb_port(USBPort *port, void *opaque, int index, |
1366 | 0d92ed30 | pbrook | usb_attachfn attach); |
1367 | a594cfbf | bellard | |
1368 | 0d92ed30 | pbrook | #define VM_USB_HUB_SIZE 8 |
1369 | a594cfbf | bellard | |
1370 | a594cfbf | bellard | void do_usb_add(const char *devname); |
1371 | a594cfbf | bellard | void do_usb_del(const char *devname); |
1372 | a594cfbf | bellard | void usb_info(void); |
1373 | a594cfbf | bellard | |
1374 | 2e5d83bb | pbrook | /* scsi-disk.c */
|
1375 | 4d611c9a | pbrook | enum scsi_reason {
|
1376 | 4d611c9a | pbrook | SCSI_REASON_DONE, /* Command complete. */
|
1377 | 4d611c9a | pbrook | SCSI_REASON_DATA /* Transfer complete, more data required. */
|
1378 | 4d611c9a | pbrook | }; |
1379 | 4d611c9a | pbrook | |
1380 | 2e5d83bb | pbrook | typedef struct SCSIDevice SCSIDevice; |
1381 | a917d384 | pbrook | typedef void (*scsi_completionfn)(void *opaque, int reason, uint32_t tag, |
1382 | a917d384 | pbrook | uint32_t arg); |
1383 | 2e5d83bb | pbrook | |
1384 | 2e5d83bb | pbrook | SCSIDevice *scsi_disk_init(BlockDriverState *bdrv, |
1385 | a917d384 | pbrook | int tcq,
|
1386 | 2e5d83bb | pbrook | scsi_completionfn completion, |
1387 | 2e5d83bb | pbrook | void *opaque);
|
1388 | 2e5d83bb | pbrook | void scsi_disk_destroy(SCSIDevice *s);
|
1389 | 2e5d83bb | pbrook | |
1390 | 0fc5c15a | pbrook | int32_t scsi_send_command(SCSIDevice *s, uint32_t tag, uint8_t *buf, int lun);
|
1391 | 4d611c9a | pbrook | /* SCSI data transfers are asynchrnonous. However, unlike the block IO
|
1392 | 4d611c9a | pbrook | layer the completion routine may be called directly by
|
1393 | 4d611c9a | pbrook | scsi_{read,write}_data. */
|
1394 | a917d384 | pbrook | void scsi_read_data(SCSIDevice *s, uint32_t tag);
|
1395 | a917d384 | pbrook | int scsi_write_data(SCSIDevice *s, uint32_t tag);
|
1396 | a917d384 | pbrook | void scsi_cancel_io(SCSIDevice *s, uint32_t tag);
|
1397 | a917d384 | pbrook | uint8_t *scsi_get_buf(SCSIDevice *s, uint32_t tag); |
1398 | 2e5d83bb | pbrook | |
1399 | 7d8406be | pbrook | /* lsi53c895a.c */
|
1400 | 7d8406be | pbrook | void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id); |
1401 | 7d8406be | pbrook | void *lsi_scsi_init(PCIBus *bus, int devfn); |
1402 | 7d8406be | pbrook | |
1403 | b5ff1b31 | bellard | /* integratorcp.c */
|
1404 | 3371d272 | pbrook | extern QEMUMachine integratorcp_machine;
|
1405 | b5ff1b31 | bellard | |
1406 | cdbdb648 | pbrook | /* versatilepb.c */
|
1407 | cdbdb648 | pbrook | extern QEMUMachine versatilepb_machine;
|
1408 | 16406950 | pbrook | extern QEMUMachine versatileab_machine;
|
1409 | cdbdb648 | pbrook | |
1410 | e69954b9 | pbrook | /* realview.c */
|
1411 | e69954b9 | pbrook | extern QEMUMachine realview_machine;
|
1412 | e69954b9 | pbrook | |
1413 | b00052e4 | balrog | /* spitz.c */
|
1414 | b00052e4 | balrog | extern QEMUMachine akitapda_machine;
|
1415 | b00052e4 | balrog | extern QEMUMachine spitzpda_machine;
|
1416 | b00052e4 | balrog | extern QEMUMachine borzoipda_machine;
|
1417 | b00052e4 | balrog | extern QEMUMachine terrierpda_machine;
|
1418 | b00052e4 | balrog | |
1419 | daa57963 | bellard | /* ps2.c */
|
1420 | daa57963 | bellard | void *ps2_kbd_init(void (*update_irq)(void *, int), void *update_arg); |
1421 | daa57963 | bellard | void *ps2_mouse_init(void (*update_irq)(void *, int), void *update_arg); |
1422 | daa57963 | bellard | void ps2_write_mouse(void *, int val); |
1423 | daa57963 | bellard | void ps2_write_keyboard(void *, int val); |
1424 | daa57963 | bellard | uint32_t ps2_read_data(void *);
|
1425 | daa57963 | bellard | void ps2_queue(void *, int b); |
1426 | f94f5d71 | pbrook | void ps2_keyboard_set_translation(void *opaque, int mode); |
1427 | 548df2ac | ths | void ps2_mouse_fake_event(void *opaque); |
1428 | daa57963 | bellard | |
1429 | 80337b66 | bellard | /* smc91c111.c */
|
1430 | d537cf6c | pbrook | void smc91c111_init(NICInfo *, uint32_t, qemu_irq);
|
1431 | 80337b66 | bellard | |
1432 | 7e1543c2 | pbrook | /* pl031.c */
|
1433 | 7e1543c2 | pbrook | void pl031_init(uint32_t base, qemu_irq irq);
|
1434 | 7e1543c2 | pbrook | |
1435 | bdd5003a | pbrook | /* pl110.c */
|
1436 | d537cf6c | pbrook | void *pl110_init(DisplayState *ds, uint32_t base, qemu_irq irq, int); |
1437 | bdd5003a | pbrook | |
1438 | cdbdb648 | pbrook | /* pl011.c */
|
1439 | d537cf6c | pbrook | void pl011_init(uint32_t base, qemu_irq irq, CharDriverState *chr);
|
1440 | cdbdb648 | pbrook | |
1441 | cdbdb648 | pbrook | /* pl050.c */
|
1442 | d537cf6c | pbrook | void pl050_init(uint32_t base, qemu_irq irq, int is_mouse); |
1443 | cdbdb648 | pbrook | |
1444 | cdbdb648 | pbrook | /* pl080.c */
|
1445 | d537cf6c | pbrook | void *pl080_init(uint32_t base, qemu_irq irq, int nchannels); |
1446 | cdbdb648 | pbrook | |
1447 | a1bb27b1 | pbrook | /* pl181.c */
|
1448 | a1bb27b1 | pbrook | void pl181_init(uint32_t base, BlockDriverState *bd,
|
1449 | d537cf6c | pbrook | qemu_irq irq0, qemu_irq irq1); |
1450 | a1bb27b1 | pbrook | |
1451 | cdbdb648 | pbrook | /* pl190.c */
|
1452 | d537cf6c | pbrook | qemu_irq *pl190_init(uint32_t base, qemu_irq irq, qemu_irq fiq); |
1453 | cdbdb648 | pbrook | |
1454 | cdbdb648 | pbrook | /* arm-timer.c */
|
1455 | d537cf6c | pbrook | void sp804_init(uint32_t base, qemu_irq irq);
|
1456 | d537cf6c | pbrook | void icp_pit_init(uint32_t base, qemu_irq *pic, int irq); |
1457 | cdbdb648 | pbrook | |
1458 | e69954b9 | pbrook | /* arm_sysctl.c */
|
1459 | e69954b9 | pbrook | void arm_sysctl_init(uint32_t base, uint32_t sys_id);
|
1460 | e69954b9 | pbrook | |
1461 | e69954b9 | pbrook | /* arm_gic.c */
|
1462 | d537cf6c | pbrook | qemu_irq *arm_gic_init(uint32_t base, qemu_irq parent_irq); |
1463 | e69954b9 | pbrook | |
1464 | 16406950 | pbrook | /* arm_boot.c */
|
1465 | 16406950 | pbrook | |
1466 | daf90626 | pbrook | void arm_load_kernel(CPUState *env, int ram_size, const char *kernel_filename, |
1467 | 16406950 | pbrook | const char *kernel_cmdline, const char *initrd_filename, |
1468 | 9d551997 | balrog | int board_id, target_phys_addr_t loader_start);
|
1469 | 16406950 | pbrook | |
1470 | 27c7ca7e | bellard | /* sh7750.c */
|
1471 | 27c7ca7e | bellard | struct SH7750State;
|
1472 | 27c7ca7e | bellard | |
1473 | 008a8818 | pbrook | struct SH7750State *sh7750_init(CPUState * cpu);
|
1474 | 27c7ca7e | bellard | |
1475 | 27c7ca7e | bellard | typedef struct { |
1476 | 27c7ca7e | bellard | /* The callback will be triggered if any of the designated lines change */
|
1477 | 27c7ca7e | bellard | uint16_t portamask_trigger; |
1478 | 27c7ca7e | bellard | uint16_t portbmask_trigger; |
1479 | 27c7ca7e | bellard | /* Return 0 if no action was taken */
|
1480 | 27c7ca7e | bellard | int (*port_change_cb) (uint16_t porta, uint16_t portb,
|
1481 | 27c7ca7e | bellard | uint16_t * periph_pdtra, |
1482 | 27c7ca7e | bellard | uint16_t * periph_portdira, |
1483 | 27c7ca7e | bellard | uint16_t * periph_pdtrb, |
1484 | 27c7ca7e | bellard | uint16_t * periph_portdirb); |
1485 | 27c7ca7e | bellard | } sh7750_io_device; |
1486 | 27c7ca7e | bellard | |
1487 | 27c7ca7e | bellard | int sh7750_register_io_device(struct SH7750State *s, |
1488 | 27c7ca7e | bellard | sh7750_io_device * device); |
1489 | 27c7ca7e | bellard | /* tc58128.c */
|
1490 | 27c7ca7e | bellard | int tc58128_init(struct SH7750State *s, char *zone1, char *zone2); |
1491 | 27c7ca7e | bellard | |
1492 | 29133e9a | bellard | /* NOR flash devices */
|
1493 | 86f55663 | j_mayer | #define MAX_PFLASH 4 |
1494 | 86f55663 | j_mayer | extern BlockDriverState *pflash_table[MAX_PFLASH];
|
1495 | 29133e9a | bellard | typedef struct pflash_t pflash_t; |
1496 | 29133e9a | bellard | |
1497 | 71db710f | blueswir1 | pflash_t *pflash_register (target_phys_addr_t base, ram_addr_t off, |
1498 | 29133e9a | bellard | BlockDriverState *bs, |
1499 | 71db710f | blueswir1 | uint32_t sector_len, int nb_blocs, int width, |
1500 | 29133e9a | bellard | uint16_t id0, uint16_t id1, |
1501 | 29133e9a | bellard | uint16_t id2, uint16_t id3); |
1502 | 29133e9a | bellard | |
1503 | 3e3d5815 | balrog | /* nand.c */
|
1504 | 3e3d5815 | balrog | struct nand_flash_s;
|
1505 | 3e3d5815 | balrog | struct nand_flash_s *nand_init(int manf_id, int chip_id); |
1506 | 3e3d5815 | balrog | void nand_done(struct nand_flash_s *s); |
1507 | 3e3d5815 | balrog | void nand_setpins(struct nand_flash_s *s, |
1508 | 3e3d5815 | balrog | int cle, int ale, int ce, int wp, int gnd); |
1509 | 3e3d5815 | balrog | void nand_getpins(struct nand_flash_s *s, int *rb); |
1510 | 3e3d5815 | balrog | void nand_setio(struct nand_flash_s *s, uint8_t value); |
1511 | 3e3d5815 | balrog | uint8_t nand_getio(struct nand_flash_s *s);
|
1512 | 3e3d5815 | balrog | |
1513 | 3e3d5815 | balrog | #define NAND_MFR_TOSHIBA 0x98 |
1514 | 3e3d5815 | balrog | #define NAND_MFR_SAMSUNG 0xec |
1515 | 3e3d5815 | balrog | #define NAND_MFR_FUJITSU 0x04 |
1516 | 3e3d5815 | balrog | #define NAND_MFR_NATIONAL 0x8f |
1517 | 3e3d5815 | balrog | #define NAND_MFR_RENESAS 0x07 |
1518 | 3e3d5815 | balrog | #define NAND_MFR_STMICRO 0x20 |
1519 | 3e3d5815 | balrog | #define NAND_MFR_HYNIX 0xad |
1520 | 3e3d5815 | balrog | #define NAND_MFR_MICRON 0x2c |
1521 | 3e3d5815 | balrog | |
1522 | 3e3d5815 | balrog | #include "ecc.h" |
1523 | 3e3d5815 | balrog | |
1524 | 2a1d1880 | balrog | /* GPIO */
|
1525 | 2a1d1880 | balrog | typedef void (*gpio_handler_t)(int line, int level, void *opaque); |
1526 | 2a1d1880 | balrog | |
1527 | fd5a3b33 | balrog | /* ads7846.c */
|
1528 | fd5a3b33 | balrog | struct ads7846_state_s;
|
1529 | fd5a3b33 | balrog | uint32_t ads7846_read(void *opaque);
|
1530 | fd5a3b33 | balrog | void ads7846_write(void *opaque, uint32_t value); |
1531 | fd5a3b33 | balrog | struct ads7846_state_s *ads7846_init(qemu_irq penirq);
|
1532 | fd5a3b33 | balrog | |
1533 | c824cacd | balrog | /* max111x.c */
|
1534 | c824cacd | balrog | struct max111x_s;
|
1535 | c824cacd | balrog | uint32_t max111x_read(void *opaque);
|
1536 | c824cacd | balrog | void max111x_write(void *opaque, uint32_t value); |
1537 | c824cacd | balrog | struct max111x_s *max1110_init(qemu_irq cb);
|
1538 | c824cacd | balrog | struct max111x_s *max1111_init(qemu_irq cb);
|
1539 | c824cacd | balrog | void max111x_set_input(struct max111x_s *s, int line, uint8_t value); |
1540 | c824cacd | balrog | |
1541 | 201a51fc | balrog | /* PCMCIA/Cardbus */
|
1542 | 201a51fc | balrog | |
1543 | 201a51fc | balrog | struct pcmcia_socket_s {
|
1544 | 201a51fc | balrog | qemu_irq irq; |
1545 | 201a51fc | balrog | int attached;
|
1546 | 201a51fc | balrog | const char *slot_string; |
1547 | 201a51fc | balrog | const char *card_string; |
1548 | 201a51fc | balrog | }; |
1549 | 201a51fc | balrog | |
1550 | 201a51fc | balrog | void pcmcia_socket_register(struct pcmcia_socket_s *socket); |
1551 | 201a51fc | balrog | void pcmcia_socket_unregister(struct pcmcia_socket_s *socket); |
1552 | 201a51fc | balrog | void pcmcia_info(void); |
1553 | 201a51fc | balrog | |
1554 | 201a51fc | balrog | struct pcmcia_card_s {
|
1555 | 201a51fc | balrog | void *state;
|
1556 | 201a51fc | balrog | struct pcmcia_socket_s *slot;
|
1557 | 201a51fc | balrog | int (*attach)(void *state); |
1558 | 201a51fc | balrog | int (*detach)(void *state); |
1559 | 201a51fc | balrog | const uint8_t *cis;
|
1560 | 201a51fc | balrog | int cis_len;
|
1561 | 201a51fc | balrog | |
1562 | 201a51fc | balrog | /* Only valid if attached */
|
1563 | 9e315fa9 | balrog | uint8_t (*attr_read)(void *state, uint32_t address);
|
1564 | 9e315fa9 | balrog | void (*attr_write)(void *state, uint32_t address, uint8_t value); |
1565 | 9e315fa9 | balrog | uint16_t (*common_read)(void *state, uint32_t address);
|
1566 | 9e315fa9 | balrog | void (*common_write)(void *state, uint32_t address, uint16_t value); |
1567 | 9e315fa9 | balrog | uint16_t (*io_read)(void *state, uint32_t address);
|
1568 | 9e315fa9 | balrog | void (*io_write)(void *state, uint32_t address, uint16_t value); |
1569 | 201a51fc | balrog | }; |
1570 | 201a51fc | balrog | |
1571 | 201a51fc | balrog | #define CISTPL_DEVICE 0x01 /* 5V Device Information Tuple */ |
1572 | 201a51fc | balrog | #define CISTPL_NO_LINK 0x14 /* No Link Tuple */ |
1573 | 201a51fc | balrog | #define CISTPL_VERS_1 0x15 /* Level 1 Version Tuple */ |
1574 | 201a51fc | balrog | #define CISTPL_JEDEC_C 0x18 /* JEDEC ID Tuple */ |
1575 | 201a51fc | balrog | #define CISTPL_JEDEC_A 0x19 /* JEDEC ID Tuple */ |
1576 | 201a51fc | balrog | #define CISTPL_CONFIG 0x1a /* Configuration Tuple */ |
1577 | 201a51fc | balrog | #define CISTPL_CFTABLE_ENTRY 0x1b /* 16-bit PCCard Configuration */ |
1578 | 201a51fc | balrog | #define CISTPL_DEVICE_OC 0x1c /* Additional Device Information */ |
1579 | 201a51fc | balrog | #define CISTPL_DEVICE_OA 0x1d /* Additional Device Information */ |
1580 | 201a51fc | balrog | #define CISTPL_DEVICE_GEO 0x1e /* Additional Device Information */ |
1581 | 201a51fc | balrog | #define CISTPL_DEVICE_GEO_A 0x1f /* Additional Device Information */ |
1582 | 201a51fc | balrog | #define CISTPL_MANFID 0x20 /* Manufacture ID Tuple */ |
1583 | 201a51fc | balrog | #define CISTPL_FUNCID 0x21 /* Function ID Tuple */ |
1584 | 201a51fc | balrog | #define CISTPL_FUNCE 0x22 /* Function Extension Tuple */ |
1585 | 201a51fc | balrog | #define CISTPL_END 0xff /* Tuple End */ |
1586 | 201a51fc | balrog | #define CISTPL_ENDMARK 0xff |
1587 | 201a51fc | balrog | |
1588 | 201a51fc | balrog | /* dscm1xxxx.c */
|
1589 | 201a51fc | balrog | struct pcmcia_card_s *dscm1xxxx_init(BlockDriverState *bdrv);
|
1590 | 201a51fc | balrog | |
1591 | 6963d7af | pbrook | /* ptimer.c */
|
1592 | 6963d7af | pbrook | typedef struct ptimer_state ptimer_state; |
1593 | 6963d7af | pbrook | typedef void (*ptimer_cb)(void *opaque); |
1594 | 6963d7af | pbrook | |
1595 | 6963d7af | pbrook | ptimer_state *ptimer_init(QEMUBH *bh); |
1596 | 6963d7af | pbrook | void ptimer_set_period(ptimer_state *s, int64_t period);
|
1597 | 6963d7af | pbrook | void ptimer_set_freq(ptimer_state *s, uint32_t freq);
|
1598 | 8d05ea8a | blueswir1 | void ptimer_set_limit(ptimer_state *s, uint64_t limit, int reload); |
1599 | 8d05ea8a | blueswir1 | uint64_t ptimer_get_count(ptimer_state *s); |
1600 | 8d05ea8a | blueswir1 | void ptimer_set_count(ptimer_state *s, uint64_t count);
|
1601 | 6963d7af | pbrook | void ptimer_run(ptimer_state *s, int oneshot); |
1602 | 6963d7af | pbrook | void ptimer_stop(ptimer_state *s);
|
1603 | 8d05ea8a | blueswir1 | void qemu_put_ptimer(QEMUFile *f, ptimer_state *s);
|
1604 | 8d05ea8a | blueswir1 | void qemu_get_ptimer(QEMUFile *f, ptimer_state *s);
|
1605 | 6963d7af | pbrook | |
1606 | c1713132 | balrog | #include "hw/pxa.h" |
1607 | c1713132 | balrog | |
1608 | 20dcee94 | pbrook | /* mcf_uart.c */
|
1609 | 20dcee94 | pbrook | uint32_t mcf_uart_read(void *opaque, target_phys_addr_t addr);
|
1610 | 20dcee94 | pbrook | void mcf_uart_write(void *opaque, target_phys_addr_t addr, uint32_t val); |
1611 | 20dcee94 | pbrook | void *mcf_uart_init(qemu_irq irq, CharDriverState *chr);
|
1612 | 20dcee94 | pbrook | void mcf_uart_mm_init(target_phys_addr_t base, qemu_irq irq,
|
1613 | 20dcee94 | pbrook | CharDriverState *chr); |
1614 | 20dcee94 | pbrook | |
1615 | 20dcee94 | pbrook | /* mcf_intc.c */
|
1616 | 20dcee94 | pbrook | qemu_irq *mcf_intc_init(target_phys_addr_t base, CPUState *env); |
1617 | 20dcee94 | pbrook | |
1618 | 7e049b8a | pbrook | /* mcf_fec.c */
|
1619 | 7e049b8a | pbrook | void mcf_fec_init(NICInfo *nd, target_phys_addr_t base, qemu_irq *irq);
|
1620 | 7e049b8a | pbrook | |
1621 | 0633879f | pbrook | /* mcf5206.c */
|
1622 | 0633879f | pbrook | qemu_irq *mcf5206_init(uint32_t base, CPUState *env); |
1623 | 0633879f | pbrook | |
1624 | 0633879f | pbrook | /* an5206.c */
|
1625 | 0633879f | pbrook | extern QEMUMachine an5206_machine;
|
1626 | 0633879f | pbrook | |
1627 | 20dcee94 | pbrook | /* mcf5208.c */
|
1628 | 20dcee94 | pbrook | extern QEMUMachine mcf5208evb_machine;
|
1629 | 20dcee94 | pbrook | |
1630 | 4046d913 | pbrook | #include "gdbstub.h" |
1631 | 4046d913 | pbrook | |
1632 | ea2384d3 | bellard | #endif /* defined(QEMU_TOOL) */ |
1633 | ea2384d3 | bellard | |
1634 | c4b1fcc0 | bellard | /* monitor.c */
|
1635 | 82c643ff | bellard | void monitor_init(CharDriverState *hd, int show_banner); |
1636 | ea2384d3 | bellard | void term_puts(const char *str); |
1637 | ea2384d3 | bellard | void term_vprintf(const char *fmt, va_list ap); |
1638 | 40c3bac3 | bellard | void term_printf(const char *fmt, ...) __attribute__ ((__format__ (__printf__, 1, 2))); |
1639 | fef30743 | ths | void term_print_filename(const char *filename); |
1640 | c4b1fcc0 | bellard | void term_flush(void); |
1641 | c4b1fcc0 | bellard | void term_print_help(void); |
1642 | ea2384d3 | bellard | void monitor_readline(const char *prompt, int is_password, |
1643 | ea2384d3 | bellard | char *buf, int buf_size); |
1644 | ea2384d3 | bellard | |
1645 | ea2384d3 | bellard | /* readline.c */
|
1646 | ea2384d3 | bellard | typedef void ReadLineFunc(void *opaque, const char *str); |
1647 | ea2384d3 | bellard | |
1648 | ea2384d3 | bellard | extern int completion_index; |
1649 | ea2384d3 | bellard | void add_completion(const char *str); |
1650 | ea2384d3 | bellard | void readline_handle_byte(int ch); |
1651 | ea2384d3 | bellard | void readline_find_completion(const char *cmdline); |
1652 | ea2384d3 | bellard | const char *readline_get_history(unsigned int index); |
1653 | ea2384d3 | bellard | void readline_start(const char *prompt, int is_password, |
1654 | ea2384d3 | bellard | ReadLineFunc *readline_func, void *opaque);
|
1655 | c4b1fcc0 | bellard | |
1656 | 5e6ad6f9 | bellard | void kqemu_record_dump(void); |
1657 | 5e6ad6f9 | bellard | |
1658 | fc01f7e7 | bellard | #endif /* VL_H */ |