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/*
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* QEMU KVM support
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*
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* Copyright (C) 2006-2008 Qumranet Technologies
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* Copyright IBM, Corp. 2008
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*
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* Authors:
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* Anthony Liguori <aliguori@us.ibm.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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*/
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#include <sys/types.h> |
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#include <sys/ioctl.h> |
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#include <sys/mman.h> |
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#include <sys/utsname.h> |
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#include <linux/kvm.h> |
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#include <linux/kvm_para.h> |
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#include "qemu-common.h" |
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#include "sysemu.h" |
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#include "kvm.h" |
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#include "cpu.h" |
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#include "gdbstub.h" |
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#include "host-utils.h" |
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#include "hw/pc.h" |
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#include "hw/apic.h" |
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#include "ioport.h" |
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#include "hyperv.h" |
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//#define DEBUG_KVM
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#ifdef DEBUG_KVM
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#define DPRINTF(fmt, ...) \
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do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0) |
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#else
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#define DPRINTF(fmt, ...) \
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do { } while (0) |
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#endif
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#define MSR_KVM_WALL_CLOCK 0x11 |
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#define MSR_KVM_SYSTEM_TIME 0x12 |
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#ifndef BUS_MCEERR_AR
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#define BUS_MCEERR_AR 4 |
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#endif
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#ifndef BUS_MCEERR_AO
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#define BUS_MCEERR_AO 5 |
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#endif
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const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
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KVM_CAP_INFO(SET_TSS_ADDR), |
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KVM_CAP_INFO(EXT_CPUID), |
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KVM_CAP_INFO(MP_STATE), |
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KVM_CAP_LAST_INFO |
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}; |
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|
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static bool has_msr_star; |
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static bool has_msr_hsave_pa; |
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static bool has_msr_tsc_deadline; |
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static bool has_msr_async_pf_en; |
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static bool has_msr_misc_enable; |
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static int lm_capable_kernel; |
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|
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static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max) |
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{ |
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struct kvm_cpuid2 *cpuid;
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int r, size;
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size = sizeof(*cpuid) + max * sizeof(*cpuid->entries); |
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cpuid = (struct kvm_cpuid2 *)g_malloc0(size);
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cpuid->nent = max; |
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r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid); |
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if (r == 0 && cpuid->nent >= max) { |
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r = -E2BIG; |
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} |
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if (r < 0) { |
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if (r == -E2BIG) {
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g_free(cpuid); |
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return NULL; |
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} else {
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fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
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strerror(-r)); |
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exit(1);
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} |
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} |
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return cpuid;
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} |
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struct kvm_para_features {
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int cap;
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int feature;
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} para_features[] = { |
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{ KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE }, |
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{ KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY }, |
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{ KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP }, |
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{ KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF }, |
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{ -1, -1 } |
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}; |
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static int get_para_features(KVMState *s) |
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{ |
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int i, features = 0; |
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for (i = 0; i < ARRAY_SIZE(para_features) - 1; i++) { |
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if (kvm_check_extension(s, para_features[i].cap)) {
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features |= (1 << para_features[i].feature);
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} |
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} |
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return features;
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} |
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uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function, |
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uint32_t index, int reg)
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{ |
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struct kvm_cpuid2 *cpuid;
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int i, max;
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uint32_t ret = 0;
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uint32_t cpuid_1_edx; |
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int has_kvm_features = 0; |
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max = 1;
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while ((cpuid = try_get_cpuid(s, max)) == NULL) { |
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max *= 2;
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} |
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for (i = 0; i < cpuid->nent; ++i) { |
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if (cpuid->entries[i].function == function &&
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cpuid->entries[i].index == index) { |
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if (cpuid->entries[i].function == KVM_CPUID_FEATURES) {
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has_kvm_features = 1;
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} |
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switch (reg) {
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case R_EAX:
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ret = cpuid->entries[i].eax; |
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break;
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case R_EBX:
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ret = cpuid->entries[i].ebx; |
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break;
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case R_ECX:
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ret = cpuid->entries[i].ecx; |
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break;
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case R_EDX:
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ret = cpuid->entries[i].edx; |
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switch (function) {
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case 1: |
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/* KVM before 2.6.30 misreports the following features */
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ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA; |
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break;
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case 0x80000001: |
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/* On Intel, kvm returns cpuid according to the Intel spec,
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* so add missing bits according to the AMD spec:
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*/
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cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX); |
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ret |= cpuid_1_edx & 0x183f7ff;
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break;
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} |
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break;
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} |
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} |
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} |
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g_free(cpuid); |
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/* fallback for older kernels */
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if (!has_kvm_features && (function == KVM_CPUID_FEATURES)) {
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ret = get_para_features(s); |
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} |
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return ret;
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} |
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typedef struct HWPoisonPage { |
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ram_addr_t ram_addr; |
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QLIST_ENTRY(HWPoisonPage) list; |
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} HWPoisonPage; |
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static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
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QLIST_HEAD_INITIALIZER(hwpoison_page_list); |
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static void kvm_unpoison_all(void *param) |
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{ |
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HWPoisonPage *page, *next_page; |
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QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) { |
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QLIST_REMOVE(page, list); |
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qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE); |
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g_free(page); |
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} |
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} |
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static void kvm_hwpoison_page_add(ram_addr_t ram_addr) |
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{ |
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HWPoisonPage *page; |
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QLIST_FOREACH(page, &hwpoison_page_list, list) { |
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if (page->ram_addr == ram_addr) {
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return;
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} |
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} |
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page = g_malloc(sizeof(HWPoisonPage));
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page->ram_addr = ram_addr; |
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QLIST_INSERT_HEAD(&hwpoison_page_list, page, list); |
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} |
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static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap, |
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int *max_banks)
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{ |
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int r;
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r = kvm_check_extension(s, KVM_CAP_MCE); |
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if (r > 0) { |
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*max_banks = r; |
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return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
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} |
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return -ENOSYS;
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} |
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static void kvm_mce_inject(CPUState *env, target_phys_addr_t paddr, int code) |
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{ |
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uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN | |
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MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S; |
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uint64_t mcg_status = MCG_STATUS_MCIP; |
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if (code == BUS_MCEERR_AR) {
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status |= MCI_STATUS_AR | 0x134;
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mcg_status |= MCG_STATUS_EIPV; |
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} else {
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status |= 0xc0;
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mcg_status |= MCG_STATUS_RIPV; |
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} |
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cpu_x86_inject_mce(NULL, env, 9, status, mcg_status, paddr, |
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(MCM_ADDR_PHYS << 6) | 0xc, |
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cpu_x86_support_mca_broadcast(env) ? |
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MCE_INJECT_BROADCAST : 0);
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} |
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static void hardware_memory_error(void) |
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{ |
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fprintf(stderr, "Hardware memory error!\n");
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exit(1);
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} |
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int kvm_arch_on_sigbus_vcpu(CPUState *env, int code, void *addr) |
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{ |
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ram_addr_t ram_addr; |
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target_phys_addr_t paddr; |
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if ((env->mcg_cap & MCG_SER_P) && addr
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&& (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) { |
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if (qemu_ram_addr_from_host(addr, &ram_addr) ||
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!kvm_physical_memory_addr_from_host(env->kvm_state, addr, &paddr)) { |
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fprintf(stderr, "Hardware memory error for memory used by "
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"QEMU itself instead of guest system!\n");
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/* Hope we are lucky for AO MCE */
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if (code == BUS_MCEERR_AO) {
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return 0; |
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} else {
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hardware_memory_error(); |
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} |
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} |
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kvm_hwpoison_page_add(ram_addr); |
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kvm_mce_inject(env, paddr, code); |
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} else {
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if (code == BUS_MCEERR_AO) {
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return 0; |
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} else if (code == BUS_MCEERR_AR) { |
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hardware_memory_error(); |
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} else {
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return 1; |
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} |
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} |
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return 0; |
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} |
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int kvm_arch_on_sigbus(int code, void *addr) |
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{ |
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if ((first_cpu->mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
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ram_addr_t ram_addr; |
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target_phys_addr_t paddr; |
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/* Hope we are lucky for AO MCE */
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if (qemu_ram_addr_from_host(addr, &ram_addr) ||
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!kvm_physical_memory_addr_from_host(first_cpu->kvm_state, addr, |
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&paddr)) { |
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fprintf(stderr, "Hardware memory error for memory used by "
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"QEMU itself instead of guest system!: %p\n", addr);
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return 0; |
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} |
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kvm_hwpoison_page_add(ram_addr); |
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kvm_mce_inject(first_cpu, paddr, code); |
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} else {
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if (code == BUS_MCEERR_AO) {
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return 0; |
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} else if (code == BUS_MCEERR_AR) { |
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hardware_memory_error(); |
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} else {
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return 1; |
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} |
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} |
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return 0; |
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} |
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static int kvm_inject_mce_oldstyle(CPUState *env) |
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{ |
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if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
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unsigned int bank, bank_num = env->mcg_cap & 0xff; |
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struct kvm_x86_mce mce;
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env->exception_injected = -1;
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/*
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* There must be at least one bank in use if an MCE is pending.
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* Find it and use its values for the event injection.
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*/
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for (bank = 0; bank < bank_num; bank++) { |
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if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) { |
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break;
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} |
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} |
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assert(bank < bank_num); |
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mce.bank = bank; |
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mce.status = env->mce_banks[bank * 4 + 1]; |
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mce.mcg_status = env->mcg_status; |
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mce.addr = env->mce_banks[bank * 4 + 2]; |
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mce.misc = env->mce_banks[bank * 4 + 3]; |
333 |
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return kvm_vcpu_ioctl(env, KVM_X86_SET_MCE, &mce);
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} |
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return 0; |
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} |
338 |
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static void cpu_update_state(void *opaque, int running, RunState state) |
340 |
{ |
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CPUState *env = opaque; |
342 |
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if (running) {
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env->tsc_valid = false;
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} |
346 |
} |
347 |
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int kvm_arch_init_vcpu(CPUState *env)
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{ |
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struct {
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struct kvm_cpuid2 cpuid;
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struct kvm_cpuid_entry2 entries[100]; |
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} QEMU_PACKED cpuid_data; |
354 |
KVMState *s = env->kvm_state; |
355 |
uint32_t limit, i, j, cpuid_i; |
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uint32_t unused; |
357 |
struct kvm_cpuid_entry2 *c;
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uint32_t signature[3];
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int r;
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env->cpuid_features &= kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX); |
362 |
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i = env->cpuid_ext_features & CPUID_EXT_HYPERVISOR; |
364 |
env->cpuid_ext_features &= kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX); |
365 |
env->cpuid_ext_features |= i; |
366 |
|
367 |
env->cpuid_ext2_features &= kvm_arch_get_supported_cpuid(s, 0x80000001,
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0, R_EDX);
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env->cpuid_ext3_features &= kvm_arch_get_supported_cpuid(s, 0x80000001,
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0, R_ECX);
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env->cpuid_svm_features &= kvm_arch_get_supported_cpuid(s, 0x8000000A,
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0, R_EDX);
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374 |
cpuid_i = 0;
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375 |
|
376 |
/* Paravirtualization CPUIDs */
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377 |
c = &cpuid_data.entries[cpuid_i++]; |
378 |
memset(c, 0, sizeof(*c)); |
379 |
c->function = KVM_CPUID_SIGNATURE; |
380 |
if (!hyperv_enabled()) {
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381 |
memcpy(signature, "KVMKVMKVM\0\0\0", 12); |
382 |
c->eax = 0;
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383 |
} else {
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384 |
memcpy(signature, "Microsoft Hv", 12); |
385 |
c->eax = HYPERV_CPUID_MIN; |
386 |
} |
387 |
c->ebx = signature[0];
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388 |
c->ecx = signature[1];
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389 |
c->edx = signature[2];
|
390 |
|
391 |
c = &cpuid_data.entries[cpuid_i++]; |
392 |
memset(c, 0, sizeof(*c)); |
393 |
c->function = KVM_CPUID_FEATURES; |
394 |
c->eax = env->cpuid_kvm_features & |
395 |
kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
|
396 |
|
397 |
if (hyperv_enabled()) {
|
398 |
memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12); |
399 |
c->eax = signature[0];
|
400 |
|
401 |
c = &cpuid_data.entries[cpuid_i++]; |
402 |
memset(c, 0, sizeof(*c)); |
403 |
c->function = HYPERV_CPUID_VERSION; |
404 |
c->eax = 0x00001bbc;
|
405 |
c->ebx = 0x00060001;
|
406 |
|
407 |
c = &cpuid_data.entries[cpuid_i++]; |
408 |
memset(c, 0, sizeof(*c)); |
409 |
c->function = HYPERV_CPUID_FEATURES; |
410 |
if (hyperv_relaxed_timing_enabled()) {
|
411 |
c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE; |
412 |
} |
413 |
if (hyperv_vapic_recommended()) {
|
414 |
c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE; |
415 |
c->eax |= HV_X64_MSR_APIC_ACCESS_AVAILABLE; |
416 |
} |
417 |
|
418 |
c = &cpuid_data.entries[cpuid_i++]; |
419 |
memset(c, 0, sizeof(*c)); |
420 |
c->function = HYPERV_CPUID_ENLIGHTMENT_INFO; |
421 |
if (hyperv_relaxed_timing_enabled()) {
|
422 |
c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED; |
423 |
} |
424 |
if (hyperv_vapic_recommended()) {
|
425 |
c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED; |
426 |
} |
427 |
c->ebx = hyperv_get_spinlock_retries(); |
428 |
|
429 |
c = &cpuid_data.entries[cpuid_i++]; |
430 |
memset(c, 0, sizeof(*c)); |
431 |
c->function = HYPERV_CPUID_IMPLEMENT_LIMITS; |
432 |
c->eax = 0x40;
|
433 |
c->ebx = 0x40;
|
434 |
|
435 |
c = &cpuid_data.entries[cpuid_i++]; |
436 |
memset(c, 0, sizeof(*c)); |
437 |
c->function = KVM_CPUID_SIGNATURE_NEXT; |
438 |
memcpy(signature, "KVMKVMKVM\0\0\0", 12); |
439 |
c->eax = 0;
|
440 |
c->ebx = signature[0];
|
441 |
c->ecx = signature[1];
|
442 |
c->edx = signature[2];
|
443 |
} |
444 |
|
445 |
has_msr_async_pf_en = c->eax & (1 << KVM_FEATURE_ASYNC_PF);
|
446 |
|
447 |
cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused); |
448 |
|
449 |
for (i = 0; i <= limit; i++) { |
450 |
c = &cpuid_data.entries[cpuid_i++]; |
451 |
|
452 |
switch (i) {
|
453 |
case 2: { |
454 |
/* Keep reading function 2 till all the input is received */
|
455 |
int times;
|
456 |
|
457 |
c->function = i; |
458 |
c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC | |
459 |
KVM_CPUID_FLAG_STATE_READ_NEXT; |
460 |
cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
|
461 |
times = c->eax & 0xff;
|
462 |
|
463 |
for (j = 1; j < times; ++j) { |
464 |
c = &cpuid_data.entries[cpuid_i++]; |
465 |
c->function = i; |
466 |
c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC; |
467 |
cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
|
468 |
} |
469 |
break;
|
470 |
} |
471 |
case 4: |
472 |
case 0xb: |
473 |
case 0xd: |
474 |
for (j = 0; ; j++) { |
475 |
if (i == 0xd && j == 64) { |
476 |
break;
|
477 |
} |
478 |
c->function = i; |
479 |
c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX; |
480 |
c->index = j; |
481 |
cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx); |
482 |
|
483 |
if (i == 4 && c->eax == 0) { |
484 |
break;
|
485 |
} |
486 |
if (i == 0xb && !(c->ecx & 0xff00)) { |
487 |
break;
|
488 |
} |
489 |
if (i == 0xd && c->eax == 0) { |
490 |
continue;
|
491 |
} |
492 |
c = &cpuid_data.entries[cpuid_i++]; |
493 |
} |
494 |
break;
|
495 |
default:
|
496 |
c->function = i; |
497 |
c->flags = 0;
|
498 |
cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
|
499 |
break;
|
500 |
} |
501 |
} |
502 |
cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused); |
503 |
|
504 |
for (i = 0x80000000; i <= limit; i++) { |
505 |
c = &cpuid_data.entries[cpuid_i++]; |
506 |
|
507 |
c->function = i; |
508 |
c->flags = 0;
|
509 |
cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
|
510 |
} |
511 |
|
512 |
/* Call Centaur's CPUID instructions they are supported. */
|
513 |
if (env->cpuid_xlevel2 > 0) { |
514 |
env->cpuid_ext4_features &= |
515 |
kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX); |
516 |
cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused); |
517 |
|
518 |
for (i = 0xC0000000; i <= limit; i++) { |
519 |
c = &cpuid_data.entries[cpuid_i++]; |
520 |
|
521 |
c->function = i; |
522 |
c->flags = 0;
|
523 |
cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
|
524 |
} |
525 |
} |
526 |
|
527 |
cpuid_data.cpuid.nent = cpuid_i; |
528 |
|
529 |
if (((env->cpuid_version >> 8)&0xF) >= 6 |
530 |
&& (env->cpuid_features&(CPUID_MCE|CPUID_MCA)) == (CPUID_MCE|CPUID_MCA) |
531 |
&& kvm_check_extension(env->kvm_state, KVM_CAP_MCE) > 0) {
|
532 |
uint64_t mcg_cap; |
533 |
int banks;
|
534 |
int ret;
|
535 |
|
536 |
ret = kvm_get_mce_cap_supported(env->kvm_state, &mcg_cap, &banks); |
537 |
if (ret < 0) { |
538 |
fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
|
539 |
return ret;
|
540 |
} |
541 |
|
542 |
if (banks > MCE_BANKS_DEF) {
|
543 |
banks = MCE_BANKS_DEF; |
544 |
} |
545 |
mcg_cap &= MCE_CAP_DEF; |
546 |
mcg_cap |= banks; |
547 |
ret = kvm_vcpu_ioctl(env, KVM_X86_SETUP_MCE, &mcg_cap); |
548 |
if (ret < 0) { |
549 |
fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
|
550 |
return ret;
|
551 |
} |
552 |
|
553 |
env->mcg_cap = mcg_cap; |
554 |
} |
555 |
|
556 |
qemu_add_vm_change_state_handler(cpu_update_state, env); |
557 |
|
558 |
cpuid_data.cpuid.padding = 0;
|
559 |
r = kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data); |
560 |
if (r) {
|
561 |
return r;
|
562 |
} |
563 |
|
564 |
r = kvm_check_extension(env->kvm_state, KVM_CAP_TSC_CONTROL); |
565 |
if (r && env->tsc_khz) {
|
566 |
r = kvm_vcpu_ioctl(env, KVM_SET_TSC_KHZ, env->tsc_khz); |
567 |
if (r < 0) { |
568 |
fprintf(stderr, "KVM_SET_TSC_KHZ failed\n");
|
569 |
return r;
|
570 |
} |
571 |
} |
572 |
|
573 |
if (kvm_has_xsave()) {
|
574 |
env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave)); |
575 |
} |
576 |
|
577 |
return 0; |
578 |
} |
579 |
|
580 |
void kvm_arch_reset_vcpu(CPUState *env)
|
581 |
{ |
582 |
env->exception_injected = -1;
|
583 |
env->interrupt_injected = -1;
|
584 |
env->xcr0 = 1;
|
585 |
if (kvm_irqchip_in_kernel()) {
|
586 |
env->mp_state = cpu_is_bsp(env) ? KVM_MP_STATE_RUNNABLE : |
587 |
KVM_MP_STATE_UNINITIALIZED; |
588 |
} else {
|
589 |
env->mp_state = KVM_MP_STATE_RUNNABLE; |
590 |
} |
591 |
} |
592 |
|
593 |
static int kvm_get_supported_msrs(KVMState *s) |
594 |
{ |
595 |
static int kvm_supported_msrs; |
596 |
int ret = 0; |
597 |
|
598 |
/* first time */
|
599 |
if (kvm_supported_msrs == 0) { |
600 |
struct kvm_msr_list msr_list, *kvm_msr_list;
|
601 |
|
602 |
kvm_supported_msrs = -1;
|
603 |
|
604 |
/* Obtain MSR list from KVM. These are the MSRs that we must
|
605 |
* save/restore */
|
606 |
msr_list.nmsrs = 0;
|
607 |
ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list); |
608 |
if (ret < 0 && ret != -E2BIG) { |
609 |
return ret;
|
610 |
} |
611 |
/* Old kernel modules had a bug and could write beyond the provided
|
612 |
memory. Allocate at least a safe amount of 1K. */
|
613 |
kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) + |
614 |
msr_list.nmsrs * |
615 |
sizeof(msr_list.indices[0]))); |
616 |
|
617 |
kvm_msr_list->nmsrs = msr_list.nmsrs; |
618 |
ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list); |
619 |
if (ret >= 0) { |
620 |
int i;
|
621 |
|
622 |
for (i = 0; i < kvm_msr_list->nmsrs; i++) { |
623 |
if (kvm_msr_list->indices[i] == MSR_STAR) {
|
624 |
has_msr_star = true;
|
625 |
continue;
|
626 |
} |
627 |
if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
|
628 |
has_msr_hsave_pa = true;
|
629 |
continue;
|
630 |
} |
631 |
if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
|
632 |
has_msr_tsc_deadline = true;
|
633 |
continue;
|
634 |
} |
635 |
if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) {
|
636 |
has_msr_misc_enable = true;
|
637 |
continue;
|
638 |
} |
639 |
} |
640 |
} |
641 |
|
642 |
g_free(kvm_msr_list); |
643 |
} |
644 |
|
645 |
return ret;
|
646 |
} |
647 |
|
648 |
int kvm_arch_init(KVMState *s)
|
649 |
{ |
650 |
QemuOptsList *list = qemu_find_opts("machine");
|
651 |
uint64_t identity_base = 0xfffbc000;
|
652 |
uint64_t shadow_mem; |
653 |
int ret;
|
654 |
struct utsname utsname;
|
655 |
|
656 |
ret = kvm_get_supported_msrs(s); |
657 |
if (ret < 0) { |
658 |
return ret;
|
659 |
} |
660 |
|
661 |
uname(&utsname); |
662 |
lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0; |
663 |
|
664 |
/*
|
665 |
* On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
|
666 |
* In order to use vm86 mode, an EPT identity map and a TSS are needed.
|
667 |
* Since these must be part of guest physical memory, we need to allocate
|
668 |
* them, both by setting their start addresses in the kernel and by
|
669 |
* creating a corresponding e820 entry. We need 4 pages before the BIOS.
|
670 |
*
|
671 |
* Older KVM versions may not support setting the identity map base. In
|
672 |
* that case we need to stick with the default, i.e. a 256K maximum BIOS
|
673 |
* size.
|
674 |
*/
|
675 |
if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
|
676 |
/* Allows up to 16M BIOSes. */
|
677 |
identity_base = 0xfeffc000;
|
678 |
|
679 |
ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base); |
680 |
if (ret < 0) { |
681 |
return ret;
|
682 |
} |
683 |
} |
684 |
|
685 |
/* Set TSS base one page after EPT identity map. */
|
686 |
ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
|
687 |
if (ret < 0) { |
688 |
return ret;
|
689 |
} |
690 |
|
691 |
/* Tell fw_cfg to notify the BIOS to reserve the range. */
|
692 |
ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
|
693 |
if (ret < 0) { |
694 |
fprintf(stderr, "e820_add_entry() table is full\n");
|
695 |
return ret;
|
696 |
} |
697 |
qemu_register_reset(kvm_unpoison_all, NULL);
|
698 |
|
699 |
if (!QTAILQ_EMPTY(&list->head)) {
|
700 |
shadow_mem = qemu_opt_get_size(QTAILQ_FIRST(&list->head), |
701 |
"kvm_shadow_mem", -1); |
702 |
if (shadow_mem != -1) { |
703 |
shadow_mem /= 4096;
|
704 |
ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem); |
705 |
if (ret < 0) { |
706 |
return ret;
|
707 |
} |
708 |
} |
709 |
} |
710 |
return 0; |
711 |
} |
712 |
|
713 |
static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs) |
714 |
{ |
715 |
lhs->selector = rhs->selector; |
716 |
lhs->base = rhs->base; |
717 |
lhs->limit = rhs->limit; |
718 |
lhs->type = 3;
|
719 |
lhs->present = 1;
|
720 |
lhs->dpl = 3;
|
721 |
lhs->db = 0;
|
722 |
lhs->s = 1;
|
723 |
lhs->l = 0;
|
724 |
lhs->g = 0;
|
725 |
lhs->avl = 0;
|
726 |
lhs->unusable = 0;
|
727 |
} |
728 |
|
729 |
static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs) |
730 |
{ |
731 |
unsigned flags = rhs->flags;
|
732 |
lhs->selector = rhs->selector; |
733 |
lhs->base = rhs->base; |
734 |
lhs->limit = rhs->limit; |
735 |
lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
|
736 |
lhs->present = (flags & DESC_P_MASK) != 0;
|
737 |
lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
|
738 |
lhs->db = (flags >> DESC_B_SHIFT) & 1;
|
739 |
lhs->s = (flags & DESC_S_MASK) != 0;
|
740 |
lhs->l = (flags >> DESC_L_SHIFT) & 1;
|
741 |
lhs->g = (flags & DESC_G_MASK) != 0;
|
742 |
lhs->avl = (flags & DESC_AVL_MASK) != 0;
|
743 |
lhs->unusable = 0;
|
744 |
lhs->padding = 0;
|
745 |
} |
746 |
|
747 |
static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs) |
748 |
{ |
749 |
lhs->selector = rhs->selector; |
750 |
lhs->base = rhs->base; |
751 |
lhs->limit = rhs->limit; |
752 |
lhs->flags = (rhs->type << DESC_TYPE_SHIFT) | |
753 |
(rhs->present * DESC_P_MASK) | |
754 |
(rhs->dpl << DESC_DPL_SHIFT) | |
755 |
(rhs->db << DESC_B_SHIFT) | |
756 |
(rhs->s * DESC_S_MASK) | |
757 |
(rhs->l << DESC_L_SHIFT) | |
758 |
(rhs->g * DESC_G_MASK) | |
759 |
(rhs->avl * DESC_AVL_MASK); |
760 |
} |
761 |
|
762 |
static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set) |
763 |
{ |
764 |
if (set) {
|
765 |
*kvm_reg = *qemu_reg; |
766 |
} else {
|
767 |
*qemu_reg = *kvm_reg; |
768 |
} |
769 |
} |
770 |
|
771 |
static int kvm_getput_regs(CPUState *env, int set) |
772 |
{ |
773 |
struct kvm_regs regs;
|
774 |
int ret = 0; |
775 |
|
776 |
if (!set) {
|
777 |
ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, ®s); |
778 |
if (ret < 0) { |
779 |
return ret;
|
780 |
} |
781 |
} |
782 |
|
783 |
kvm_getput_reg(®s.rax, &env->regs[R_EAX], set); |
784 |
kvm_getput_reg(®s.rbx, &env->regs[R_EBX], set); |
785 |
kvm_getput_reg(®s.rcx, &env->regs[R_ECX], set); |
786 |
kvm_getput_reg(®s.rdx, &env->regs[R_EDX], set); |
787 |
kvm_getput_reg(®s.rsi, &env->regs[R_ESI], set); |
788 |
kvm_getput_reg(®s.rdi, &env->regs[R_EDI], set); |
789 |
kvm_getput_reg(®s.rsp, &env->regs[R_ESP], set); |
790 |
kvm_getput_reg(®s.rbp, &env->regs[R_EBP], set); |
791 |
#ifdef TARGET_X86_64
|
792 |
kvm_getput_reg(®s.r8, &env->regs[8], set);
|
793 |
kvm_getput_reg(®s.r9, &env->regs[9], set);
|
794 |
kvm_getput_reg(®s.r10, &env->regs[10], set);
|
795 |
kvm_getput_reg(®s.r11, &env->regs[11], set);
|
796 |
kvm_getput_reg(®s.r12, &env->regs[12], set);
|
797 |
kvm_getput_reg(®s.r13, &env->regs[13], set);
|
798 |
kvm_getput_reg(®s.r14, &env->regs[14], set);
|
799 |
kvm_getput_reg(®s.r15, &env->regs[15], set);
|
800 |
#endif
|
801 |
|
802 |
kvm_getput_reg(®s.rflags, &env->eflags, set); |
803 |
kvm_getput_reg(®s.rip, &env->eip, set); |
804 |
|
805 |
if (set) {
|
806 |
ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, ®s); |
807 |
} |
808 |
|
809 |
return ret;
|
810 |
} |
811 |
|
812 |
static int kvm_put_fpu(CPUState *env) |
813 |
{ |
814 |
struct kvm_fpu fpu;
|
815 |
int i;
|
816 |
|
817 |
memset(&fpu, 0, sizeof fpu); |
818 |
fpu.fsw = env->fpus & ~(7 << 11); |
819 |
fpu.fsw |= (env->fpstt & 7) << 11; |
820 |
fpu.fcw = env->fpuc; |
821 |
fpu.last_opcode = env->fpop; |
822 |
fpu.last_ip = env->fpip; |
823 |
fpu.last_dp = env->fpdp; |
824 |
for (i = 0; i < 8; ++i) { |
825 |
fpu.ftwx |= (!env->fptags[i]) << i; |
826 |
} |
827 |
memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
|
828 |
memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
|
829 |
fpu.mxcsr = env->mxcsr; |
830 |
|
831 |
return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu);
|
832 |
} |
833 |
|
834 |
#define XSAVE_FCW_FSW 0 |
835 |
#define XSAVE_FTW_FOP 1 |
836 |
#define XSAVE_CWD_RIP 2 |
837 |
#define XSAVE_CWD_RDP 4 |
838 |
#define XSAVE_MXCSR 6 |
839 |
#define XSAVE_ST_SPACE 8 |
840 |
#define XSAVE_XMM_SPACE 40 |
841 |
#define XSAVE_XSTATE_BV 128 |
842 |
#define XSAVE_YMMH_SPACE 144 |
843 |
|
844 |
static int kvm_put_xsave(CPUState *env) |
845 |
{ |
846 |
struct kvm_xsave* xsave = env->kvm_xsave_buf;
|
847 |
uint16_t cwd, swd, twd; |
848 |
int i, r;
|
849 |
|
850 |
if (!kvm_has_xsave()) {
|
851 |
return kvm_put_fpu(env);
|
852 |
} |
853 |
|
854 |
memset(xsave, 0, sizeof(struct kvm_xsave)); |
855 |
twd = 0;
|
856 |
swd = env->fpus & ~(7 << 11); |
857 |
swd |= (env->fpstt & 7) << 11; |
858 |
cwd = env->fpuc; |
859 |
for (i = 0; i < 8; ++i) { |
860 |
twd |= (!env->fptags[i]) << i; |
861 |
} |
862 |
xsave->region[XSAVE_FCW_FSW] = (uint32_t)(swd << 16) + cwd;
|
863 |
xsave->region[XSAVE_FTW_FOP] = (uint32_t)(env->fpop << 16) + twd;
|
864 |
memcpy(&xsave->region[XSAVE_CWD_RIP], &env->fpip, sizeof(env->fpip));
|
865 |
memcpy(&xsave->region[XSAVE_CWD_RDP], &env->fpdp, sizeof(env->fpdp));
|
866 |
memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs, |
867 |
sizeof env->fpregs);
|
868 |
memcpy(&xsave->region[XSAVE_XMM_SPACE], env->xmm_regs, |
869 |
sizeof env->xmm_regs);
|
870 |
xsave->region[XSAVE_MXCSR] = env->mxcsr; |
871 |
*(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv; |
872 |
memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs, |
873 |
sizeof env->ymmh_regs);
|
874 |
r = kvm_vcpu_ioctl(env, KVM_SET_XSAVE, xsave); |
875 |
return r;
|
876 |
} |
877 |
|
878 |
static int kvm_put_xcrs(CPUState *env) |
879 |
{ |
880 |
struct kvm_xcrs xcrs;
|
881 |
|
882 |
if (!kvm_has_xcrs()) {
|
883 |
return 0; |
884 |
} |
885 |
|
886 |
xcrs.nr_xcrs = 1;
|
887 |
xcrs.flags = 0;
|
888 |
xcrs.xcrs[0].xcr = 0; |
889 |
xcrs.xcrs[0].value = env->xcr0;
|
890 |
return kvm_vcpu_ioctl(env, KVM_SET_XCRS, &xcrs);
|
891 |
} |
892 |
|
893 |
static int kvm_put_sregs(CPUState *env) |
894 |
{ |
895 |
struct kvm_sregs sregs;
|
896 |
|
897 |
memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap)); |
898 |
if (env->interrupt_injected >= 0) { |
899 |
sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
|
900 |
(uint64_t)1 << (env->interrupt_injected % 64); |
901 |
} |
902 |
|
903 |
if ((env->eflags & VM_MASK)) {
|
904 |
set_v8086_seg(&sregs.cs, &env->segs[R_CS]); |
905 |
set_v8086_seg(&sregs.ds, &env->segs[R_DS]); |
906 |
set_v8086_seg(&sregs.es, &env->segs[R_ES]); |
907 |
set_v8086_seg(&sregs.fs, &env->segs[R_FS]); |
908 |
set_v8086_seg(&sregs.gs, &env->segs[R_GS]); |
909 |
set_v8086_seg(&sregs.ss, &env->segs[R_SS]); |
910 |
} else {
|
911 |
set_seg(&sregs.cs, &env->segs[R_CS]); |
912 |
set_seg(&sregs.ds, &env->segs[R_DS]); |
913 |
set_seg(&sregs.es, &env->segs[R_ES]); |
914 |
set_seg(&sregs.fs, &env->segs[R_FS]); |
915 |
set_seg(&sregs.gs, &env->segs[R_GS]); |
916 |
set_seg(&sregs.ss, &env->segs[R_SS]); |
917 |
} |
918 |
|
919 |
set_seg(&sregs.tr, &env->tr); |
920 |
set_seg(&sregs.ldt, &env->ldt); |
921 |
|
922 |
sregs.idt.limit = env->idt.limit; |
923 |
sregs.idt.base = env->idt.base; |
924 |
memset(sregs.idt.padding, 0, sizeof sregs.idt.padding); |
925 |
sregs.gdt.limit = env->gdt.limit; |
926 |
sregs.gdt.base = env->gdt.base; |
927 |
memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding); |
928 |
|
929 |
sregs.cr0 = env->cr[0];
|
930 |
sregs.cr2 = env->cr[2];
|
931 |
sregs.cr3 = env->cr[3];
|
932 |
sregs.cr4 = env->cr[4];
|
933 |
|
934 |
sregs.cr8 = cpu_get_apic_tpr(env->apic_state); |
935 |
sregs.apic_base = cpu_get_apic_base(env->apic_state); |
936 |
|
937 |
sregs.efer = env->efer; |
938 |
|
939 |
return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);
|
940 |
} |
941 |
|
942 |
static void kvm_msr_entry_set(struct kvm_msr_entry *entry, |
943 |
uint32_t index, uint64_t value) |
944 |
{ |
945 |
entry->index = index; |
946 |
entry->data = value; |
947 |
} |
948 |
|
949 |
static int kvm_put_msrs(CPUState *env, int level) |
950 |
{ |
951 |
struct {
|
952 |
struct kvm_msrs info;
|
953 |
struct kvm_msr_entry entries[100]; |
954 |
} msr_data; |
955 |
struct kvm_msr_entry *msrs = msr_data.entries;
|
956 |
int n = 0; |
957 |
|
958 |
kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs); |
959 |
kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp); |
960 |
kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip); |
961 |
kvm_msr_entry_set(&msrs[n++], MSR_PAT, env->pat); |
962 |
if (has_msr_star) {
|
963 |
kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star); |
964 |
} |
965 |
if (has_msr_hsave_pa) {
|
966 |
kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave); |
967 |
} |
968 |
if (has_msr_tsc_deadline) {
|
969 |
kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSCDEADLINE, env->tsc_deadline); |
970 |
} |
971 |
if (has_msr_misc_enable) {
|
972 |
kvm_msr_entry_set(&msrs[n++], MSR_IA32_MISC_ENABLE, |
973 |
env->msr_ia32_misc_enable); |
974 |
} |
975 |
#ifdef TARGET_X86_64
|
976 |
if (lm_capable_kernel) {
|
977 |
kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar); |
978 |
kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase); |
979 |
kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask); |
980 |
kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar); |
981 |
} |
982 |
#endif
|
983 |
if (level == KVM_PUT_FULL_STATE) {
|
984 |
/*
|
985 |
* KVM is yet unable to synchronize TSC values of multiple VCPUs on
|
986 |
* writeback. Until this is fixed, we only write the offset to SMP
|
987 |
* guests after migration, desynchronizing the VCPUs, but avoiding
|
988 |
* huge jump-backs that would occur without any writeback at all.
|
989 |
*/
|
990 |
if (smp_cpus == 1 || env->tsc != 0) { |
991 |
kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc); |
992 |
} |
993 |
} |
994 |
/*
|
995 |
* The following paravirtual MSRs have side effects on the guest or are
|
996 |
* too heavy for normal writeback. Limit them to reset or full state
|
997 |
* updates.
|
998 |
*/
|
999 |
if (level >= KVM_PUT_RESET_STATE) {
|
1000 |
kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME, |
1001 |
env->system_time_msr); |
1002 |
kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr); |
1003 |
if (has_msr_async_pf_en) {
|
1004 |
kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN, |
1005 |
env->async_pf_en_msr); |
1006 |
} |
1007 |
if (hyperv_hypercall_available()) {
|
1008 |
kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_GUEST_OS_ID, 0);
|
1009 |
kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_HYPERCALL, 0);
|
1010 |
} |
1011 |
if (hyperv_vapic_recommended()) {
|
1012 |
kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_APIC_ASSIST_PAGE, 0);
|
1013 |
} |
1014 |
} |
1015 |
if (env->mcg_cap) {
|
1016 |
int i;
|
1017 |
|
1018 |
kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status); |
1019 |
kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl); |
1020 |
for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) { |
1021 |
kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]); |
1022 |
} |
1023 |
} |
1024 |
|
1025 |
msr_data.info.nmsrs = n; |
1026 |
|
1027 |
return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);
|
1028 |
|
1029 |
} |
1030 |
|
1031 |
|
1032 |
static int kvm_get_fpu(CPUState *env) |
1033 |
{ |
1034 |
struct kvm_fpu fpu;
|
1035 |
int i, ret;
|
1036 |
|
1037 |
ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu); |
1038 |
if (ret < 0) { |
1039 |
return ret;
|
1040 |
} |
1041 |
|
1042 |
env->fpstt = (fpu.fsw >> 11) & 7; |
1043 |
env->fpus = fpu.fsw; |
1044 |
env->fpuc = fpu.fcw; |
1045 |
env->fpop = fpu.last_opcode; |
1046 |
env->fpip = fpu.last_ip; |
1047 |
env->fpdp = fpu.last_dp; |
1048 |
for (i = 0; i < 8; ++i) { |
1049 |
env->fptags[i] = !((fpu.ftwx >> i) & 1);
|
1050 |
} |
1051 |
memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
|
1052 |
memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
|
1053 |
env->mxcsr = fpu.mxcsr; |
1054 |
|
1055 |
return 0; |
1056 |
} |
1057 |
|
1058 |
static int kvm_get_xsave(CPUState *env) |
1059 |
{ |
1060 |
struct kvm_xsave* xsave = env->kvm_xsave_buf;
|
1061 |
int ret, i;
|
1062 |
uint16_t cwd, swd, twd; |
1063 |
|
1064 |
if (!kvm_has_xsave()) {
|
1065 |
return kvm_get_fpu(env);
|
1066 |
} |
1067 |
|
1068 |
ret = kvm_vcpu_ioctl(env, KVM_GET_XSAVE, xsave); |
1069 |
if (ret < 0) { |
1070 |
return ret;
|
1071 |
} |
1072 |
|
1073 |
cwd = (uint16_t)xsave->region[XSAVE_FCW_FSW]; |
1074 |
swd = (uint16_t)(xsave->region[XSAVE_FCW_FSW] >> 16);
|
1075 |
twd = (uint16_t)xsave->region[XSAVE_FTW_FOP]; |
1076 |
env->fpop = (uint16_t)(xsave->region[XSAVE_FTW_FOP] >> 16);
|
1077 |
env->fpstt = (swd >> 11) & 7; |
1078 |
env->fpus = swd; |
1079 |
env->fpuc = cwd; |
1080 |
for (i = 0; i < 8; ++i) { |
1081 |
env->fptags[i] = !((twd >> i) & 1);
|
1082 |
} |
1083 |
memcpy(&env->fpip, &xsave->region[XSAVE_CWD_RIP], sizeof(env->fpip));
|
1084 |
memcpy(&env->fpdp, &xsave->region[XSAVE_CWD_RDP], sizeof(env->fpdp));
|
1085 |
env->mxcsr = xsave->region[XSAVE_MXCSR]; |
1086 |
memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE], |
1087 |
sizeof env->fpregs);
|
1088 |
memcpy(env->xmm_regs, &xsave->region[XSAVE_XMM_SPACE], |
1089 |
sizeof env->xmm_regs);
|
1090 |
env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV]; |
1091 |
memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE], |
1092 |
sizeof env->ymmh_regs);
|
1093 |
return 0; |
1094 |
} |
1095 |
|
1096 |
static int kvm_get_xcrs(CPUState *env) |
1097 |
{ |
1098 |
int i, ret;
|
1099 |
struct kvm_xcrs xcrs;
|
1100 |
|
1101 |
if (!kvm_has_xcrs()) {
|
1102 |
return 0; |
1103 |
} |
1104 |
|
1105 |
ret = kvm_vcpu_ioctl(env, KVM_GET_XCRS, &xcrs); |
1106 |
if (ret < 0) { |
1107 |
return ret;
|
1108 |
} |
1109 |
|
1110 |
for (i = 0; i < xcrs.nr_xcrs; i++) { |
1111 |
/* Only support xcr0 now */
|
1112 |
if (xcrs.xcrs[0].xcr == 0) { |
1113 |
env->xcr0 = xcrs.xcrs[0].value;
|
1114 |
break;
|
1115 |
} |
1116 |
} |
1117 |
return 0; |
1118 |
} |
1119 |
|
1120 |
static int kvm_get_sregs(CPUState *env) |
1121 |
{ |
1122 |
struct kvm_sregs sregs;
|
1123 |
uint32_t hflags; |
1124 |
int bit, i, ret;
|
1125 |
|
1126 |
ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs); |
1127 |
if (ret < 0) { |
1128 |
return ret;
|
1129 |
} |
1130 |
|
1131 |
/* There can only be one pending IRQ set in the bitmap at a time, so try
|
1132 |
to find it and save its number instead (-1 for none). */
|
1133 |
env->interrupt_injected = -1;
|
1134 |
for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) { |
1135 |
if (sregs.interrupt_bitmap[i]) {
|
1136 |
bit = ctz64(sregs.interrupt_bitmap[i]); |
1137 |
env->interrupt_injected = i * 64 + bit;
|
1138 |
break;
|
1139 |
} |
1140 |
} |
1141 |
|
1142 |
get_seg(&env->segs[R_CS], &sregs.cs); |
1143 |
get_seg(&env->segs[R_DS], &sregs.ds); |
1144 |
get_seg(&env->segs[R_ES], &sregs.es); |
1145 |
get_seg(&env->segs[R_FS], &sregs.fs); |
1146 |
get_seg(&env->segs[R_GS], &sregs.gs); |
1147 |
get_seg(&env->segs[R_SS], &sregs.ss); |
1148 |
|
1149 |
get_seg(&env->tr, &sregs.tr); |
1150 |
get_seg(&env->ldt, &sregs.ldt); |
1151 |
|
1152 |
env->idt.limit = sregs.idt.limit; |
1153 |
env->idt.base = sregs.idt.base; |
1154 |
env->gdt.limit = sregs.gdt.limit; |
1155 |
env->gdt.base = sregs.gdt.base; |
1156 |
|
1157 |
env->cr[0] = sregs.cr0;
|
1158 |
env->cr[2] = sregs.cr2;
|
1159 |
env->cr[3] = sregs.cr3;
|
1160 |
env->cr[4] = sregs.cr4;
|
1161 |
|
1162 |
env->efer = sregs.efer; |
1163 |
|
1164 |
/* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
|
1165 |
|
1166 |
#define HFLAG_COPY_MASK \
|
1167 |
~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \ |
1168 |
HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \ |
1169 |
HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \ |
1170 |
HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK) |
1171 |
|
1172 |
hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK; |
1173 |
hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
|
1174 |
hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
|
1175 |
(HF_MP_MASK | HF_EM_MASK | HF_TS_MASK); |
1176 |
hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK)); |
1177 |
hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
|
1178 |
(HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT); |
1179 |
|
1180 |
if (env->efer & MSR_EFER_LMA) {
|
1181 |
hflags |= HF_LMA_MASK; |
1182 |
} |
1183 |
|
1184 |
if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
|
1185 |
hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; |
1186 |
} else {
|
1187 |
hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >> |
1188 |
(DESC_B_SHIFT - HF_CS32_SHIFT); |
1189 |
hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >> |
1190 |
(DESC_B_SHIFT - HF_SS32_SHIFT); |
1191 |
if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) || |
1192 |
!(hflags & HF_CS32_MASK)) { |
1193 |
hflags |= HF_ADDSEG_MASK; |
1194 |
} else {
|
1195 |
hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base | |
1196 |
env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
|
1197 |
} |
1198 |
} |
1199 |
env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags; |
1200 |
|
1201 |
return 0; |
1202 |
} |
1203 |
|
1204 |
static int kvm_get_msrs(CPUState *env) |
1205 |
{ |
1206 |
struct {
|
1207 |
struct kvm_msrs info;
|
1208 |
struct kvm_msr_entry entries[100]; |
1209 |
} msr_data; |
1210 |
struct kvm_msr_entry *msrs = msr_data.entries;
|
1211 |
int ret, i, n;
|
1212 |
|
1213 |
n = 0;
|
1214 |
msrs[n++].index = MSR_IA32_SYSENTER_CS; |
1215 |
msrs[n++].index = MSR_IA32_SYSENTER_ESP; |
1216 |
msrs[n++].index = MSR_IA32_SYSENTER_EIP; |
1217 |
msrs[n++].index = MSR_PAT; |
1218 |
if (has_msr_star) {
|
1219 |
msrs[n++].index = MSR_STAR; |
1220 |
} |
1221 |
if (has_msr_hsave_pa) {
|
1222 |
msrs[n++].index = MSR_VM_HSAVE_PA; |
1223 |
} |
1224 |
if (has_msr_tsc_deadline) {
|
1225 |
msrs[n++].index = MSR_IA32_TSCDEADLINE; |
1226 |
} |
1227 |
if (has_msr_misc_enable) {
|
1228 |
msrs[n++].index = MSR_IA32_MISC_ENABLE; |
1229 |
} |
1230 |
|
1231 |
if (!env->tsc_valid) {
|
1232 |
msrs[n++].index = MSR_IA32_TSC; |
1233 |
env->tsc_valid = !runstate_is_running(); |
1234 |
} |
1235 |
|
1236 |
#ifdef TARGET_X86_64
|
1237 |
if (lm_capable_kernel) {
|
1238 |
msrs[n++].index = MSR_CSTAR; |
1239 |
msrs[n++].index = MSR_KERNELGSBASE; |
1240 |
msrs[n++].index = MSR_FMASK; |
1241 |
msrs[n++].index = MSR_LSTAR; |
1242 |
} |
1243 |
#endif
|
1244 |
msrs[n++].index = MSR_KVM_SYSTEM_TIME; |
1245 |
msrs[n++].index = MSR_KVM_WALL_CLOCK; |
1246 |
if (has_msr_async_pf_en) {
|
1247 |
msrs[n++].index = MSR_KVM_ASYNC_PF_EN; |
1248 |
} |
1249 |
|
1250 |
if (env->mcg_cap) {
|
1251 |
msrs[n++].index = MSR_MCG_STATUS; |
1252 |
msrs[n++].index = MSR_MCG_CTL; |
1253 |
for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) { |
1254 |
msrs[n++].index = MSR_MC0_CTL + i; |
1255 |
} |
1256 |
} |
1257 |
|
1258 |
msr_data.info.nmsrs = n; |
1259 |
ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data); |
1260 |
if (ret < 0) { |
1261 |
return ret;
|
1262 |
} |
1263 |
|
1264 |
for (i = 0; i < ret; i++) { |
1265 |
switch (msrs[i].index) {
|
1266 |
case MSR_IA32_SYSENTER_CS:
|
1267 |
env->sysenter_cs = msrs[i].data; |
1268 |
break;
|
1269 |
case MSR_IA32_SYSENTER_ESP:
|
1270 |
env->sysenter_esp = msrs[i].data; |
1271 |
break;
|
1272 |
case MSR_IA32_SYSENTER_EIP:
|
1273 |
env->sysenter_eip = msrs[i].data; |
1274 |
break;
|
1275 |
case MSR_PAT:
|
1276 |
env->pat = msrs[i].data; |
1277 |
break;
|
1278 |
case MSR_STAR:
|
1279 |
env->star = msrs[i].data; |
1280 |
break;
|
1281 |
#ifdef TARGET_X86_64
|
1282 |
case MSR_CSTAR:
|
1283 |
env->cstar = msrs[i].data; |
1284 |
break;
|
1285 |
case MSR_KERNELGSBASE:
|
1286 |
env->kernelgsbase = msrs[i].data; |
1287 |
break;
|
1288 |
case MSR_FMASK:
|
1289 |
env->fmask = msrs[i].data; |
1290 |
break;
|
1291 |
case MSR_LSTAR:
|
1292 |
env->lstar = msrs[i].data; |
1293 |
break;
|
1294 |
#endif
|
1295 |
case MSR_IA32_TSC:
|
1296 |
env->tsc = msrs[i].data; |
1297 |
break;
|
1298 |
case MSR_IA32_TSCDEADLINE:
|
1299 |
env->tsc_deadline = msrs[i].data; |
1300 |
break;
|
1301 |
case MSR_VM_HSAVE_PA:
|
1302 |
env->vm_hsave = msrs[i].data; |
1303 |
break;
|
1304 |
case MSR_KVM_SYSTEM_TIME:
|
1305 |
env->system_time_msr = msrs[i].data; |
1306 |
break;
|
1307 |
case MSR_KVM_WALL_CLOCK:
|
1308 |
env->wall_clock_msr = msrs[i].data; |
1309 |
break;
|
1310 |
case MSR_MCG_STATUS:
|
1311 |
env->mcg_status = msrs[i].data; |
1312 |
break;
|
1313 |
case MSR_MCG_CTL:
|
1314 |
env->mcg_ctl = msrs[i].data; |
1315 |
break;
|
1316 |
case MSR_IA32_MISC_ENABLE:
|
1317 |
env->msr_ia32_misc_enable = msrs[i].data; |
1318 |
break;
|
1319 |
default:
|
1320 |
if (msrs[i].index >= MSR_MC0_CTL &&
|
1321 |
msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) { |
1322 |
env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data; |
1323 |
} |
1324 |
break;
|
1325 |
case MSR_KVM_ASYNC_PF_EN:
|
1326 |
env->async_pf_en_msr = msrs[i].data; |
1327 |
break;
|
1328 |
} |
1329 |
} |
1330 |
|
1331 |
return 0; |
1332 |
} |
1333 |
|
1334 |
static int kvm_put_mp_state(CPUState *env) |
1335 |
{ |
1336 |
struct kvm_mp_state mp_state = { .mp_state = env->mp_state };
|
1337 |
|
1338 |
return kvm_vcpu_ioctl(env, KVM_SET_MP_STATE, &mp_state);
|
1339 |
} |
1340 |
|
1341 |
static int kvm_get_mp_state(CPUState *env) |
1342 |
{ |
1343 |
struct kvm_mp_state mp_state;
|
1344 |
int ret;
|
1345 |
|
1346 |
ret = kvm_vcpu_ioctl(env, KVM_GET_MP_STATE, &mp_state); |
1347 |
if (ret < 0) { |
1348 |
return ret;
|
1349 |
} |
1350 |
env->mp_state = mp_state.mp_state; |
1351 |
if (kvm_irqchip_in_kernel()) {
|
1352 |
env->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED); |
1353 |
} |
1354 |
return 0; |
1355 |
} |
1356 |
|
1357 |
static int kvm_get_apic(CPUState *env) |
1358 |
{ |
1359 |
DeviceState *apic = env->apic_state; |
1360 |
struct kvm_lapic_state kapic;
|
1361 |
int ret;
|
1362 |
|
1363 |
if (apic && kvm_irqchip_in_kernel()) {
|
1364 |
ret = kvm_vcpu_ioctl(env, KVM_GET_LAPIC, &kapic); |
1365 |
if (ret < 0) { |
1366 |
return ret;
|
1367 |
} |
1368 |
|
1369 |
kvm_get_apic_state(apic, &kapic); |
1370 |
} |
1371 |
return 0; |
1372 |
} |
1373 |
|
1374 |
static int kvm_put_apic(CPUState *env) |
1375 |
{ |
1376 |
DeviceState *apic = env->apic_state; |
1377 |
struct kvm_lapic_state kapic;
|
1378 |
|
1379 |
if (apic && kvm_irqchip_in_kernel()) {
|
1380 |
kvm_put_apic_state(apic, &kapic); |
1381 |
|
1382 |
return kvm_vcpu_ioctl(env, KVM_SET_LAPIC, &kapic);
|
1383 |
} |
1384 |
return 0; |
1385 |
} |
1386 |
|
1387 |
static int kvm_put_vcpu_events(CPUState *env, int level) |
1388 |
{ |
1389 |
struct kvm_vcpu_events events;
|
1390 |
|
1391 |
if (!kvm_has_vcpu_events()) {
|
1392 |
return 0; |
1393 |
} |
1394 |
|
1395 |
events.exception.injected = (env->exception_injected >= 0);
|
1396 |
events.exception.nr = env->exception_injected; |
1397 |
events.exception.has_error_code = env->has_error_code; |
1398 |
events.exception.error_code = env->error_code; |
1399 |
events.exception.pad = 0;
|
1400 |
|
1401 |
events.interrupt.injected = (env->interrupt_injected >= 0);
|
1402 |
events.interrupt.nr = env->interrupt_injected; |
1403 |
events.interrupt.soft = env->soft_interrupt; |
1404 |
|
1405 |
events.nmi.injected = env->nmi_injected; |
1406 |
events.nmi.pending = env->nmi_pending; |
1407 |
events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK); |
1408 |
events.nmi.pad = 0;
|
1409 |
|
1410 |
events.sipi_vector = env->sipi_vector; |
1411 |
|
1412 |
events.flags = 0;
|
1413 |
if (level >= KVM_PUT_RESET_STATE) {
|
1414 |
events.flags |= |
1415 |
KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR; |
1416 |
} |
1417 |
|
1418 |
return kvm_vcpu_ioctl(env, KVM_SET_VCPU_EVENTS, &events);
|
1419 |
} |
1420 |
|
1421 |
static int kvm_get_vcpu_events(CPUState *env) |
1422 |
{ |
1423 |
struct kvm_vcpu_events events;
|
1424 |
int ret;
|
1425 |
|
1426 |
if (!kvm_has_vcpu_events()) {
|
1427 |
return 0; |
1428 |
} |
1429 |
|
1430 |
ret = kvm_vcpu_ioctl(env, KVM_GET_VCPU_EVENTS, &events); |
1431 |
if (ret < 0) { |
1432 |
return ret;
|
1433 |
} |
1434 |
env->exception_injected = |
1435 |
events.exception.injected ? events.exception.nr : -1;
|
1436 |
env->has_error_code = events.exception.has_error_code; |
1437 |
env->error_code = events.exception.error_code; |
1438 |
|
1439 |
env->interrupt_injected = |
1440 |
events.interrupt.injected ? events.interrupt.nr : -1;
|
1441 |
env->soft_interrupt = events.interrupt.soft; |
1442 |
|
1443 |
env->nmi_injected = events.nmi.injected; |
1444 |
env->nmi_pending = events.nmi.pending; |
1445 |
if (events.nmi.masked) {
|
1446 |
env->hflags2 |= HF2_NMI_MASK; |
1447 |
} else {
|
1448 |
env->hflags2 &= ~HF2_NMI_MASK; |
1449 |
} |
1450 |
|
1451 |
env->sipi_vector = events.sipi_vector; |
1452 |
|
1453 |
return 0; |
1454 |
} |
1455 |
|
1456 |
static int kvm_guest_debug_workarounds(CPUState *env) |
1457 |
{ |
1458 |
int ret = 0; |
1459 |
unsigned long reinject_trap = 0; |
1460 |
|
1461 |
if (!kvm_has_vcpu_events()) {
|
1462 |
if (env->exception_injected == 1) { |
1463 |
reinject_trap = KVM_GUESTDBG_INJECT_DB; |
1464 |
} else if (env->exception_injected == 3) { |
1465 |
reinject_trap = KVM_GUESTDBG_INJECT_BP; |
1466 |
} |
1467 |
env->exception_injected = -1;
|
1468 |
} |
1469 |
|
1470 |
/*
|
1471 |
* Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
|
1472 |
* injected via SET_GUEST_DEBUG while updating GP regs. Work around this
|
1473 |
* by updating the debug state once again if single-stepping is on.
|
1474 |
* Another reason to call kvm_update_guest_debug here is a pending debug
|
1475 |
* trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
|
1476 |
* reinject them via SET_GUEST_DEBUG.
|
1477 |
*/
|
1478 |
if (reinject_trap ||
|
1479 |
(!kvm_has_robust_singlestep() && env->singlestep_enabled)) { |
1480 |
ret = kvm_update_guest_debug(env, reinject_trap); |
1481 |
} |
1482 |
return ret;
|
1483 |
} |
1484 |
|
1485 |
static int kvm_put_debugregs(CPUState *env) |
1486 |
{ |
1487 |
struct kvm_debugregs dbgregs;
|
1488 |
int i;
|
1489 |
|
1490 |
if (!kvm_has_debugregs()) {
|
1491 |
return 0; |
1492 |
} |
1493 |
|
1494 |
for (i = 0; i < 4; i++) { |
1495 |
dbgregs.db[i] = env->dr[i]; |
1496 |
} |
1497 |
dbgregs.dr6 = env->dr[6];
|
1498 |
dbgregs.dr7 = env->dr[7];
|
1499 |
dbgregs.flags = 0;
|
1500 |
|
1501 |
return kvm_vcpu_ioctl(env, KVM_SET_DEBUGREGS, &dbgregs);
|
1502 |
} |
1503 |
|
1504 |
static int kvm_get_debugregs(CPUState *env) |
1505 |
{ |
1506 |
struct kvm_debugregs dbgregs;
|
1507 |
int i, ret;
|
1508 |
|
1509 |
if (!kvm_has_debugregs()) {
|
1510 |
return 0; |
1511 |
} |
1512 |
|
1513 |
ret = kvm_vcpu_ioctl(env, KVM_GET_DEBUGREGS, &dbgregs); |
1514 |
if (ret < 0) { |
1515 |
return ret;
|
1516 |
} |
1517 |
for (i = 0; i < 4; i++) { |
1518 |
env->dr[i] = dbgregs.db[i]; |
1519 |
} |
1520 |
env->dr[4] = env->dr[6] = dbgregs.dr6; |
1521 |
env->dr[5] = env->dr[7] = dbgregs.dr7; |
1522 |
|
1523 |
return 0; |
1524 |
} |
1525 |
|
1526 |
int kvm_arch_put_registers(CPUState *env, int level) |
1527 |
{ |
1528 |
int ret;
|
1529 |
|
1530 |
assert(cpu_is_stopped(env) || qemu_cpu_is_self(env)); |
1531 |
|
1532 |
ret = kvm_getput_regs(env, 1);
|
1533 |
if (ret < 0) { |
1534 |
return ret;
|
1535 |
} |
1536 |
ret = kvm_put_xsave(env); |
1537 |
if (ret < 0) { |
1538 |
return ret;
|
1539 |
} |
1540 |
ret = kvm_put_xcrs(env); |
1541 |
if (ret < 0) { |
1542 |
return ret;
|
1543 |
} |
1544 |
ret = kvm_put_sregs(env); |
1545 |
if (ret < 0) { |
1546 |
return ret;
|
1547 |
} |
1548 |
/* must be before kvm_put_msrs */
|
1549 |
ret = kvm_inject_mce_oldstyle(env); |
1550 |
if (ret < 0) { |
1551 |
return ret;
|
1552 |
} |
1553 |
ret = kvm_put_msrs(env, level); |
1554 |
if (ret < 0) { |
1555 |
return ret;
|
1556 |
} |
1557 |
if (level >= KVM_PUT_RESET_STATE) {
|
1558 |
ret = kvm_put_mp_state(env); |
1559 |
if (ret < 0) { |
1560 |
return ret;
|
1561 |
} |
1562 |
ret = kvm_put_apic(env); |
1563 |
if (ret < 0) { |
1564 |
return ret;
|
1565 |
} |
1566 |
} |
1567 |
ret = kvm_put_vcpu_events(env, level); |
1568 |
if (ret < 0) { |
1569 |
return ret;
|
1570 |
} |
1571 |
ret = kvm_put_debugregs(env); |
1572 |
if (ret < 0) { |
1573 |
return ret;
|
1574 |
} |
1575 |
/* must be last */
|
1576 |
ret = kvm_guest_debug_workarounds(env); |
1577 |
if (ret < 0) { |
1578 |
return ret;
|
1579 |
} |
1580 |
return 0; |
1581 |
} |
1582 |
|
1583 |
int kvm_arch_get_registers(CPUState *env)
|
1584 |
{ |
1585 |
int ret;
|
1586 |
|
1587 |
assert(cpu_is_stopped(env) || qemu_cpu_is_self(env)); |
1588 |
|
1589 |
ret = kvm_getput_regs(env, 0);
|
1590 |
if (ret < 0) { |
1591 |
return ret;
|
1592 |
} |
1593 |
ret = kvm_get_xsave(env); |
1594 |
if (ret < 0) { |
1595 |
return ret;
|
1596 |
} |
1597 |
ret = kvm_get_xcrs(env); |
1598 |
if (ret < 0) { |
1599 |
return ret;
|
1600 |
} |
1601 |
ret = kvm_get_sregs(env); |
1602 |
if (ret < 0) { |
1603 |
return ret;
|
1604 |
} |
1605 |
ret = kvm_get_msrs(env); |
1606 |
if (ret < 0) { |
1607 |
return ret;
|
1608 |
} |
1609 |
ret = kvm_get_mp_state(env); |
1610 |
if (ret < 0) { |
1611 |
return ret;
|
1612 |
} |
1613 |
ret = kvm_get_apic(env); |
1614 |
if (ret < 0) { |
1615 |
return ret;
|
1616 |
} |
1617 |
ret = kvm_get_vcpu_events(env); |
1618 |
if (ret < 0) { |
1619 |
return ret;
|
1620 |
} |
1621 |
ret = kvm_get_debugregs(env); |
1622 |
if (ret < 0) { |
1623 |
return ret;
|
1624 |
} |
1625 |
return 0; |
1626 |
} |
1627 |
|
1628 |
void kvm_arch_pre_run(CPUState *env, struct kvm_run *run) |
1629 |
{ |
1630 |
int ret;
|
1631 |
|
1632 |
/* Inject NMI */
|
1633 |
if (env->interrupt_request & CPU_INTERRUPT_NMI) {
|
1634 |
env->interrupt_request &= ~CPU_INTERRUPT_NMI; |
1635 |
DPRINTF("injected NMI\n");
|
1636 |
ret = kvm_vcpu_ioctl(env, KVM_NMI); |
1637 |
if (ret < 0) { |
1638 |
fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
|
1639 |
strerror(-ret)); |
1640 |
} |
1641 |
} |
1642 |
|
1643 |
if (!kvm_irqchip_in_kernel()) {
|
1644 |
/* Force the VCPU out of its inner loop to process any INIT requests
|
1645 |
* or pending TPR access reports. */
|
1646 |
if (env->interrupt_request &
|
1647 |
(CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) { |
1648 |
env->exit_request = 1;
|
1649 |
} |
1650 |
|
1651 |
/* Try to inject an interrupt if the guest can accept it */
|
1652 |
if (run->ready_for_interrupt_injection &&
|
1653 |
(env->interrupt_request & CPU_INTERRUPT_HARD) && |
1654 |
(env->eflags & IF_MASK)) { |
1655 |
int irq;
|
1656 |
|
1657 |
env->interrupt_request &= ~CPU_INTERRUPT_HARD; |
1658 |
irq = cpu_get_pic_interrupt(env); |
1659 |
if (irq >= 0) { |
1660 |
struct kvm_interrupt intr;
|
1661 |
|
1662 |
intr.irq = irq; |
1663 |
DPRINTF("injected interrupt %d\n", irq);
|
1664 |
ret = kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr); |
1665 |
if (ret < 0) { |
1666 |
fprintf(stderr, |
1667 |
"KVM: injection failed, interrupt lost (%s)\n",
|
1668 |
strerror(-ret)); |
1669 |
} |
1670 |
} |
1671 |
} |
1672 |
|
1673 |
/* If we have an interrupt but the guest is not ready to receive an
|
1674 |
* interrupt, request an interrupt window exit. This will
|
1675 |
* cause a return to userspace as soon as the guest is ready to
|
1676 |
* receive interrupts. */
|
1677 |
if ((env->interrupt_request & CPU_INTERRUPT_HARD)) {
|
1678 |
run->request_interrupt_window = 1;
|
1679 |
} else {
|
1680 |
run->request_interrupt_window = 0;
|
1681 |
} |
1682 |
|
1683 |
DPRINTF("setting tpr\n");
|
1684 |
run->cr8 = cpu_get_apic_tpr(env->apic_state); |
1685 |
} |
1686 |
} |
1687 |
|
1688 |
void kvm_arch_post_run(CPUState *env, struct kvm_run *run) |
1689 |
{ |
1690 |
if (run->if_flag) {
|
1691 |
env->eflags |= IF_MASK; |
1692 |
} else {
|
1693 |
env->eflags &= ~IF_MASK; |
1694 |
} |
1695 |
cpu_set_apic_tpr(env->apic_state, run->cr8); |
1696 |
cpu_set_apic_base(env->apic_state, run->apic_base); |
1697 |
} |
1698 |
|
1699 |
int kvm_arch_process_async_events(CPUState *env)
|
1700 |
{ |
1701 |
if (env->interrupt_request & CPU_INTERRUPT_MCE) {
|
1702 |
/* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
|
1703 |
assert(env->mcg_cap); |
1704 |
|
1705 |
env->interrupt_request &= ~CPU_INTERRUPT_MCE; |
1706 |
|
1707 |
kvm_cpu_synchronize_state(env); |
1708 |
|
1709 |
if (env->exception_injected == EXCP08_DBLE) {
|
1710 |
/* this means triple fault */
|
1711 |
qemu_system_reset_request(); |
1712 |
env->exit_request = 1;
|
1713 |
return 0; |
1714 |
} |
1715 |
env->exception_injected = EXCP12_MCHK; |
1716 |
env->has_error_code = 0;
|
1717 |
|
1718 |
env->halted = 0;
|
1719 |
if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
|
1720 |
env->mp_state = KVM_MP_STATE_RUNNABLE; |
1721 |
} |
1722 |
} |
1723 |
|
1724 |
if (kvm_irqchip_in_kernel()) {
|
1725 |
return 0; |
1726 |
} |
1727 |
|
1728 |
if (((env->interrupt_request & CPU_INTERRUPT_HARD) &&
|
1729 |
(env->eflags & IF_MASK)) || |
1730 |
(env->interrupt_request & CPU_INTERRUPT_NMI)) { |
1731 |
env->halted = 0;
|
1732 |
} |
1733 |
if (env->interrupt_request & CPU_INTERRUPT_INIT) {
|
1734 |
kvm_cpu_synchronize_state(env); |
1735 |
do_cpu_init(env); |
1736 |
} |
1737 |
if (env->interrupt_request & CPU_INTERRUPT_SIPI) {
|
1738 |
kvm_cpu_synchronize_state(env); |
1739 |
do_cpu_sipi(env); |
1740 |
} |
1741 |
if (env->interrupt_request & CPU_INTERRUPT_TPR) {
|
1742 |
env->interrupt_request &= ~CPU_INTERRUPT_TPR; |
1743 |
kvm_cpu_synchronize_state(env); |
1744 |
apic_handle_tpr_access_report(env->apic_state, env->eip, |
1745 |
env->tpr_access_type); |
1746 |
} |
1747 |
|
1748 |
return env->halted;
|
1749 |
} |
1750 |
|
1751 |
static int kvm_handle_halt(CPUState *env) |
1752 |
{ |
1753 |
if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
|
1754 |
(env->eflags & IF_MASK)) && |
1755 |
!(env->interrupt_request & CPU_INTERRUPT_NMI)) { |
1756 |
env->halted = 1;
|
1757 |
return EXCP_HLT;
|
1758 |
} |
1759 |
|
1760 |
return 0; |
1761 |
} |
1762 |
|
1763 |
static int kvm_handle_tpr_access(CPUState *env) |
1764 |
{ |
1765 |
struct kvm_run *run = env->kvm_run;
|
1766 |
|
1767 |
apic_handle_tpr_access_report(env->apic_state, run->tpr_access.rip, |
1768 |
run->tpr_access.is_write ? TPR_ACCESS_WRITE |
1769 |
: TPR_ACCESS_READ); |
1770 |
return 1; |
1771 |
} |
1772 |
|
1773 |
int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp) |
1774 |
{ |
1775 |
static const uint8_t int3 = 0xcc; |
1776 |
|
1777 |
if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) || |
1778 |
cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1)) { |
1779 |
return -EINVAL;
|
1780 |
} |
1781 |
return 0; |
1782 |
} |
1783 |
|
1784 |
int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp) |
1785 |
{ |
1786 |
uint8_t int3; |
1787 |
|
1788 |
if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc || |
1789 |
cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) { |
1790 |
return -EINVAL;
|
1791 |
} |
1792 |
return 0; |
1793 |
} |
1794 |
|
1795 |
static struct { |
1796 |
target_ulong addr; |
1797 |
int len;
|
1798 |
int type;
|
1799 |
} hw_breakpoint[4];
|
1800 |
|
1801 |
static int nb_hw_breakpoint; |
1802 |
|
1803 |
static int find_hw_breakpoint(target_ulong addr, int len, int type) |
1804 |
{ |
1805 |
int n;
|
1806 |
|
1807 |
for (n = 0; n < nb_hw_breakpoint; n++) { |
1808 |
if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
|
1809 |
(hw_breakpoint[n].len == len || len == -1)) {
|
1810 |
return n;
|
1811 |
} |
1812 |
} |
1813 |
return -1; |
1814 |
} |
1815 |
|
1816 |
int kvm_arch_insert_hw_breakpoint(target_ulong addr,
|
1817 |
target_ulong len, int type)
|
1818 |
{ |
1819 |
switch (type) {
|
1820 |
case GDB_BREAKPOINT_HW:
|
1821 |
len = 1;
|
1822 |
break;
|
1823 |
case GDB_WATCHPOINT_WRITE:
|
1824 |
case GDB_WATCHPOINT_ACCESS:
|
1825 |
switch (len) {
|
1826 |
case 1: |
1827 |
break;
|
1828 |
case 2: |
1829 |
case 4: |
1830 |
case 8: |
1831 |
if (addr & (len - 1)) { |
1832 |
return -EINVAL;
|
1833 |
} |
1834 |
break;
|
1835 |
default:
|
1836 |
return -EINVAL;
|
1837 |
} |
1838 |
break;
|
1839 |
default:
|
1840 |
return -ENOSYS;
|
1841 |
} |
1842 |
|
1843 |
if (nb_hw_breakpoint == 4) { |
1844 |
return -ENOBUFS;
|
1845 |
} |
1846 |
if (find_hw_breakpoint(addr, len, type) >= 0) { |
1847 |
return -EEXIST;
|
1848 |
} |
1849 |
hw_breakpoint[nb_hw_breakpoint].addr = addr; |
1850 |
hw_breakpoint[nb_hw_breakpoint].len = len; |
1851 |
hw_breakpoint[nb_hw_breakpoint].type = type; |
1852 |
nb_hw_breakpoint++; |
1853 |
|
1854 |
return 0; |
1855 |
} |
1856 |
|
1857 |
int kvm_arch_remove_hw_breakpoint(target_ulong addr,
|
1858 |
target_ulong len, int type)
|
1859 |
{ |
1860 |
int n;
|
1861 |
|
1862 |
n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
|
1863 |
if (n < 0) { |
1864 |
return -ENOENT;
|
1865 |
} |
1866 |
nb_hw_breakpoint--; |
1867 |
hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint]; |
1868 |
|
1869 |
return 0; |
1870 |
} |
1871 |
|
1872 |
void kvm_arch_remove_all_hw_breakpoints(void) |
1873 |
{ |
1874 |
nb_hw_breakpoint = 0;
|
1875 |
} |
1876 |
|
1877 |
static CPUWatchpoint hw_watchpoint;
|
1878 |
|
1879 |
static int kvm_handle_debug(struct kvm_debug_exit_arch *arch_info) |
1880 |
{ |
1881 |
int ret = 0; |
1882 |
int n;
|
1883 |
|
1884 |
if (arch_info->exception == 1) { |
1885 |
if (arch_info->dr6 & (1 << 14)) { |
1886 |
if (cpu_single_env->singlestep_enabled) {
|
1887 |
ret = EXCP_DEBUG; |
1888 |
} |
1889 |
} else {
|
1890 |
for (n = 0; n < 4; n++) { |
1891 |
if (arch_info->dr6 & (1 << n)) { |
1892 |
switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) { |
1893 |
case 0x0: |
1894 |
ret = EXCP_DEBUG; |
1895 |
break;
|
1896 |
case 0x1: |
1897 |
ret = EXCP_DEBUG; |
1898 |
cpu_single_env->watchpoint_hit = &hw_watchpoint; |
1899 |
hw_watchpoint.vaddr = hw_breakpoint[n].addr; |
1900 |
hw_watchpoint.flags = BP_MEM_WRITE; |
1901 |
break;
|
1902 |
case 0x3: |
1903 |
ret = EXCP_DEBUG; |
1904 |
cpu_single_env->watchpoint_hit = &hw_watchpoint; |
1905 |
hw_watchpoint.vaddr = hw_breakpoint[n].addr; |
1906 |
hw_watchpoint.flags = BP_MEM_ACCESS; |
1907 |
break;
|
1908 |
} |
1909 |
} |
1910 |
} |
1911 |
} |
1912 |
} else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc)) { |
1913 |
ret = EXCP_DEBUG; |
1914 |
} |
1915 |
if (ret == 0) { |
1916 |
cpu_synchronize_state(cpu_single_env); |
1917 |
assert(cpu_single_env->exception_injected == -1);
|
1918 |
|
1919 |
/* pass to guest */
|
1920 |
cpu_single_env->exception_injected = arch_info->exception; |
1921 |
cpu_single_env->has_error_code = 0;
|
1922 |
} |
1923 |
|
1924 |
return ret;
|
1925 |
} |
1926 |
|
1927 |
void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg) |
1928 |
{ |
1929 |
const uint8_t type_code[] = {
|
1930 |
[GDB_BREAKPOINT_HW] = 0x0,
|
1931 |
[GDB_WATCHPOINT_WRITE] = 0x1,
|
1932 |
[GDB_WATCHPOINT_ACCESS] = 0x3
|
1933 |
}; |
1934 |
const uint8_t len_code[] = {
|
1935 |
[1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2 |
1936 |
}; |
1937 |
int n;
|
1938 |
|
1939 |
if (kvm_sw_breakpoints_active(env)) {
|
1940 |
dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP; |
1941 |
} |
1942 |
if (nb_hw_breakpoint > 0) { |
1943 |
dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP; |
1944 |
dbg->arch.debugreg[7] = 0x0600; |
1945 |
for (n = 0; n < nb_hw_breakpoint; n++) { |
1946 |
dbg->arch.debugreg[n] = hw_breakpoint[n].addr; |
1947 |
dbg->arch.debugreg[7] |= (2 << (n * 2)) | |
1948 |
(type_code[hw_breakpoint[n].type] << (16 + n*4)) | |
1949 |
((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4)); |
1950 |
} |
1951 |
} |
1952 |
} |
1953 |
|
1954 |
static bool host_supports_vmx(void) |
1955 |
{ |
1956 |
uint32_t ecx, unused; |
1957 |
|
1958 |
host_cpuid(1, 0, &unused, &unused, &ecx, &unused); |
1959 |
return ecx & CPUID_EXT_VMX;
|
1960 |
} |
1961 |
|
1962 |
#define VMX_INVALID_GUEST_STATE 0x80000021 |
1963 |
|
1964 |
int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run) |
1965 |
{ |
1966 |
uint64_t code; |
1967 |
int ret;
|
1968 |
|
1969 |
switch (run->exit_reason) {
|
1970 |
case KVM_EXIT_HLT:
|
1971 |
DPRINTF("handle_hlt\n");
|
1972 |
ret = kvm_handle_halt(env); |
1973 |
break;
|
1974 |
case KVM_EXIT_SET_TPR:
|
1975 |
ret = 0;
|
1976 |
break;
|
1977 |
case KVM_EXIT_TPR_ACCESS:
|
1978 |
ret = kvm_handle_tpr_access(env); |
1979 |
break;
|
1980 |
case KVM_EXIT_FAIL_ENTRY:
|
1981 |
code = run->fail_entry.hardware_entry_failure_reason; |
1982 |
fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n", |
1983 |
code); |
1984 |
if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
|
1985 |
fprintf(stderr, |
1986 |
"\nIf you're running a guest on an Intel machine without "
|
1987 |
"unrestricted mode\n"
|
1988 |
"support, the failure can be most likely due to the guest "
|
1989 |
"entering an invalid\n"
|
1990 |
"state for Intel VT. For example, the guest maybe running "
|
1991 |
"in big real mode\n"
|
1992 |
"which is not supported on less recent Intel processors."
|
1993 |
"\n\n");
|
1994 |
} |
1995 |
ret = -1;
|
1996 |
break;
|
1997 |
case KVM_EXIT_EXCEPTION:
|
1998 |
fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
|
1999 |
run->ex.exception, run->ex.error_code); |
2000 |
ret = -1;
|
2001 |
break;
|
2002 |
case KVM_EXIT_DEBUG:
|
2003 |
DPRINTF("kvm_exit_debug\n");
|
2004 |
ret = kvm_handle_debug(&run->debug.arch); |
2005 |
break;
|
2006 |
default:
|
2007 |
fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
|
2008 |
ret = -1;
|
2009 |
break;
|
2010 |
} |
2011 |
|
2012 |
return ret;
|
2013 |
} |
2014 |
|
2015 |
bool kvm_arch_stop_on_emulation_error(CPUState *env)
|
2016 |
{ |
2017 |
kvm_cpu_synchronize_state(env); |
2018 |
return !(env->cr[0] & CR0_PE_MASK) || |
2019 |
((env->segs[R_CS].selector & 3) != 3); |
2020 |
} |
2021 |
|
2022 |
void kvm_arch_init_irq_routing(KVMState *s)
|
2023 |
{ |
2024 |
if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
|
2025 |
/* If kernel can't do irq routing, interrupt source
|
2026 |
* override 0->2 cannot be set up as required by HPET.
|
2027 |
* So we have to disable it.
|
2028 |
*/
|
2029 |
no_hpet = 1;
|
2030 |
} |
2031 |
} |