root / hw / slavio_misc.c @ 7ed208c4
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1 | 3475187d | bellard | /*
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2 | 3475187d | bellard | * QEMU Sparc SLAVIO aux io port emulation
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3 | 5fafdf24 | ths | *
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4 | 3475187d | bellard | * Copyright (c) 2005 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 3475187d | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 3475187d | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 3475187d | bellard | * in the Software without restriction, including without limitation the rights
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9 | 3475187d | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 3475187d | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 3475187d | bellard | * furnished to do so, subject to the following conditions:
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12 | 3475187d | bellard | *
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13 | 3475187d | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 3475187d | bellard | * all copies or substantial portions of the Software.
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15 | 3475187d | bellard | *
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16 | 3475187d | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 3475187d | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 3475187d | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 3475187d | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 3475187d | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 3475187d | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 3475187d | bellard | * THE SOFTWARE.
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23 | 3475187d | bellard | */
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24 | 2582cfa0 | Blue Swirl | |
25 | 87ecb68b | pbrook | #include "sun4m.h" |
26 | 87ecb68b | pbrook | #include "sysemu.h" |
27 | 2582cfa0 | Blue Swirl | #include "sysbus.h" |
28 | 87ecb68b | pbrook | |
29 | 3475187d | bellard | /* debug misc */
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30 | 3475187d | bellard | //#define DEBUG_MISC
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31 | 3475187d | bellard | |
32 | 3475187d | bellard | /*
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33 | 3475187d | bellard | * This is the auxio port, chip control and system control part of
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34 | 3475187d | bellard | * chip STP2001 (Slave I/O), also produced as NCR89C105. See
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35 | 3475187d | bellard | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
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36 | 3475187d | bellard | *
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37 | 3475187d | bellard | * This also includes the PMC CPU idle controller.
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38 | 3475187d | bellard | */
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39 | 3475187d | bellard | |
40 | 3475187d | bellard | #ifdef DEBUG_MISC
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41 | 001faf32 | Blue Swirl | #define MISC_DPRINTF(fmt, ...) \
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42 | 001faf32 | Blue Swirl | do { printf("MISC: " fmt , ## __VA_ARGS__); } while (0) |
43 | 3475187d | bellard | #else
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44 | 001faf32 | Blue Swirl | #define MISC_DPRINTF(fmt, ...)
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45 | 3475187d | bellard | #endif
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46 | 3475187d | bellard | |
47 | 3475187d | bellard | typedef struct MiscState { |
48 | 2582cfa0 | Blue Swirl | SysBusDevice busdev; |
49 | d537cf6c | pbrook | qemu_irq irq; |
50 | 3475187d | bellard | uint8_t config; |
51 | 3475187d | bellard | uint8_t aux1, aux2; |
52 | bfa30a38 | blueswir1 | uint8_t diag, mctrl; |
53 | bfa30a38 | blueswir1 | uint32_t sysctrl; |
54 | 6a3b9cc9 | blueswir1 | uint16_t leds; |
55 | 2be17ebd | blueswir1 | qemu_irq fdc_tc; |
56 | 3475187d | bellard | } MiscState; |
57 | 3475187d | bellard | |
58 | 2582cfa0 | Blue Swirl | typedef struct APCState { |
59 | 2582cfa0 | Blue Swirl | SysBusDevice busdev; |
60 | 2582cfa0 | Blue Swirl | qemu_irq cpu_halt; |
61 | 2582cfa0 | Blue Swirl | } APCState; |
62 | 2582cfa0 | Blue Swirl | |
63 | 5aca8c3b | blueswir1 | #define MISC_SIZE 1 |
64 | a8f48dcc | blueswir1 | #define SYSCTRL_SIZE 4 |
65 | 3475187d | bellard | |
66 | 7debeb82 | blueswir1 | #define MISC_LEDS 0x01600000 |
67 | 7debeb82 | blueswir1 | #define MISC_CFG 0x01800000 |
68 | 7debeb82 | blueswir1 | #define MISC_DIAG 0x01a00000 |
69 | 7debeb82 | blueswir1 | #define MISC_MDM 0x01b00000 |
70 | 7debeb82 | blueswir1 | #define MISC_SYS 0x01f00000 |
71 | 7debeb82 | blueswir1 | |
72 | 2be17ebd | blueswir1 | #define AUX1_TC 0x02 |
73 | 2be17ebd | blueswir1 | |
74 | 7debeb82 | blueswir1 | #define AUX2_PWROFF 0x01 |
75 | 7debeb82 | blueswir1 | #define AUX2_PWRINTCLR 0x02 |
76 | 7debeb82 | blueswir1 | #define AUX2_PWRFAIL 0x20 |
77 | 7debeb82 | blueswir1 | |
78 | 7debeb82 | blueswir1 | #define CFG_PWRINTEN 0x08 |
79 | 7debeb82 | blueswir1 | |
80 | 7debeb82 | blueswir1 | #define SYS_RESET 0x01 |
81 | 7debeb82 | blueswir1 | #define SYS_RESETSTAT 0x02 |
82 | 7debeb82 | blueswir1 | |
83 | 3475187d | bellard | static void slavio_misc_update_irq(void *opaque) |
84 | 3475187d | bellard | { |
85 | 3475187d | bellard | MiscState *s = opaque; |
86 | 3475187d | bellard | |
87 | 7debeb82 | blueswir1 | if ((s->aux2 & AUX2_PWRFAIL) && (s->config & CFG_PWRINTEN)) {
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88 | d537cf6c | pbrook | MISC_DPRINTF("Raise IRQ\n");
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89 | d537cf6c | pbrook | qemu_irq_raise(s->irq); |
90 | 3475187d | bellard | } else {
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91 | d537cf6c | pbrook | MISC_DPRINTF("Lower IRQ\n");
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92 | d537cf6c | pbrook | qemu_irq_lower(s->irq); |
93 | 3475187d | bellard | } |
94 | 3475187d | bellard | } |
95 | 3475187d | bellard | |
96 | 3475187d | bellard | static void slavio_misc_reset(void *opaque) |
97 | 3475187d | bellard | { |
98 | 3475187d | bellard | MiscState *s = opaque; |
99 | 3475187d | bellard | |
100 | 4e3b1ea1 | bellard | // Diagnostic and system control registers not cleared in reset
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101 | 3475187d | bellard | s->config = s->aux1 = s->aux2 = s->mctrl = 0;
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102 | 3475187d | bellard | } |
103 | 3475187d | bellard | |
104 | 3475187d | bellard | void slavio_set_power_fail(void *opaque, int power_failing) |
105 | 3475187d | bellard | { |
106 | 3475187d | bellard | MiscState *s = opaque; |
107 | 3475187d | bellard | |
108 | 3475187d | bellard | MISC_DPRINTF("Power fail: %d, config: %d\n", power_failing, s->config);
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109 | 7debeb82 | blueswir1 | if (power_failing && (s->config & CFG_PWRINTEN)) {
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110 | 7debeb82 | blueswir1 | s->aux2 |= AUX2_PWRFAIL; |
111 | 3475187d | bellard | } else {
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112 | 7debeb82 | blueswir1 | s->aux2 &= ~AUX2_PWRFAIL; |
113 | 3475187d | bellard | } |
114 | 3475187d | bellard | slavio_misc_update_irq(s); |
115 | 3475187d | bellard | } |
116 | 3475187d | bellard | |
117 | a8f48dcc | blueswir1 | static void slavio_cfg_mem_writeb(void *opaque, target_phys_addr_t addr, |
118 | a8f48dcc | blueswir1 | uint32_t val) |
119 | a8f48dcc | blueswir1 | { |
120 | a8f48dcc | blueswir1 | MiscState *s = opaque; |
121 | a8f48dcc | blueswir1 | |
122 | a8f48dcc | blueswir1 | MISC_DPRINTF("Write config %2.2x\n", val & 0xff); |
123 | a8f48dcc | blueswir1 | s->config = val & 0xff;
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124 | a8f48dcc | blueswir1 | slavio_misc_update_irq(s); |
125 | a8f48dcc | blueswir1 | } |
126 | a8f48dcc | blueswir1 | |
127 | a8f48dcc | blueswir1 | static uint32_t slavio_cfg_mem_readb(void *opaque, target_phys_addr_t addr) |
128 | a8f48dcc | blueswir1 | { |
129 | a8f48dcc | blueswir1 | MiscState *s = opaque; |
130 | a8f48dcc | blueswir1 | uint32_t ret = 0;
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131 | a8f48dcc | blueswir1 | |
132 | a8f48dcc | blueswir1 | ret = s->config; |
133 | a8f48dcc | blueswir1 | MISC_DPRINTF("Read config %2.2x\n", ret);
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134 | a8f48dcc | blueswir1 | return ret;
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135 | a8f48dcc | blueswir1 | } |
136 | a8f48dcc | blueswir1 | |
137 | a8f48dcc | blueswir1 | static CPUReadMemoryFunc *slavio_cfg_mem_read[3] = { |
138 | a8f48dcc | blueswir1 | slavio_cfg_mem_readb, |
139 | a8f48dcc | blueswir1 | NULL,
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140 | a8f48dcc | blueswir1 | NULL,
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141 | a8f48dcc | blueswir1 | }; |
142 | a8f48dcc | blueswir1 | |
143 | a8f48dcc | blueswir1 | static CPUWriteMemoryFunc *slavio_cfg_mem_write[3] = { |
144 | a8f48dcc | blueswir1 | slavio_cfg_mem_writeb, |
145 | a8f48dcc | blueswir1 | NULL,
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146 | a8f48dcc | blueswir1 | NULL,
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147 | a8f48dcc | blueswir1 | }; |
148 | a8f48dcc | blueswir1 | |
149 | a8f48dcc | blueswir1 | static void slavio_diag_mem_writeb(void *opaque, target_phys_addr_t addr, |
150 | bfa30a38 | blueswir1 | uint32_t val) |
151 | 3475187d | bellard | { |
152 | 3475187d | bellard | MiscState *s = opaque; |
153 | 3475187d | bellard | |
154 | a8f48dcc | blueswir1 | MISC_DPRINTF("Write diag %2.2x\n", val & 0xff); |
155 | a8f48dcc | blueswir1 | s->diag = val & 0xff;
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156 | 3475187d | bellard | } |
157 | 3475187d | bellard | |
158 | a8f48dcc | blueswir1 | static uint32_t slavio_diag_mem_readb(void *opaque, target_phys_addr_t addr) |
159 | 3475187d | bellard | { |
160 | 3475187d | bellard | MiscState *s = opaque; |
161 | 3475187d | bellard | uint32_t ret = 0;
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162 | 3475187d | bellard | |
163 | a8f48dcc | blueswir1 | ret = s->diag; |
164 | a8f48dcc | blueswir1 | MISC_DPRINTF("Read diag %2.2x\n", ret);
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165 | a8f48dcc | blueswir1 | return ret;
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166 | a8f48dcc | blueswir1 | } |
167 | a8f48dcc | blueswir1 | |
168 | a8f48dcc | blueswir1 | static CPUReadMemoryFunc *slavio_diag_mem_read[3] = { |
169 | a8f48dcc | blueswir1 | slavio_diag_mem_readb, |
170 | a8f48dcc | blueswir1 | NULL,
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171 | a8f48dcc | blueswir1 | NULL,
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172 | a8f48dcc | blueswir1 | }; |
173 | a8f48dcc | blueswir1 | |
174 | a8f48dcc | blueswir1 | static CPUWriteMemoryFunc *slavio_diag_mem_write[3] = { |
175 | a8f48dcc | blueswir1 | slavio_diag_mem_writeb, |
176 | a8f48dcc | blueswir1 | NULL,
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177 | a8f48dcc | blueswir1 | NULL,
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178 | a8f48dcc | blueswir1 | }; |
179 | a8f48dcc | blueswir1 | |
180 | a8f48dcc | blueswir1 | static void slavio_mdm_mem_writeb(void *opaque, target_phys_addr_t addr, |
181 | a8f48dcc | blueswir1 | uint32_t val) |
182 | a8f48dcc | blueswir1 | { |
183 | a8f48dcc | blueswir1 | MiscState *s = opaque; |
184 | a8f48dcc | blueswir1 | |
185 | a8f48dcc | blueswir1 | MISC_DPRINTF("Write modem control %2.2x\n", val & 0xff); |
186 | a8f48dcc | blueswir1 | s->mctrl = val & 0xff;
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187 | a8f48dcc | blueswir1 | } |
188 | a8f48dcc | blueswir1 | |
189 | a8f48dcc | blueswir1 | static uint32_t slavio_mdm_mem_readb(void *opaque, target_phys_addr_t addr) |
190 | a8f48dcc | blueswir1 | { |
191 | a8f48dcc | blueswir1 | MiscState *s = opaque; |
192 | a8f48dcc | blueswir1 | uint32_t ret = 0;
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193 | a8f48dcc | blueswir1 | |
194 | a8f48dcc | blueswir1 | ret = s->mctrl; |
195 | a8f48dcc | blueswir1 | MISC_DPRINTF("Read modem control %2.2x\n", ret);
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196 | 3475187d | bellard | return ret;
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197 | 3475187d | bellard | } |
198 | 3475187d | bellard | |
199 | a8f48dcc | blueswir1 | static CPUReadMemoryFunc *slavio_mdm_mem_read[3] = { |
200 | a8f48dcc | blueswir1 | slavio_mdm_mem_readb, |
201 | 7c560456 | blueswir1 | NULL,
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202 | 7c560456 | blueswir1 | NULL,
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203 | 3475187d | bellard | }; |
204 | 3475187d | bellard | |
205 | a8f48dcc | blueswir1 | static CPUWriteMemoryFunc *slavio_mdm_mem_write[3] = { |
206 | a8f48dcc | blueswir1 | slavio_mdm_mem_writeb, |
207 | 7c560456 | blueswir1 | NULL,
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208 | 7c560456 | blueswir1 | NULL,
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209 | 3475187d | bellard | }; |
210 | 3475187d | bellard | |
211 | 0019ad53 | blueswir1 | static void slavio_aux1_mem_writeb(void *opaque, target_phys_addr_t addr, |
212 | 0019ad53 | blueswir1 | uint32_t val) |
213 | 0019ad53 | blueswir1 | { |
214 | 0019ad53 | blueswir1 | MiscState *s = opaque; |
215 | 0019ad53 | blueswir1 | |
216 | 0019ad53 | blueswir1 | MISC_DPRINTF("Write aux1 %2.2x\n", val & 0xff); |
217 | 2be17ebd | blueswir1 | if (val & AUX1_TC) {
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218 | 2be17ebd | blueswir1 | // Send a pulse to floppy terminal count line
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219 | 2be17ebd | blueswir1 | if (s->fdc_tc) {
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220 | 2be17ebd | blueswir1 | qemu_irq_raise(s->fdc_tc); |
221 | 2be17ebd | blueswir1 | qemu_irq_lower(s->fdc_tc); |
222 | 2be17ebd | blueswir1 | } |
223 | 2be17ebd | blueswir1 | val &= ~AUX1_TC; |
224 | 2be17ebd | blueswir1 | } |
225 | 0019ad53 | blueswir1 | s->aux1 = val & 0xff;
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226 | 0019ad53 | blueswir1 | } |
227 | 0019ad53 | blueswir1 | |
228 | 0019ad53 | blueswir1 | static uint32_t slavio_aux1_mem_readb(void *opaque, target_phys_addr_t addr) |
229 | 0019ad53 | blueswir1 | { |
230 | 0019ad53 | blueswir1 | MiscState *s = opaque; |
231 | 0019ad53 | blueswir1 | uint32_t ret = 0;
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232 | 0019ad53 | blueswir1 | |
233 | 0019ad53 | blueswir1 | ret = s->aux1; |
234 | 0019ad53 | blueswir1 | MISC_DPRINTF("Read aux1 %2.2x\n", ret);
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235 | 0019ad53 | blueswir1 | |
236 | 0019ad53 | blueswir1 | return ret;
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237 | 0019ad53 | blueswir1 | } |
238 | 0019ad53 | blueswir1 | |
239 | 0019ad53 | blueswir1 | static CPUReadMemoryFunc *slavio_aux1_mem_read[3] = { |
240 | 0019ad53 | blueswir1 | slavio_aux1_mem_readb, |
241 | 0019ad53 | blueswir1 | NULL,
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242 | 0019ad53 | blueswir1 | NULL,
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243 | 0019ad53 | blueswir1 | }; |
244 | 0019ad53 | blueswir1 | |
245 | 0019ad53 | blueswir1 | static CPUWriteMemoryFunc *slavio_aux1_mem_write[3] = { |
246 | 0019ad53 | blueswir1 | slavio_aux1_mem_writeb, |
247 | 0019ad53 | blueswir1 | NULL,
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248 | 0019ad53 | blueswir1 | NULL,
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249 | 0019ad53 | blueswir1 | }; |
250 | 0019ad53 | blueswir1 | |
251 | 0019ad53 | blueswir1 | static void slavio_aux2_mem_writeb(void *opaque, target_phys_addr_t addr, |
252 | 0019ad53 | blueswir1 | uint32_t val) |
253 | 0019ad53 | blueswir1 | { |
254 | 0019ad53 | blueswir1 | MiscState *s = opaque; |
255 | 0019ad53 | blueswir1 | |
256 | 0019ad53 | blueswir1 | val &= AUX2_PWRINTCLR | AUX2_PWROFF; |
257 | 0019ad53 | blueswir1 | MISC_DPRINTF("Write aux2 %2.2x\n", val);
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258 | 0019ad53 | blueswir1 | val |= s->aux2 & AUX2_PWRFAIL; |
259 | 0019ad53 | blueswir1 | if (val & AUX2_PWRINTCLR) // Clear Power Fail int |
260 | 0019ad53 | blueswir1 | val &= AUX2_PWROFF; |
261 | 0019ad53 | blueswir1 | s->aux2 = val; |
262 | 0019ad53 | blueswir1 | if (val & AUX2_PWROFF)
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263 | 0019ad53 | blueswir1 | qemu_system_shutdown_request(); |
264 | 0019ad53 | blueswir1 | slavio_misc_update_irq(s); |
265 | 0019ad53 | blueswir1 | } |
266 | 0019ad53 | blueswir1 | |
267 | 0019ad53 | blueswir1 | static uint32_t slavio_aux2_mem_readb(void *opaque, target_phys_addr_t addr) |
268 | 0019ad53 | blueswir1 | { |
269 | 0019ad53 | blueswir1 | MiscState *s = opaque; |
270 | 0019ad53 | blueswir1 | uint32_t ret = 0;
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271 | 0019ad53 | blueswir1 | |
272 | 0019ad53 | blueswir1 | ret = s->aux2; |
273 | 0019ad53 | blueswir1 | MISC_DPRINTF("Read aux2 %2.2x\n", ret);
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274 | 0019ad53 | blueswir1 | |
275 | 0019ad53 | blueswir1 | return ret;
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276 | 0019ad53 | blueswir1 | } |
277 | 0019ad53 | blueswir1 | |
278 | 0019ad53 | blueswir1 | static CPUReadMemoryFunc *slavio_aux2_mem_read[3] = { |
279 | 0019ad53 | blueswir1 | slavio_aux2_mem_readb, |
280 | 0019ad53 | blueswir1 | NULL,
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281 | 0019ad53 | blueswir1 | NULL,
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282 | 0019ad53 | blueswir1 | }; |
283 | 0019ad53 | blueswir1 | |
284 | 0019ad53 | blueswir1 | static CPUWriteMemoryFunc *slavio_aux2_mem_write[3] = { |
285 | 0019ad53 | blueswir1 | slavio_aux2_mem_writeb, |
286 | 0019ad53 | blueswir1 | NULL,
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287 | 0019ad53 | blueswir1 | NULL,
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288 | 0019ad53 | blueswir1 | }; |
289 | 0019ad53 | blueswir1 | |
290 | 0019ad53 | blueswir1 | static void apc_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
291 | 0019ad53 | blueswir1 | { |
292 | 2582cfa0 | Blue Swirl | APCState *s = opaque; |
293 | 0019ad53 | blueswir1 | |
294 | 0019ad53 | blueswir1 | MISC_DPRINTF("Write power management %2.2x\n", val & 0xff); |
295 | 6d0c293d | blueswir1 | qemu_irq_raise(s->cpu_halt); |
296 | 0019ad53 | blueswir1 | } |
297 | 0019ad53 | blueswir1 | |
298 | 0019ad53 | blueswir1 | static uint32_t apc_mem_readb(void *opaque, target_phys_addr_t addr) |
299 | 0019ad53 | blueswir1 | { |
300 | 0019ad53 | blueswir1 | uint32_t ret = 0;
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301 | 0019ad53 | blueswir1 | |
302 | 0019ad53 | blueswir1 | MISC_DPRINTF("Read power management %2.2x\n", ret);
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303 | 0019ad53 | blueswir1 | return ret;
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304 | 0019ad53 | blueswir1 | } |
305 | 0019ad53 | blueswir1 | |
306 | 0019ad53 | blueswir1 | static CPUReadMemoryFunc *apc_mem_read[3] = { |
307 | 0019ad53 | blueswir1 | apc_mem_readb, |
308 | 0019ad53 | blueswir1 | NULL,
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309 | 0019ad53 | blueswir1 | NULL,
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310 | 0019ad53 | blueswir1 | }; |
311 | 0019ad53 | blueswir1 | |
312 | 0019ad53 | blueswir1 | static CPUWriteMemoryFunc *apc_mem_write[3] = { |
313 | 0019ad53 | blueswir1 | apc_mem_writeb, |
314 | 0019ad53 | blueswir1 | NULL,
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315 | 0019ad53 | blueswir1 | NULL,
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316 | 0019ad53 | blueswir1 | }; |
317 | 0019ad53 | blueswir1 | |
318 | bfa30a38 | blueswir1 | static uint32_t slavio_sysctrl_mem_readl(void *opaque, target_phys_addr_t addr) |
319 | bfa30a38 | blueswir1 | { |
320 | bfa30a38 | blueswir1 | MiscState *s = opaque; |
321 | a8f48dcc | blueswir1 | uint32_t ret = 0;
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322 | bfa30a38 | blueswir1 | |
323 | a8f48dcc | blueswir1 | switch (addr) {
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324 | bfa30a38 | blueswir1 | case 0: |
325 | bfa30a38 | blueswir1 | ret = s->sysctrl; |
326 | bfa30a38 | blueswir1 | break;
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327 | bfa30a38 | blueswir1 | default:
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328 | bfa30a38 | blueswir1 | break;
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329 | bfa30a38 | blueswir1 | } |
330 | 5626b017 | blueswir1 | MISC_DPRINTF("Read system control %08x\n", ret);
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331 | bfa30a38 | blueswir1 | return ret;
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332 | bfa30a38 | blueswir1 | } |
333 | bfa30a38 | blueswir1 | |
334 | bfa30a38 | blueswir1 | static void slavio_sysctrl_mem_writel(void *opaque, target_phys_addr_t addr, |
335 | bfa30a38 | blueswir1 | uint32_t val) |
336 | bfa30a38 | blueswir1 | { |
337 | bfa30a38 | blueswir1 | MiscState *s = opaque; |
338 | bfa30a38 | blueswir1 | |
339 | 5626b017 | blueswir1 | MISC_DPRINTF("Write system control %08x\n", val);
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340 | a8f48dcc | blueswir1 | switch (addr) {
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341 | bfa30a38 | blueswir1 | case 0: |
342 | 7debeb82 | blueswir1 | if (val & SYS_RESET) {
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343 | 7debeb82 | blueswir1 | s->sysctrl = SYS_RESETSTAT; |
344 | bfa30a38 | blueswir1 | qemu_system_reset_request(); |
345 | bfa30a38 | blueswir1 | } |
346 | bfa30a38 | blueswir1 | break;
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347 | bfa30a38 | blueswir1 | default:
|
348 | bfa30a38 | blueswir1 | break;
|
349 | bfa30a38 | blueswir1 | } |
350 | bfa30a38 | blueswir1 | } |
351 | bfa30a38 | blueswir1 | |
352 | bfa30a38 | blueswir1 | static CPUReadMemoryFunc *slavio_sysctrl_mem_read[3] = { |
353 | 7c560456 | blueswir1 | NULL,
|
354 | 7c560456 | blueswir1 | NULL,
|
355 | bfa30a38 | blueswir1 | slavio_sysctrl_mem_readl, |
356 | bfa30a38 | blueswir1 | }; |
357 | bfa30a38 | blueswir1 | |
358 | bfa30a38 | blueswir1 | static CPUWriteMemoryFunc *slavio_sysctrl_mem_write[3] = { |
359 | 7c560456 | blueswir1 | NULL,
|
360 | 7c560456 | blueswir1 | NULL,
|
361 | bfa30a38 | blueswir1 | slavio_sysctrl_mem_writel, |
362 | bfa30a38 | blueswir1 | }; |
363 | bfa30a38 | blueswir1 | |
364 | 7c560456 | blueswir1 | static uint32_t slavio_led_mem_readw(void *opaque, target_phys_addr_t addr) |
365 | 6a3b9cc9 | blueswir1 | { |
366 | 6a3b9cc9 | blueswir1 | MiscState *s = opaque; |
367 | a8f48dcc | blueswir1 | uint32_t ret = 0;
|
368 | 6a3b9cc9 | blueswir1 | |
369 | a8f48dcc | blueswir1 | switch (addr) {
|
370 | 6a3b9cc9 | blueswir1 | case 0: |
371 | 6a3b9cc9 | blueswir1 | ret = s->leds; |
372 | 6a3b9cc9 | blueswir1 | break;
|
373 | 6a3b9cc9 | blueswir1 | default:
|
374 | 6a3b9cc9 | blueswir1 | break;
|
375 | 6a3b9cc9 | blueswir1 | } |
376 | 5626b017 | blueswir1 | MISC_DPRINTF("Read diagnostic LED %04x\n", ret);
|
377 | 6a3b9cc9 | blueswir1 | return ret;
|
378 | 6a3b9cc9 | blueswir1 | } |
379 | 6a3b9cc9 | blueswir1 | |
380 | 7c560456 | blueswir1 | static void slavio_led_mem_writew(void *opaque, target_phys_addr_t addr, |
381 | 6a3b9cc9 | blueswir1 | uint32_t val) |
382 | 6a3b9cc9 | blueswir1 | { |
383 | 6a3b9cc9 | blueswir1 | MiscState *s = opaque; |
384 | 6a3b9cc9 | blueswir1 | |
385 | 5626b017 | blueswir1 | MISC_DPRINTF("Write diagnostic LED %04x\n", val & 0xffff); |
386 | a8f48dcc | blueswir1 | switch (addr) {
|
387 | 6a3b9cc9 | blueswir1 | case 0: |
388 | d5296cb5 | blueswir1 | s->leds = val; |
389 | 6a3b9cc9 | blueswir1 | break;
|
390 | 6a3b9cc9 | blueswir1 | default:
|
391 | 6a3b9cc9 | blueswir1 | break;
|
392 | 6a3b9cc9 | blueswir1 | } |
393 | 6a3b9cc9 | blueswir1 | } |
394 | 6a3b9cc9 | blueswir1 | |
395 | 6a3b9cc9 | blueswir1 | static CPUReadMemoryFunc *slavio_led_mem_read[3] = { |
396 | 7c560456 | blueswir1 | NULL,
|
397 | 7c560456 | blueswir1 | slavio_led_mem_readw, |
398 | 7c560456 | blueswir1 | NULL,
|
399 | 6a3b9cc9 | blueswir1 | }; |
400 | 6a3b9cc9 | blueswir1 | |
401 | 6a3b9cc9 | blueswir1 | static CPUWriteMemoryFunc *slavio_led_mem_write[3] = { |
402 | 7c560456 | blueswir1 | NULL,
|
403 | 7c560456 | blueswir1 | slavio_led_mem_writew, |
404 | 7c560456 | blueswir1 | NULL,
|
405 | 6a3b9cc9 | blueswir1 | }; |
406 | 6a3b9cc9 | blueswir1 | |
407 | 3475187d | bellard | static void slavio_misc_save(QEMUFile *f, void *opaque) |
408 | 3475187d | bellard | { |
409 | 3475187d | bellard | MiscState *s = opaque; |
410 | 22548760 | blueswir1 | uint32_t tmp = 0;
|
411 | bfa30a38 | blueswir1 | uint8_t tmp8; |
412 | 3475187d | bellard | |
413 | d537cf6c | pbrook | qemu_put_be32s(f, &tmp); /* ignored, was IRQ. */
|
414 | 3475187d | bellard | qemu_put_8s(f, &s->config); |
415 | 3475187d | bellard | qemu_put_8s(f, &s->aux1); |
416 | 3475187d | bellard | qemu_put_8s(f, &s->aux2); |
417 | 3475187d | bellard | qemu_put_8s(f, &s->diag); |
418 | 3475187d | bellard | qemu_put_8s(f, &s->mctrl); |
419 | bfa30a38 | blueswir1 | tmp8 = s->sysctrl & 0xff;
|
420 | bfa30a38 | blueswir1 | qemu_put_8s(f, &tmp8); |
421 | 3475187d | bellard | } |
422 | 3475187d | bellard | |
423 | 3475187d | bellard | static int slavio_misc_load(QEMUFile *f, void *opaque, int version_id) |
424 | 3475187d | bellard | { |
425 | 3475187d | bellard | MiscState *s = opaque; |
426 | 22548760 | blueswir1 | uint32_t tmp; |
427 | bfa30a38 | blueswir1 | uint8_t tmp8; |
428 | 3475187d | bellard | |
429 | 3475187d | bellard | if (version_id != 1) |
430 | 3475187d | bellard | return -EINVAL;
|
431 | 3475187d | bellard | |
432 | d537cf6c | pbrook | qemu_get_be32s(f, &tmp); |
433 | 3475187d | bellard | qemu_get_8s(f, &s->config); |
434 | 3475187d | bellard | qemu_get_8s(f, &s->aux1); |
435 | 3475187d | bellard | qemu_get_8s(f, &s->aux2); |
436 | 3475187d | bellard | qemu_get_8s(f, &s->diag); |
437 | 3475187d | bellard | qemu_get_8s(f, &s->mctrl); |
438 | bfa30a38 | blueswir1 | qemu_get_8s(f, &tmp8); |
439 | bfa30a38 | blueswir1 | s->sysctrl = (uint32_t)tmp8; |
440 | 3475187d | bellard | return 0; |
441 | 3475187d | bellard | } |
442 | 3475187d | bellard | |
443 | 2582cfa0 | Blue Swirl | void *slavio_misc_init(target_phys_addr_t base,
|
444 | 0019ad53 | blueswir1 | target_phys_addr_t aux1_base, |
445 | 0019ad53 | blueswir1 | target_phys_addr_t aux2_base, qemu_irq irq, |
446 | 2582cfa0 | Blue Swirl | qemu_irq fdc_tc) |
447 | 3475187d | bellard | { |
448 | 2582cfa0 | Blue Swirl | DeviceState *dev; |
449 | 2582cfa0 | Blue Swirl | SysBusDevice *s; |
450 | 2582cfa0 | Blue Swirl | MiscState *d; |
451 | 3475187d | bellard | |
452 | 2582cfa0 | Blue Swirl | dev = qdev_create(NULL, "slavio_misc"); |
453 | 2582cfa0 | Blue Swirl | qdev_init(dev); |
454 | 2582cfa0 | Blue Swirl | s = sysbus_from_qdev(dev); |
455 | 0019ad53 | blueswir1 | if (base) {
|
456 | 0019ad53 | blueswir1 | /* 8 bit registers */
|
457 | 2582cfa0 | Blue Swirl | /* Slavio control */
|
458 | 2582cfa0 | Blue Swirl | sysbus_mmio_map(s, 0, base + MISC_CFG);
|
459 | 2582cfa0 | Blue Swirl | /* Diagnostics */
|
460 | 2582cfa0 | Blue Swirl | sysbus_mmio_map(s, 1, base + MISC_DIAG);
|
461 | 2582cfa0 | Blue Swirl | /* Modem control */
|
462 | 2582cfa0 | Blue Swirl | sysbus_mmio_map(s, 2, base + MISC_MDM);
|
463 | 0019ad53 | blueswir1 | /* 16 bit registers */
|
464 | 0019ad53 | blueswir1 | /* ss600mp diag LEDs */
|
465 | 2582cfa0 | Blue Swirl | sysbus_mmio_map(s, 3, base + MISC_LEDS);
|
466 | 0019ad53 | blueswir1 | /* 32 bit registers */
|
467 | 2582cfa0 | Blue Swirl | /* System control */
|
468 | 2582cfa0 | Blue Swirl | sysbus_mmio_map(s, 4, base + MISC_SYS);
|
469 | 0019ad53 | blueswir1 | } |
470 | 0019ad53 | blueswir1 | if (aux1_base) {
|
471 | 2582cfa0 | Blue Swirl | /* AUX 1 (Misc System Functions) */
|
472 | 2582cfa0 | Blue Swirl | sysbus_mmio_map(s, 5, aux1_base);
|
473 | 0019ad53 | blueswir1 | } |
474 | 0019ad53 | blueswir1 | if (aux2_base) {
|
475 | 2582cfa0 | Blue Swirl | /* AUX 2 (Software Powerdown Control) */
|
476 | 2582cfa0 | Blue Swirl | sysbus_mmio_map(s, 6, aux2_base);
|
477 | 0019ad53 | blueswir1 | } |
478 | 2582cfa0 | Blue Swirl | sysbus_connect_irq(s, 0, irq);
|
479 | 2582cfa0 | Blue Swirl | sysbus_connect_irq(s, 1, fdc_tc);
|
480 | 0019ad53 | blueswir1 | |
481 | 2582cfa0 | Blue Swirl | d = FROM_SYSBUS(MiscState, s); |
482 | bfa30a38 | blueswir1 | |
483 | 2582cfa0 | Blue Swirl | return d;
|
484 | 2582cfa0 | Blue Swirl | } |
485 | 2582cfa0 | Blue Swirl | |
486 | 2582cfa0 | Blue Swirl | static void apc_init1(SysBusDevice *dev) |
487 | 2582cfa0 | Blue Swirl | { |
488 | 2582cfa0 | Blue Swirl | APCState *s = FROM_SYSBUS(APCState, dev); |
489 | 2582cfa0 | Blue Swirl | int io;
|
490 | 3475187d | bellard | |
491 | 2582cfa0 | Blue Swirl | sysbus_init_irq(dev, &s->cpu_halt); |
492 | 2582cfa0 | Blue Swirl | |
493 | 2582cfa0 | Blue Swirl | /* Power management (APC) XXX: not a Slavio device */
|
494 | 2582cfa0 | Blue Swirl | io = cpu_register_io_memory(apc_mem_read, apc_mem_write, s); |
495 | 2582cfa0 | Blue Swirl | sysbus_init_mmio(dev, MISC_SIZE, io); |
496 | 2582cfa0 | Blue Swirl | } |
497 | 2582cfa0 | Blue Swirl | |
498 | 2582cfa0 | Blue Swirl | void apc_init(target_phys_addr_t power_base, qemu_irq cpu_halt)
|
499 | 2582cfa0 | Blue Swirl | { |
500 | 2582cfa0 | Blue Swirl | DeviceState *dev; |
501 | 2582cfa0 | Blue Swirl | SysBusDevice *s; |
502 | 2582cfa0 | Blue Swirl | |
503 | 2582cfa0 | Blue Swirl | dev = qdev_create(NULL, "apc"); |
504 | 2582cfa0 | Blue Swirl | qdev_init(dev); |
505 | 2582cfa0 | Blue Swirl | s = sysbus_from_qdev(dev); |
506 | 2582cfa0 | Blue Swirl | /* Power management (APC) XXX: not a Slavio device */
|
507 | 2582cfa0 | Blue Swirl | sysbus_mmio_map(s, 0, power_base);
|
508 | 2582cfa0 | Blue Swirl | sysbus_connect_irq(s, 0, cpu_halt);
|
509 | 2582cfa0 | Blue Swirl | } |
510 | 2582cfa0 | Blue Swirl | |
511 | 2582cfa0 | Blue Swirl | static void slavio_misc_init1(SysBusDevice *dev) |
512 | 2582cfa0 | Blue Swirl | { |
513 | 2582cfa0 | Blue Swirl | MiscState *s = FROM_SYSBUS(MiscState, dev); |
514 | 2582cfa0 | Blue Swirl | int io;
|
515 | 2582cfa0 | Blue Swirl | |
516 | 2582cfa0 | Blue Swirl | sysbus_init_irq(dev, &s->irq); |
517 | 2582cfa0 | Blue Swirl | sysbus_init_irq(dev, &s->fdc_tc); |
518 | 2582cfa0 | Blue Swirl | |
519 | 2582cfa0 | Blue Swirl | /* 8 bit registers */
|
520 | 2582cfa0 | Blue Swirl | /* Slavio control */
|
521 | 2582cfa0 | Blue Swirl | io = cpu_register_io_memory(slavio_cfg_mem_read, |
522 | 2582cfa0 | Blue Swirl | slavio_cfg_mem_write, s); |
523 | 2582cfa0 | Blue Swirl | sysbus_init_mmio(dev, MISC_SIZE, io); |
524 | 2582cfa0 | Blue Swirl | |
525 | 2582cfa0 | Blue Swirl | /* Diagnostics */
|
526 | 2582cfa0 | Blue Swirl | io = cpu_register_io_memory(slavio_diag_mem_read, |
527 | 2582cfa0 | Blue Swirl | slavio_diag_mem_write, s); |
528 | 2582cfa0 | Blue Swirl | sysbus_init_mmio(dev, MISC_SIZE, io); |
529 | 2582cfa0 | Blue Swirl | |
530 | 2582cfa0 | Blue Swirl | /* Modem control */
|
531 | 2582cfa0 | Blue Swirl | io = cpu_register_io_memory(slavio_mdm_mem_read, |
532 | 2582cfa0 | Blue Swirl | slavio_mdm_mem_write, s); |
533 | 2582cfa0 | Blue Swirl | sysbus_init_mmio(dev, MISC_SIZE, io); |
534 | 2582cfa0 | Blue Swirl | |
535 | 2582cfa0 | Blue Swirl | /* 16 bit registers */
|
536 | 2582cfa0 | Blue Swirl | /* ss600mp diag LEDs */
|
537 | 2582cfa0 | Blue Swirl | io = cpu_register_io_memory(slavio_led_mem_read, |
538 | 2582cfa0 | Blue Swirl | slavio_led_mem_write, s); |
539 | 2582cfa0 | Blue Swirl | sysbus_init_mmio(dev, MISC_SIZE, io); |
540 | 2582cfa0 | Blue Swirl | |
541 | 2582cfa0 | Blue Swirl | /* 32 bit registers */
|
542 | 2582cfa0 | Blue Swirl | /* System control */
|
543 | 2582cfa0 | Blue Swirl | io = cpu_register_io_memory(slavio_sysctrl_mem_read, |
544 | 2582cfa0 | Blue Swirl | slavio_sysctrl_mem_write, s); |
545 | 2582cfa0 | Blue Swirl | sysbus_init_mmio(dev, SYSCTRL_SIZE, io); |
546 | 2582cfa0 | Blue Swirl | |
547 | 2582cfa0 | Blue Swirl | /* AUX 1 (Misc System Functions) */
|
548 | 2582cfa0 | Blue Swirl | io = cpu_register_io_memory(slavio_aux1_mem_read, |
549 | 2582cfa0 | Blue Swirl | slavio_aux1_mem_write, s); |
550 | 2582cfa0 | Blue Swirl | sysbus_init_mmio(dev, MISC_SIZE, io); |
551 | 2582cfa0 | Blue Swirl | |
552 | 2582cfa0 | Blue Swirl | /* AUX 2 (Software Powerdown Control) */
|
553 | 2582cfa0 | Blue Swirl | io = cpu_register_io_memory(slavio_aux2_mem_read, |
554 | 2582cfa0 | Blue Swirl | slavio_aux2_mem_write, s); |
555 | 2582cfa0 | Blue Swirl | sysbus_init_mmio(dev, MISC_SIZE, io); |
556 | 2582cfa0 | Blue Swirl | |
557 | 2582cfa0 | Blue Swirl | register_savevm("slavio_misc", -1, 1, slavio_misc_save, slavio_misc_load, |
558 | bfa30a38 | blueswir1 | s); |
559 | a08d4367 | Jan Kiszka | qemu_register_reset(slavio_misc_reset, s); |
560 | 3475187d | bellard | slavio_misc_reset(s); |
561 | 2582cfa0 | Blue Swirl | } |
562 | 0019ad53 | blueswir1 | |
563 | 2582cfa0 | Blue Swirl | static SysBusDeviceInfo slavio_misc_info = {
|
564 | 2582cfa0 | Blue Swirl | .init = slavio_misc_init1, |
565 | 2582cfa0 | Blue Swirl | .qdev.name = "slavio_misc",
|
566 | 2582cfa0 | Blue Swirl | .qdev.size = sizeof(MiscState),
|
567 | 2582cfa0 | Blue Swirl | }; |
568 | 2582cfa0 | Blue Swirl | |
569 | 2582cfa0 | Blue Swirl | static SysBusDeviceInfo apc_info = {
|
570 | 2582cfa0 | Blue Swirl | .init = apc_init1, |
571 | 2582cfa0 | Blue Swirl | .qdev.name = "apc",
|
572 | 2582cfa0 | Blue Swirl | .qdev.size = sizeof(MiscState),
|
573 | 2582cfa0 | Blue Swirl | }; |
574 | 2582cfa0 | Blue Swirl | |
575 | 2582cfa0 | Blue Swirl | static void slavio_misc_register_devices(void) |
576 | 2582cfa0 | Blue Swirl | { |
577 | 2582cfa0 | Blue Swirl | sysbus_register_withprop(&slavio_misc_info); |
578 | 2582cfa0 | Blue Swirl | sysbus_register_withprop(&apc_info); |
579 | 3475187d | bellard | } |
580 | 2582cfa0 | Blue Swirl | |
581 | 2582cfa0 | Blue Swirl | device_init(slavio_misc_register_devices) |