Revision 7eee2a50 target-i386/cpu.h
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| 115 | 115 |
/* copy of CR0.PE (protected mode) */ |
| 116 | 116 |
#define HF_PE_SHIFT 7 |
| 117 | 117 |
#define HF_TF_SHIFT 8 /* must be same as eflags */ |
| 118 |
#define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */ |
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| 119 |
#define HF_EM_SHIFT 10 |
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| 120 |
#define HF_TS_SHIFT 11 |
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| 118 | 121 |
#define HF_IOPL_SHIFT 12 /* must be same as eflags */ |
| 119 | 122 |
#define HF_VM_SHIFT 17 /* must be same as eflags */ |
| 120 | 123 |
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| ... | ... | |
| 126 | 129 |
#define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT) |
| 127 | 130 |
#define HF_PE_MASK (1 << HF_PE_SHIFT) |
| 128 | 131 |
#define HF_TF_MASK (1 << HF_TF_SHIFT) |
| 132 |
#define HF_MP_MASK (1 << HF_MP_SHIFT) |
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| 133 |
#define HF_EM_MASK (1 << HF_EM_SHIFT) |
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| 134 |
#define HF_TS_MASK (1 << HF_TS_SHIFT) |
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| 129 | 135 |
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| 130 | 136 |
#define CR0_PE_MASK (1 << 0) |
| 137 |
#define CR0_MP_MASK (1 << 1) |
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| 138 |
#define CR0_EM_MASK (1 << 2) |
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| 131 | 139 |
#define CR0_TS_MASK (1 << 3) |
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#define CR0_NE_MASK (1 << 5) |
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| 132 | 141 |
#define CR0_WP_MASK (1 << 16) |
| 133 | 142 |
#define CR0_AM_MASK (1 << 18) |
| 134 | 143 |
#define CR0_PG_MASK (1 << 31) |
| ... | ... | |
| 280 | 289 |
unsigned int fpus; |
| 281 | 290 |
unsigned int fpuc; |
| 282 | 291 |
uint8_t fptags[8]; /* 0 = valid, 1 = empty */ |
| 283 |
CPU86_LDouble fpregs[8];
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| 292 |
CPU86_LDouble fpregs[8]; |
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| 284 | 293 |
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| 285 | 294 |
/* emulator internal variables */ |
| 286 | 295 |
CPU86_LDouble ft0; |
| ... | ... | |
| 304 | 313 |
uint32_t sysenter_eip; |
| 305 | 314 |
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| 306 | 315 |
/* temporary data for USE_CODE_COPY mode */ |
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#ifdef USE_CODE_COPY |
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| 307 | 317 |
uint32_t tmp0; |
| 308 | 318 |
uint32_t saved_esp; |
| 319 |
int native_fp_regs; /* if true, the FPU state is in the native CPU regs */ |
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| 320 |
#endif |
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| 309 | 321 |
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| 310 | 322 |
/* exception/interrupt handling */ |
| 311 | 323 |
jmp_buf jmp_env; |
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