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1 | 27503323 | bellard | /*
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2 | 27503323 | bellard | * QEMU DMA emulation
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3 | 85571bc7 | bellard | *
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4 | 85571bc7 | bellard | * Copyright (c) 2003-2004 Vassili Karpov (malc)
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5 | 85571bc7 | bellard | *
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6 | 27503323 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 27503323 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 27503323 | bellard | * in the Software without restriction, including without limitation the rights
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9 | 27503323 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 27503323 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 27503323 | bellard | * furnished to do so, subject to the following conditions:
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12 | 27503323 | bellard | *
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13 | 27503323 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 27503323 | bellard | * all copies or substantial portions of the Software.
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15 | 27503323 | bellard | *
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16 | 27503323 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 27503323 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 27503323 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 27503323 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 27503323 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 27503323 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 27503323 | bellard | * THE SOFTWARE.
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23 | 27503323 | bellard | */
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24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "isa.h" |
26 | 27503323 | bellard | |
27 | 85571bc7 | bellard | /* #define DEBUG_DMA */
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28 | 7ebb5e41 | bellard | |
29 | 85571bc7 | bellard | #define dolog(...) fprintf (stderr, "dma: " __VA_ARGS__) |
30 | 27503323 | bellard | #ifdef DEBUG_DMA
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31 | 27503323 | bellard | #define linfo(...) fprintf (stderr, "dma: " __VA_ARGS__) |
32 | 27503323 | bellard | #define ldebug(...) fprintf (stderr, "dma: " __VA_ARGS__) |
33 | 27503323 | bellard | #else
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34 | 27503323 | bellard | #define linfo(...)
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35 | 27503323 | bellard | #define ldebug(...)
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36 | 27503323 | bellard | #endif
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37 | 27503323 | bellard | |
38 | 27503323 | bellard | struct dma_regs {
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39 | 27503323 | bellard | int now[2]; |
40 | 27503323 | bellard | uint16_t base[2];
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41 | 27503323 | bellard | uint8_t mode; |
42 | 27503323 | bellard | uint8_t page; |
43 | b0bda528 | bellard | uint8_t pageh; |
44 | 27503323 | bellard | uint8_t dack; |
45 | 27503323 | bellard | uint8_t eop; |
46 | 16f62432 | bellard | DMA_transfer_handler transfer_handler; |
47 | 16f62432 | bellard | void *opaque;
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48 | 27503323 | bellard | }; |
49 | 27503323 | bellard | |
50 | 27503323 | bellard | #define ADDR 0 |
51 | 27503323 | bellard | #define COUNT 1 |
52 | 27503323 | bellard | |
53 | 27503323 | bellard | static struct dma_cont { |
54 | 27503323 | bellard | uint8_t status; |
55 | 27503323 | bellard | uint8_t command; |
56 | 27503323 | bellard | uint8_t mask; |
57 | 27503323 | bellard | uint8_t flip_flop; |
58 | 9eb153f1 | bellard | int dshift;
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59 | 27503323 | bellard | struct dma_regs regs[4]; |
60 | 4556bd8b | Blue Swirl | qemu_irq *cpu_request_exit; |
61 | 27503323 | bellard | } dma_controllers[2];
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62 | 27503323 | bellard | |
63 | 27503323 | bellard | enum {
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64 | e875c40a | bellard | CMD_MEMORY_TO_MEMORY = 0x01,
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65 | e875c40a | bellard | CMD_FIXED_ADDRESS = 0x02,
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66 | e875c40a | bellard | CMD_BLOCK_CONTROLLER = 0x04,
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67 | e875c40a | bellard | CMD_COMPRESSED_TIME = 0x08,
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68 | e875c40a | bellard | CMD_CYCLIC_PRIORITY = 0x10,
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69 | e875c40a | bellard | CMD_EXTENDED_WRITE = 0x20,
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70 | e875c40a | bellard | CMD_LOW_DREQ = 0x40,
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71 | e875c40a | bellard | CMD_LOW_DACK = 0x80,
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72 | e875c40a | bellard | CMD_NOT_SUPPORTED = CMD_MEMORY_TO_MEMORY | CMD_FIXED_ADDRESS |
73 | e875c40a | bellard | | CMD_COMPRESSED_TIME | CMD_CYCLIC_PRIORITY | CMD_EXTENDED_WRITE |
74 | e875c40a | bellard | | CMD_LOW_DREQ | CMD_LOW_DACK |
75 | 27503323 | bellard | |
76 | 27503323 | bellard | }; |
77 | 27503323 | bellard | |
78 | 492c30af | aliguori | static void DMA_run (void); |
79 | 492c30af | aliguori | |
80 | 9eb153f1 | bellard | static int channels[8] = {-1, 2, 3, 1, -1, -1, -1, 0}; |
81 | 9eb153f1 | bellard | |
82 | 7d977de7 | bellard | static void write_page (void *opaque, uint32_t nport, uint32_t data) |
83 | 27503323 | bellard | { |
84 | 9eb153f1 | bellard | struct dma_cont *d = opaque;
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85 | 27503323 | bellard | int ichan;
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86 | 27503323 | bellard | |
87 | 9eb153f1 | bellard | ichan = channels[nport & 7];
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88 | 27503323 | bellard | if (-1 == ichan) { |
89 | 85571bc7 | bellard | dolog ("invalid channel %#x %#x\n", nport, data);
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90 | 27503323 | bellard | return;
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91 | 27503323 | bellard | } |
92 | 9eb153f1 | bellard | d->regs[ichan].page = data; |
93 | 9eb153f1 | bellard | } |
94 | 9eb153f1 | bellard | |
95 | b0bda528 | bellard | static void write_pageh (void *opaque, uint32_t nport, uint32_t data) |
96 | 9eb153f1 | bellard | { |
97 | 9eb153f1 | bellard | struct dma_cont *d = opaque;
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98 | 9eb153f1 | bellard | int ichan;
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99 | 27503323 | bellard | |
100 | 9eb153f1 | bellard | ichan = channels[nport & 7];
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101 | b0bda528 | bellard | if (-1 == ichan) { |
102 | 85571bc7 | bellard | dolog ("invalid channel %#x %#x\n", nport, data);
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103 | b0bda528 | bellard | return;
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104 | b0bda528 | bellard | } |
105 | b0bda528 | bellard | d->regs[ichan].pageh = data; |
106 | b0bda528 | bellard | } |
107 | 9eb153f1 | bellard | |
108 | b0bda528 | bellard | static uint32_t read_page (void *opaque, uint32_t nport) |
109 | b0bda528 | bellard | { |
110 | b0bda528 | bellard | struct dma_cont *d = opaque;
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111 | b0bda528 | bellard | int ichan;
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112 | b0bda528 | bellard | |
113 | b0bda528 | bellard | ichan = channels[nport & 7];
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114 | 9eb153f1 | bellard | if (-1 == ichan) { |
115 | 85571bc7 | bellard | dolog ("invalid channel read %#x\n", nport);
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116 | 9eb153f1 | bellard | return 0; |
117 | 9eb153f1 | bellard | } |
118 | 9eb153f1 | bellard | return d->regs[ichan].page;
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119 | 27503323 | bellard | } |
120 | 27503323 | bellard | |
121 | b0bda528 | bellard | static uint32_t read_pageh (void *opaque, uint32_t nport) |
122 | b0bda528 | bellard | { |
123 | b0bda528 | bellard | struct dma_cont *d = opaque;
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124 | b0bda528 | bellard | int ichan;
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125 | b0bda528 | bellard | |
126 | b0bda528 | bellard | ichan = channels[nport & 7];
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127 | b0bda528 | bellard | if (-1 == ichan) { |
128 | 85571bc7 | bellard | dolog ("invalid channel read %#x\n", nport);
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129 | b0bda528 | bellard | return 0; |
130 | b0bda528 | bellard | } |
131 | b0bda528 | bellard | return d->regs[ichan].pageh;
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132 | b0bda528 | bellard | } |
133 | b0bda528 | bellard | |
134 | 9eb153f1 | bellard | static inline void init_chan (struct dma_cont *d, int ichan) |
135 | 27503323 | bellard | { |
136 | 27503323 | bellard | struct dma_regs *r;
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137 | 27503323 | bellard | |
138 | 9eb153f1 | bellard | r = d->regs + ichan; |
139 | 85571bc7 | bellard | r->now[ADDR] = r->base[ADDR] << d->dshift; |
140 | 27503323 | bellard | r->now[COUNT] = 0;
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141 | 27503323 | bellard | } |
142 | 27503323 | bellard | |
143 | 9eb153f1 | bellard | static inline int getff (struct dma_cont *d) |
144 | 27503323 | bellard | { |
145 | 27503323 | bellard | int ff;
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146 | 27503323 | bellard | |
147 | 9eb153f1 | bellard | ff = d->flip_flop; |
148 | 9eb153f1 | bellard | d->flip_flop = !ff; |
149 | 27503323 | bellard | return ff;
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150 | 27503323 | bellard | } |
151 | 27503323 | bellard | |
152 | 7d977de7 | bellard | static uint32_t read_chan (void *opaque, uint32_t nport) |
153 | 27503323 | bellard | { |
154 | 9eb153f1 | bellard | struct dma_cont *d = opaque;
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155 | 85571bc7 | bellard | int ichan, nreg, iport, ff, val, dir;
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156 | 27503323 | bellard | struct dma_regs *r;
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157 | 27503323 | bellard | |
158 | 9eb153f1 | bellard | iport = (nport >> d->dshift) & 0x0f;
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159 | 9eb153f1 | bellard | ichan = iport >> 1;
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160 | 9eb153f1 | bellard | nreg = iport & 1;
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161 | 9eb153f1 | bellard | r = d->regs + ichan; |
162 | 27503323 | bellard | |
163 | 85571bc7 | bellard | dir = ((r->mode >> 5) & 1) ? -1 : 1; |
164 | 9eb153f1 | bellard | ff = getff (d); |
165 | 27503323 | bellard | if (nreg)
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166 | 9eb153f1 | bellard | val = (r->base[COUNT] << d->dshift) - r->now[COUNT]; |
167 | 27503323 | bellard | else
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168 | 85571bc7 | bellard | val = r->now[ADDR] + r->now[COUNT] * dir; |
169 | 27503323 | bellard | |
170 | 85571bc7 | bellard | ldebug ("read_chan %#x -> %d\n", iport, val);
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171 | 9eb153f1 | bellard | return (val >> (d->dshift + (ff << 3))) & 0xff; |
172 | 27503323 | bellard | } |
173 | 27503323 | bellard | |
174 | 7d977de7 | bellard | static void write_chan (void *opaque, uint32_t nport, uint32_t data) |
175 | 27503323 | bellard | { |
176 | 9eb153f1 | bellard | struct dma_cont *d = opaque;
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177 | 9eb153f1 | bellard | int iport, ichan, nreg;
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178 | 27503323 | bellard | struct dma_regs *r;
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179 | 27503323 | bellard | |
180 | 9eb153f1 | bellard | iport = (nport >> d->dshift) & 0x0f;
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181 | 9eb153f1 | bellard | ichan = iport >> 1;
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182 | 9eb153f1 | bellard | nreg = iport & 1;
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183 | 9eb153f1 | bellard | r = d->regs + ichan; |
184 | 9eb153f1 | bellard | if (getff (d)) {
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185 | 3504fe17 | bellard | r->base[nreg] = (r->base[nreg] & 0xff) | ((data << 8) & 0xff00); |
186 | 9eb153f1 | bellard | init_chan (d, ichan); |
187 | 3504fe17 | bellard | } else {
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188 | 3504fe17 | bellard | r->base[nreg] = (r->base[nreg] & 0xff00) | (data & 0xff); |
189 | 27503323 | bellard | } |
190 | 27503323 | bellard | } |
191 | 27503323 | bellard | |
192 | 7d977de7 | bellard | static void write_cont (void *opaque, uint32_t nport, uint32_t data) |
193 | 27503323 | bellard | { |
194 | 9eb153f1 | bellard | struct dma_cont *d = opaque;
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195 | 85571bc7 | bellard | int iport, ichan = 0; |
196 | 27503323 | bellard | |
197 | 9eb153f1 | bellard | iport = (nport >> d->dshift) & 0x0f;
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198 | 27503323 | bellard | switch (iport) {
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199 | 85571bc7 | bellard | case 0x08: /* command */ |
200 | df475d18 | bellard | if ((data != 0) && (data & CMD_NOT_SUPPORTED)) { |
201 | 85571bc7 | bellard | dolog ("command %#x not supported\n", data);
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202 | df475d18 | bellard | return;
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203 | 27503323 | bellard | } |
204 | 27503323 | bellard | d->command = data; |
205 | 27503323 | bellard | break;
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206 | 27503323 | bellard | |
207 | 85571bc7 | bellard | case 0x09: |
208 | 27503323 | bellard | ichan = data & 3;
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209 | 27503323 | bellard | if (data & 4) { |
210 | 27503323 | bellard | d->status |= 1 << (ichan + 4); |
211 | 27503323 | bellard | } |
212 | 27503323 | bellard | else {
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213 | 27503323 | bellard | d->status &= ~(1 << (ichan + 4)); |
214 | 27503323 | bellard | } |
215 | 27503323 | bellard | d->status &= ~(1 << ichan);
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216 | 492c30af | aliguori | DMA_run(); |
217 | 27503323 | bellard | break;
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218 | 27503323 | bellard | |
219 | 85571bc7 | bellard | case 0x0a: /* single mask */ |
220 | 27503323 | bellard | if (data & 4) |
221 | 27503323 | bellard | d->mask |= 1 << (data & 3); |
222 | 27503323 | bellard | else
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223 | 27503323 | bellard | d->mask &= ~(1 << (data & 3)); |
224 | 492c30af | aliguori | DMA_run(); |
225 | 27503323 | bellard | break;
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226 | 27503323 | bellard | |
227 | 85571bc7 | bellard | case 0x0b: /* mode */ |
228 | 27503323 | bellard | { |
229 | 16d17fdb | bellard | ichan = data & 3;
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230 | 16d17fdb | bellard | #ifdef DEBUG_DMA
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231 | 85571bc7 | bellard | { |
232 | 85571bc7 | bellard | int op, ai, dir, opmode;
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233 | e875c40a | bellard | op = (data >> 2) & 3; |
234 | e875c40a | bellard | ai = (data >> 4) & 1; |
235 | e875c40a | bellard | dir = (data >> 5) & 1; |
236 | e875c40a | bellard | opmode = (data >> 6) & 3; |
237 | 27503323 | bellard | |
238 | e875c40a | bellard | linfo ("ichan %d, op %d, ai %d, dir %d, opmode %d\n",
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239 | e875c40a | bellard | ichan, op, ai, dir, opmode); |
240 | 85571bc7 | bellard | } |
241 | 27503323 | bellard | #endif
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242 | 27503323 | bellard | d->regs[ichan].mode = data; |
243 | 27503323 | bellard | break;
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244 | 27503323 | bellard | } |
245 | 27503323 | bellard | |
246 | 85571bc7 | bellard | case 0x0c: /* clear flip flop */ |
247 | 27503323 | bellard | d->flip_flop = 0;
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248 | 27503323 | bellard | break;
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249 | 27503323 | bellard | |
250 | 85571bc7 | bellard | case 0x0d: /* reset */ |
251 | 27503323 | bellard | d->flip_flop = 0;
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252 | 27503323 | bellard | d->mask = ~0;
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253 | 27503323 | bellard | d->status = 0;
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254 | 27503323 | bellard | d->command = 0;
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255 | 27503323 | bellard | break;
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256 | 27503323 | bellard | |
257 | 85571bc7 | bellard | case 0x0e: /* clear mask for all channels */ |
258 | 27503323 | bellard | d->mask = 0;
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259 | 492c30af | aliguori | DMA_run(); |
260 | 27503323 | bellard | break;
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261 | 27503323 | bellard | |
262 | 85571bc7 | bellard | case 0x0f: /* write mask for all channels */ |
263 | 27503323 | bellard | d->mask = data; |
264 | 492c30af | aliguori | DMA_run(); |
265 | 27503323 | bellard | break;
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266 | 27503323 | bellard | |
267 | 27503323 | bellard | default:
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268 | 85571bc7 | bellard | dolog ("unknown iport %#x\n", iport);
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269 | df475d18 | bellard | break;
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270 | 27503323 | bellard | } |
271 | 27503323 | bellard | |
272 | 16d17fdb | bellard | #ifdef DEBUG_DMA
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273 | 27503323 | bellard | if (0xc != iport) { |
274 | 85571bc7 | bellard | linfo ("write_cont: nport %#06x, ichan % 2d, val %#06x\n",
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275 | 9eb153f1 | bellard | nport, ichan, data); |
276 | 27503323 | bellard | } |
277 | 27503323 | bellard | #endif
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278 | 27503323 | bellard | } |
279 | 27503323 | bellard | |
280 | 9eb153f1 | bellard | static uint32_t read_cont (void *opaque, uint32_t nport) |
281 | 9eb153f1 | bellard | { |
282 | 9eb153f1 | bellard | struct dma_cont *d = opaque;
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283 | 9eb153f1 | bellard | int iport, val;
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284 | 85571bc7 | bellard | |
285 | 9eb153f1 | bellard | iport = (nport >> d->dshift) & 0x0f;
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286 | 9eb153f1 | bellard | switch (iport) {
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287 | 85571bc7 | bellard | case 0x08: /* status */ |
288 | 9eb153f1 | bellard | val = d->status; |
289 | 9eb153f1 | bellard | d->status &= 0xf0;
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290 | 9eb153f1 | bellard | break;
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291 | 85571bc7 | bellard | case 0x0f: /* mask */ |
292 | 9eb153f1 | bellard | val = d->mask; |
293 | 9eb153f1 | bellard | break;
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294 | 9eb153f1 | bellard | default:
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295 | 9eb153f1 | bellard | val = 0;
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296 | 9eb153f1 | bellard | break;
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297 | 9eb153f1 | bellard | } |
298 | 85571bc7 | bellard | |
299 | 85571bc7 | bellard | ldebug ("read_cont: nport %#06x, iport %#04x val %#x\n", nport, iport, val);
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300 | 9eb153f1 | bellard | return val;
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301 | 9eb153f1 | bellard | } |
302 | 9eb153f1 | bellard | |
303 | 27503323 | bellard | int DMA_get_channel_mode (int nchan) |
304 | 27503323 | bellard | { |
305 | 27503323 | bellard | return dma_controllers[nchan > 3].regs[nchan & 3].mode; |
306 | 27503323 | bellard | } |
307 | 27503323 | bellard | |
308 | 27503323 | bellard | void DMA_hold_DREQ (int nchan) |
309 | 27503323 | bellard | { |
310 | 27503323 | bellard | int ncont, ichan;
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311 | 27503323 | bellard | |
312 | 27503323 | bellard | ncont = nchan > 3;
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313 | 27503323 | bellard | ichan = nchan & 3;
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314 | 27503323 | bellard | linfo ("held cont=%d chan=%d\n", ncont, ichan);
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315 | 27503323 | bellard | dma_controllers[ncont].status |= 1 << (ichan + 4); |
316 | 492c30af | aliguori | DMA_run(); |
317 | 27503323 | bellard | } |
318 | 27503323 | bellard | |
319 | 27503323 | bellard | void DMA_release_DREQ (int nchan) |
320 | 27503323 | bellard | { |
321 | 27503323 | bellard | int ncont, ichan;
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322 | 27503323 | bellard | |
323 | 27503323 | bellard | ncont = nchan > 3;
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324 | 27503323 | bellard | ichan = nchan & 3;
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325 | 27503323 | bellard | linfo ("released cont=%d chan=%d\n", ncont, ichan);
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326 | 27503323 | bellard | dma_controllers[ncont].status &= ~(1 << (ichan + 4)); |
327 | 492c30af | aliguori | DMA_run(); |
328 | 27503323 | bellard | } |
329 | 27503323 | bellard | |
330 | 27503323 | bellard | static void channel_run (int ncont, int ichan) |
331 | 27503323 | bellard | { |
332 | 27503323 | bellard | int n;
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333 | 85571bc7 | bellard | struct dma_regs *r = &dma_controllers[ncont].regs[ichan];
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334 | 85571bc7 | bellard | #ifdef DEBUG_DMA
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335 | 85571bc7 | bellard | int dir, opmode;
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336 | 27503323 | bellard | |
337 | 85571bc7 | bellard | dir = (r->mode >> 5) & 1; |
338 | 85571bc7 | bellard | opmode = (r->mode >> 6) & 3; |
339 | 27503323 | bellard | |
340 | 85571bc7 | bellard | if (dir) {
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341 | 85571bc7 | bellard | dolog ("DMA in address decrement mode\n");
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342 | 85571bc7 | bellard | } |
343 | 85571bc7 | bellard | if (opmode != 1) { |
344 | 85571bc7 | bellard | dolog ("DMA not in single mode select %#x\n", opmode);
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345 | 85571bc7 | bellard | } |
346 | 85571bc7 | bellard | #endif
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347 | 27503323 | bellard | |
348 | 85571bc7 | bellard | n = r->transfer_handler (r->opaque, ichan + (ncont << 2),
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349 | 85571bc7 | bellard | r->now[COUNT], (r->base[COUNT] + 1) << ncont);
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350 | 85571bc7 | bellard | r->now[COUNT] = n; |
351 | 85571bc7 | bellard | ldebug ("dma_pos %d size %d\n", n, (r->base[COUNT] + 1) << ncont); |
352 | 27503323 | bellard | } |
353 | 27503323 | bellard | |
354 | 492c30af | aliguori | static QEMUBH *dma_bh;
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355 | 492c30af | aliguori | |
356 | 492c30af | aliguori | static void DMA_run (void) |
357 | 27503323 | bellard | { |
358 | 27503323 | bellard | struct dma_cont *d;
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359 | 27503323 | bellard | int icont, ichan;
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360 | 492c30af | aliguori | int rearm = 0; |
361 | 27503323 | bellard | |
362 | 27503323 | bellard | d = dma_controllers; |
363 | 27503323 | bellard | |
364 | 27503323 | bellard | for (icont = 0; icont < 2; icont++, d++) { |
365 | 27503323 | bellard | for (ichan = 0; ichan < 4; ichan++) { |
366 | 27503323 | bellard | int mask;
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367 | 27503323 | bellard | |
368 | 27503323 | bellard | mask = 1 << ichan;
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369 | 27503323 | bellard | |
370 | 492c30af | aliguori | if ((0 == (d->mask & mask)) && (0 != (d->status & (mask << 4)))) { |
371 | 27503323 | bellard | channel_run (icont, ichan); |
372 | 492c30af | aliguori | rearm = 1;
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373 | 492c30af | aliguori | } |
374 | 27503323 | bellard | } |
375 | 27503323 | bellard | } |
376 | 492c30af | aliguori | |
377 | 492c30af | aliguori | if (rearm)
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378 | 492c30af | aliguori | qemu_bh_schedule_idle(dma_bh); |
379 | 492c30af | aliguori | } |
380 | 492c30af | aliguori | |
381 | 492c30af | aliguori | static void DMA_run_bh(void *unused) |
382 | 492c30af | aliguori | { |
383 | 492c30af | aliguori | DMA_run(); |
384 | 27503323 | bellard | } |
385 | 27503323 | bellard | |
386 | 27503323 | bellard | void DMA_register_channel (int nchan, |
387 | 85571bc7 | bellard | DMA_transfer_handler transfer_handler, |
388 | 16f62432 | bellard | void *opaque)
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389 | 27503323 | bellard | { |
390 | 27503323 | bellard | struct dma_regs *r;
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391 | 27503323 | bellard | int ichan, ncont;
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392 | 27503323 | bellard | |
393 | 27503323 | bellard | ncont = nchan > 3;
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394 | 27503323 | bellard | ichan = nchan & 3;
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395 | 27503323 | bellard | |
396 | 27503323 | bellard | r = dma_controllers[ncont].regs + ichan; |
397 | 16f62432 | bellard | r->transfer_handler = transfer_handler; |
398 | 16f62432 | bellard | r->opaque = opaque; |
399 | 16f62432 | bellard | } |
400 | 16f62432 | bellard | |
401 | 85571bc7 | bellard | int DMA_read_memory (int nchan, void *buf, int pos, int len) |
402 | 85571bc7 | bellard | { |
403 | 85571bc7 | bellard | struct dma_regs *r = &dma_controllers[nchan > 3].regs[nchan & 3]; |
404 | c227f099 | Anthony Liguori | target_phys_addr_t addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR]; |
405 | 85571bc7 | bellard | |
406 | 85571bc7 | bellard | if (r->mode & 0x20) { |
407 | 85571bc7 | bellard | int i;
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408 | 85571bc7 | bellard | uint8_t *p = buf; |
409 | 85571bc7 | bellard | |
410 | 85571bc7 | bellard | cpu_physical_memory_read (addr - pos - len, buf, len); |
411 | 85571bc7 | bellard | /* What about 16bit transfers? */
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412 | 85571bc7 | bellard | for (i = 0; i < len >> 1; i++) { |
413 | 85571bc7 | bellard | uint8_t b = p[len - i - 1];
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414 | 85571bc7 | bellard | p[i] = b; |
415 | 85571bc7 | bellard | } |
416 | 85571bc7 | bellard | } |
417 | 85571bc7 | bellard | else
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418 | 85571bc7 | bellard | cpu_physical_memory_read (addr + pos, buf, len); |
419 | 85571bc7 | bellard | |
420 | 85571bc7 | bellard | return len;
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421 | 85571bc7 | bellard | } |
422 | 85571bc7 | bellard | |
423 | 85571bc7 | bellard | int DMA_write_memory (int nchan, void *buf, int pos, int len) |
424 | 85571bc7 | bellard | { |
425 | 85571bc7 | bellard | struct dma_regs *r = &dma_controllers[nchan > 3].regs[nchan & 3]; |
426 | c227f099 | Anthony Liguori | target_phys_addr_t addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR]; |
427 | 85571bc7 | bellard | |
428 | 85571bc7 | bellard | if (r->mode & 0x20) { |
429 | 85571bc7 | bellard | int i;
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430 | 85571bc7 | bellard | uint8_t *p = buf; |
431 | 85571bc7 | bellard | |
432 | 85571bc7 | bellard | cpu_physical_memory_write (addr - pos - len, buf, len); |
433 | 85571bc7 | bellard | /* What about 16bit transfers? */
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434 | 85571bc7 | bellard | for (i = 0; i < len; i++) { |
435 | 85571bc7 | bellard | uint8_t b = p[len - i - 1];
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436 | 85571bc7 | bellard | p[i] = b; |
437 | 85571bc7 | bellard | } |
438 | 85571bc7 | bellard | } |
439 | 85571bc7 | bellard | else
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440 | 85571bc7 | bellard | cpu_physical_memory_write (addr + pos, buf, len); |
441 | 85571bc7 | bellard | |
442 | 85571bc7 | bellard | return len;
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443 | 85571bc7 | bellard | } |
444 | 85571bc7 | bellard | |
445 | 16f62432 | bellard | /* request the emulator to transfer a new DMA memory block ASAP */
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446 | 16f62432 | bellard | void DMA_schedule(int nchan) |
447 | 16f62432 | bellard | { |
448 | 4556bd8b | Blue Swirl | struct dma_cont *d = &dma_controllers[nchan > 3]; |
449 | 4556bd8b | Blue Swirl | |
450 | 4556bd8b | Blue Swirl | qemu_irq_pulse(*d->cpu_request_exit); |
451 | 27503323 | bellard | } |
452 | 27503323 | bellard | |
453 | d7d02e3c | bellard | static void dma_reset(void *opaque) |
454 | d7d02e3c | bellard | { |
455 | d7d02e3c | bellard | struct dma_cont *d = opaque;
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456 | d7d02e3c | bellard | write_cont (d, (0x0d << d->dshift), 0); |
457 | d7d02e3c | bellard | } |
458 | d7d02e3c | bellard | |
459 | ca9cc28c | balrog | static int dma_phony_handler (void *opaque, int nchan, int dma_pos, int dma_len) |
460 | ca9cc28c | balrog | { |
461 | ca9cc28c | balrog | dolog ("unregistered DMA channel used nchan=%d dma_pos=%d dma_len=%d\n",
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462 | ca9cc28c | balrog | nchan, dma_pos, dma_len); |
463 | ca9cc28c | balrog | return dma_pos;
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464 | ca9cc28c | balrog | } |
465 | ca9cc28c | balrog | |
466 | 9eb153f1 | bellard | /* dshift = 0: 8 bit DMA, 1 = 16 bit DMA */
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467 | 85571bc7 | bellard | static void dma_init2(struct dma_cont *d, int base, int dshift, |
468 | 4556bd8b | Blue Swirl | int page_base, int pageh_base, |
469 | 4556bd8b | Blue Swirl | qemu_irq *cpu_request_exit) |
470 | 27503323 | bellard | { |
471 | d70040bc | pbrook | static const int page_port_list[] = { 0x1, 0x2, 0x3, 0x7 }; |
472 | 27503323 | bellard | int i;
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473 | 27503323 | bellard | |
474 | 9eb153f1 | bellard | d->dshift = dshift; |
475 | 4556bd8b | Blue Swirl | d->cpu_request_exit = cpu_request_exit; |
476 | 27503323 | bellard | for (i = 0; i < 8; i++) { |
477 | 9eb153f1 | bellard | register_ioport_write (base + (i << dshift), 1, 1, write_chan, d); |
478 | 9eb153f1 | bellard | register_ioport_read (base + (i << dshift), 1, 1, read_chan, d); |
479 | 27503323 | bellard | } |
480 | b1503cda | malc | for (i = 0; i < ARRAY_SIZE (page_port_list); i++) { |
481 | 85571bc7 | bellard | register_ioport_write (page_base + page_port_list[i], 1, 1, |
482 | 9eb153f1 | bellard | write_page, d); |
483 | 85571bc7 | bellard | register_ioport_read (page_base + page_port_list[i], 1, 1, |
484 | 9eb153f1 | bellard | read_page, d); |
485 | b0bda528 | bellard | if (pageh_base >= 0) { |
486 | 85571bc7 | bellard | register_ioport_write (pageh_base + page_port_list[i], 1, 1, |
487 | b0bda528 | bellard | write_pageh, d); |
488 | 85571bc7 | bellard | register_ioport_read (pageh_base + page_port_list[i], 1, 1, |
489 | b0bda528 | bellard | read_pageh, d); |
490 | b0bda528 | bellard | } |
491 | 27503323 | bellard | } |
492 | 27503323 | bellard | for (i = 0; i < 8; i++) { |
493 | 85571bc7 | bellard | register_ioport_write (base + ((i + 8) << dshift), 1, 1, |
494 | 9eb153f1 | bellard | write_cont, d); |
495 | 85571bc7 | bellard | register_ioport_read (base + ((i + 8) << dshift), 1, 1, |
496 | 9eb153f1 | bellard | read_cont, d); |
497 | 27503323 | bellard | } |
498 | a08d4367 | Jan Kiszka | qemu_register_reset(dma_reset, d); |
499 | d7d02e3c | bellard | dma_reset(d); |
500 | b1503cda | malc | for (i = 0; i < ARRAY_SIZE (d->regs); ++i) { |
501 | ca9cc28c | balrog | d->regs[i].transfer_handler = dma_phony_handler; |
502 | ca9cc28c | balrog | } |
503 | 9eb153f1 | bellard | } |
504 | 27503323 | bellard | |
505 | 7b5045c5 | Juan Quintela | static const VMStateDescription vmstate_dma_regs = { |
506 | 7b5045c5 | Juan Quintela | .name = "dma_regs",
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507 | 7b5045c5 | Juan Quintela | .version_id = 1,
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508 | 7b5045c5 | Juan Quintela | .minimum_version_id = 1,
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509 | 7b5045c5 | Juan Quintela | .minimum_version_id_old = 1,
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510 | 7b5045c5 | Juan Quintela | .fields = (VMStateField []) { |
511 | 7b5045c5 | Juan Quintela | VMSTATE_INT32_ARRAY(now, struct dma_regs, 2), |
512 | 7b5045c5 | Juan Quintela | VMSTATE_UINT16_ARRAY(base, struct dma_regs, 2), |
513 | 7b5045c5 | Juan Quintela | VMSTATE_UINT8(mode, struct dma_regs),
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514 | 7b5045c5 | Juan Quintela | VMSTATE_UINT8(page, struct dma_regs),
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515 | 7b5045c5 | Juan Quintela | VMSTATE_UINT8(pageh, struct dma_regs),
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516 | 7b5045c5 | Juan Quintela | VMSTATE_UINT8(dack, struct dma_regs),
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517 | 7b5045c5 | Juan Quintela | VMSTATE_UINT8(eop, struct dma_regs),
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518 | 7b5045c5 | Juan Quintela | VMSTATE_END_OF_LIST() |
519 | 85571bc7 | bellard | } |
520 | 7b5045c5 | Juan Quintela | }; |
521 | 85571bc7 | bellard | |
522 | e59fb374 | Juan Quintela | static int dma_post_load(void *opaque, int version_id) |
523 | 85571bc7 | bellard | { |
524 | 492c30af | aliguori | DMA_run(); |
525 | 492c30af | aliguori | |
526 | 85571bc7 | bellard | return 0; |
527 | 85571bc7 | bellard | } |
528 | 85571bc7 | bellard | |
529 | 7b5045c5 | Juan Quintela | static const VMStateDescription vmstate_dma = { |
530 | 7b5045c5 | Juan Quintela | .name = "dma",
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531 | 7b5045c5 | Juan Quintela | .version_id = 1,
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532 | 7b5045c5 | Juan Quintela | .minimum_version_id = 1,
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533 | 7b5045c5 | Juan Quintela | .minimum_version_id_old = 1,
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534 | 7b5045c5 | Juan Quintela | .post_load = dma_post_load, |
535 | 7b5045c5 | Juan Quintela | .fields = (VMStateField []) { |
536 | 7b5045c5 | Juan Quintela | VMSTATE_UINT8(command, struct dma_cont),
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537 | 7b5045c5 | Juan Quintela | VMSTATE_UINT8(mask, struct dma_cont),
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538 | 7b5045c5 | Juan Quintela | VMSTATE_UINT8(flip_flop, struct dma_cont),
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539 | 7b5045c5 | Juan Quintela | VMSTATE_INT32(dshift, struct dma_cont),
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540 | 7b5045c5 | Juan Quintela | VMSTATE_STRUCT_ARRAY(regs, struct dma_cont, 4, 1, vmstate_dma_regs, struct dma_regs), |
541 | 7b5045c5 | Juan Quintela | VMSTATE_END_OF_LIST() |
542 | 7b5045c5 | Juan Quintela | } |
543 | 7b5045c5 | Juan Quintela | }; |
544 | 7b5045c5 | Juan Quintela | |
545 | 4556bd8b | Blue Swirl | void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit) |
546 | 9eb153f1 | bellard | { |
547 | 85571bc7 | bellard | dma_init2(&dma_controllers[0], 0x00, 0, 0x80, |
548 | 4556bd8b | Blue Swirl | high_page_enable ? 0x480 : -1, cpu_request_exit); |
549 | b0bda528 | bellard | dma_init2(&dma_controllers[1], 0xc0, 1, 0x88, |
550 | 4556bd8b | Blue Swirl | high_page_enable ? 0x488 : -1, cpu_request_exit); |
551 | 7b5045c5 | Juan Quintela | vmstate_register (0, &vmstate_dma, &dma_controllers[0]); |
552 | 7b5045c5 | Juan Quintela | vmstate_register (1, &vmstate_dma, &dma_controllers[1]); |
553 | 492c30af | aliguori | |
554 | 492c30af | aliguori | dma_bh = qemu_bh_new(DMA_run_bh, NULL);
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555 | 27503323 | bellard | } |