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1 | c3d2689d | balrog | /*
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2 | c3d2689d | balrog | * Texas Instruments OMAP processors.
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3 | c3d2689d | balrog | *
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4 | b4e3104b | balrog | * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
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5 | c3d2689d | balrog | *
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6 | c3d2689d | balrog | * This program is free software; you can redistribute it and/or
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7 | c3d2689d | balrog | * modify it under the terms of the GNU General Public License as
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8 | 827df9f3 | balrog | * published by the Free Software Foundation; either version 2 or
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9 | 827df9f3 | balrog | * (at your option) version 3 of the License.
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10 | c3d2689d | balrog | *
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11 | c3d2689d | balrog | * This program is distributed in the hope that it will be useful,
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12 | c3d2689d | balrog | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | c3d2689d | balrog | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 | c3d2689d | balrog | * GNU General Public License for more details.
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15 | c3d2689d | balrog | *
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16 | fad6cb1a | aurel32 | * You should have received a copy of the GNU General Public License along
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17 | 8167ee88 | Blue Swirl | * with this program; if not, see <http://www.gnu.org/licenses/>.
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18 | c3d2689d | balrog | */
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19 | c3d2689d | balrog | #ifndef hw_omap_h
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20 | c3d2689d | balrog | # define hw_omap_h "omap.h" |
21 | c3d2689d | balrog | |
22 | c3d2689d | balrog | # define OMAP_EMIFS_BASE 0x00000000 |
23 | 827df9f3 | balrog | # define OMAP2_Q0_BASE 0x00000000 |
24 | c3d2689d | balrog | # define OMAP_CS0_BASE 0x00000000 |
25 | c3d2689d | balrog | # define OMAP_CS1_BASE 0x04000000 |
26 | c3d2689d | balrog | # define OMAP_CS2_BASE 0x08000000 |
27 | c3d2689d | balrog | # define OMAP_CS3_BASE 0x0c000000 |
28 | c3d2689d | balrog | # define OMAP_EMIFF_BASE 0x10000000 |
29 | c3d2689d | balrog | # define OMAP_IMIF_BASE 0x20000000 |
30 | c3d2689d | balrog | # define OMAP_LOCALBUS_BASE 0x30000000 |
31 | 827df9f3 | balrog | # define OMAP2_Q1_BASE 0x40000000 |
32 | 827df9f3 | balrog | # define OMAP2_L4_BASE 0x48000000 |
33 | 827df9f3 | balrog | # define OMAP2_SRAM_BASE 0x40200000 |
34 | 827df9f3 | balrog | # define OMAP2_L3_BASE 0x68000000 |
35 | 827df9f3 | balrog | # define OMAP2_Q2_BASE 0x80000000 |
36 | 827df9f3 | balrog | # define OMAP2_Q3_BASE 0xc0000000 |
37 | c3d2689d | balrog | # define OMAP_MPUI_BASE 0xe1000000 |
38 | c3d2689d | balrog | |
39 | c3d2689d | balrog | # define OMAP730_SRAM_SIZE 0x00032000 |
40 | c3d2689d | balrog | # define OMAP15XX_SRAM_SIZE 0x00030000 |
41 | c3d2689d | balrog | # define OMAP16XX_SRAM_SIZE 0x00004000 |
42 | c3d2689d | balrog | # define OMAP1611_SRAM_SIZE 0x0003e800 |
43 | 827df9f3 | balrog | # define OMAP242X_SRAM_SIZE 0x000a0000 |
44 | 827df9f3 | balrog | # define OMAP243X_SRAM_SIZE 0x00010000 |
45 | c3d2689d | balrog | # define OMAP_CS0_SIZE 0x04000000 |
46 | c3d2689d | balrog | # define OMAP_CS1_SIZE 0x04000000 |
47 | c3d2689d | balrog | # define OMAP_CS2_SIZE 0x04000000 |
48 | c3d2689d | balrog | # define OMAP_CS3_SIZE 0x04000000 |
49 | c3d2689d | balrog | |
50 | 827df9f3 | balrog | /* omap_clk.c */
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51 | c3d2689d | balrog | struct omap_mpu_state_s;
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52 | c3d2689d | balrog | typedef struct clk *omap_clk; |
53 | c3d2689d | balrog | omap_clk omap_findclk(struct omap_mpu_state_s *mpu, const char *name); |
54 | c3d2689d | balrog | void omap_clk_init(struct omap_mpu_state_s *mpu); |
55 | c3d2689d | balrog | void omap_clk_adduser(struct clk *clk, qemu_irq user); |
56 | c3d2689d | balrog | void omap_clk_get(omap_clk clk);
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57 | c3d2689d | balrog | void omap_clk_put(omap_clk clk);
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58 | c3d2689d | balrog | void omap_clk_onoff(omap_clk clk, int on); |
59 | c3d2689d | balrog | void omap_clk_canidle(omap_clk clk, int can); |
60 | c3d2689d | balrog | void omap_clk_setrate(omap_clk clk, int divide, int multiply); |
61 | c3d2689d | balrog | int64_t omap_clk_getrate(omap_clk clk); |
62 | c3d2689d | balrog | void omap_clk_reparent(omap_clk clk, omap_clk parent);
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63 | c3d2689d | balrog | |
64 | b4e3104b | balrog | /* omap[123].c */
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65 | 827df9f3 | balrog | struct omap_l4_s;
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66 | c227f099 | Anthony Liguori | struct omap_l4_s *omap_l4_init(target_phys_addr_t base, int ta_num); |
67 | 827df9f3 | balrog | |
68 | 827df9f3 | balrog | struct omap_target_agent_s;
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69 | 827df9f3 | balrog | struct omap_target_agent_s *omap_l4ta_get(struct omap_l4_s *bus, int cs); |
70 | c227f099 | Anthony Liguori | target_phys_addr_t omap_l4_attach(struct omap_target_agent_s *ta, int region, |
71 | 827df9f3 | balrog | int iotype);
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72 | c66fb5bc | balrog | # define l4_register_io_memory cpu_register_io_memory
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73 | 827df9f3 | balrog | |
74 | 7f132a21 | cmchao | /* OMAP interrupt controller */
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75 | c3d2689d | balrog | struct omap_intr_handler_s;
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76 | c227f099 | Anthony Liguori | struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base,
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77 | 827df9f3 | balrog | unsigned long size, unsigned char nbanks, qemu_irq **pins, |
78 | 106627d0 | balrog | qemu_irq parent_irq, qemu_irq parent_fiq, omap_clk clk); |
79 | c227f099 | Anthony Liguori | struct omap_intr_handler_s *omap2_inth_init(target_phys_addr_t base,
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80 | 827df9f3 | balrog | int size, int nbanks, qemu_irq **pins, |
81 | 827df9f3 | balrog | qemu_irq parent_irq, qemu_irq parent_fiq, |
82 | 827df9f3 | balrog | omap_clk fclk, omap_clk iclk); |
83 | 827df9f3 | balrog | void omap_inth_reset(struct omap_intr_handler_s *s); |
84 | 7f132a21 | cmchao | qemu_irq omap_inth_get_pin(struct omap_intr_handler_s *s, int n); |
85 | 827df9f3 | balrog | |
86 | 827df9f3 | balrog | struct omap_prcm_s;
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87 | 827df9f3 | balrog | struct omap_prcm_s *omap_prcm_init(struct omap_target_agent_s *ta, |
88 | 827df9f3 | balrog | qemu_irq mpu_int, qemu_irq dsp_int, qemu_irq iva_int, |
89 | 827df9f3 | balrog | struct omap_mpu_state_s *mpu);
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90 | 827df9f3 | balrog | |
91 | 827df9f3 | balrog | struct omap_sysctl_s;
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92 | 827df9f3 | balrog | struct omap_sysctl_s *omap_sysctl_init(struct omap_target_agent_s *ta, |
93 | 827df9f3 | balrog | omap_clk iclk, struct omap_mpu_state_s *mpu);
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94 | 827df9f3 | balrog | |
95 | 0bf43016 | cmchao | /* OMAP2 SDRAM controller */
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96 | 827df9f3 | balrog | struct omap_sdrc_s;
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97 | c227f099 | Anthony Liguori | struct omap_sdrc_s *omap_sdrc_init(target_phys_addr_t base);
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98 | 0bf43016 | cmchao | void omap_sdrc_reset(struct omap_sdrc_s *s); |
99 | 827df9f3 | balrog | |
100 | f3354b0e | cmchao | /* OMAP2 general purpose memory controller */
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101 | 827df9f3 | balrog | struct omap_gpmc_s;
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102 | c227f099 | Anthony Liguori | struct omap_gpmc_s *omap_gpmc_init(target_phys_addr_t base, qemu_irq irq);
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103 | f3354b0e | cmchao | void omap_gpmc_reset(struct omap_gpmc_s *s); |
104 | 827df9f3 | balrog | void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, int iomemtype, |
105 | c227f099 | Anthony Liguori | void (*base_upd)(void *opaque, target_phys_addr_t new), |
106 | 827df9f3 | balrog | void (*unmap)(void *opaque), void *opaque); |
107 | 29885477 | balrog | |
108 | c3d2689d | balrog | /*
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109 | c3d2689d | balrog | * Common IRQ numbers for level 1 interrupt handler
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110 | c3d2689d | balrog | * See /usr/include/asm-arm/arch-omap/irqs.h in Linux.
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111 | c3d2689d | balrog | */
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112 | c3d2689d | balrog | # define OMAP_INT_CAMERA 1 |
113 | c3d2689d | balrog | # define OMAP_INT_FIQ 3 |
114 | c3d2689d | balrog | # define OMAP_INT_RTDX 6 |
115 | c3d2689d | balrog | # define OMAP_INT_DSP_MMU_ABORT 7 |
116 | c3d2689d | balrog | # define OMAP_INT_HOST 8 |
117 | c3d2689d | balrog | # define OMAP_INT_ABORT 9 |
118 | c3d2689d | balrog | # define OMAP_INT_BRIDGE_PRIV 13 |
119 | c3d2689d | balrog | # define OMAP_INT_GPIO_BANK1 14 |
120 | c3d2689d | balrog | # define OMAP_INT_UART3 15 |
121 | c3d2689d | balrog | # define OMAP_INT_TIMER3 16 |
122 | c3d2689d | balrog | # define OMAP_INT_DMA_CH0_6 19 |
123 | c3d2689d | balrog | # define OMAP_INT_DMA_CH1_7 20 |
124 | c3d2689d | balrog | # define OMAP_INT_DMA_CH2_8 21 |
125 | c3d2689d | balrog | # define OMAP_INT_DMA_CH3 22 |
126 | c3d2689d | balrog | # define OMAP_INT_DMA_CH4 23 |
127 | c3d2689d | balrog | # define OMAP_INT_DMA_CH5 24 |
128 | c3d2689d | balrog | # define OMAP_INT_DMA_LCD 25 |
129 | c3d2689d | balrog | # define OMAP_INT_TIMER1 26 |
130 | c3d2689d | balrog | # define OMAP_INT_WD_TIMER 27 |
131 | c3d2689d | balrog | # define OMAP_INT_BRIDGE_PUB 28 |
132 | c3d2689d | balrog | # define OMAP_INT_TIMER2 30 |
133 | c3d2689d | balrog | # define OMAP_INT_LCD_CTRL 31 |
134 | c3d2689d | balrog | |
135 | c3d2689d | balrog | /*
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136 | c3d2689d | balrog | * Common OMAP-15xx IRQ numbers for level 1 interrupt handler
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137 | c3d2689d | balrog | */
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138 | c3d2689d | balrog | # define OMAP_INT_15XX_IH2_IRQ 0 |
139 | c3d2689d | balrog | # define OMAP_INT_15XX_LB_MMU 17 |
140 | c3d2689d | balrog | # define OMAP_INT_15XX_LOCAL_BUS 29 |
141 | c3d2689d | balrog | |
142 | c3d2689d | balrog | /*
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143 | c3d2689d | balrog | * OMAP-1510 specific IRQ numbers for level 1 interrupt handler
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144 | c3d2689d | balrog | */
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145 | c3d2689d | balrog | # define OMAP_INT_1510_SPI_TX 4 |
146 | c3d2689d | balrog | # define OMAP_INT_1510_SPI_RX 5 |
147 | c3d2689d | balrog | # define OMAP_INT_1510_DSP_MAILBOX1 10 |
148 | c3d2689d | balrog | # define OMAP_INT_1510_DSP_MAILBOX2 11 |
149 | c3d2689d | balrog | |
150 | c3d2689d | balrog | /*
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151 | c3d2689d | balrog | * OMAP-310 specific IRQ numbers for level 1 interrupt handler
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152 | c3d2689d | balrog | */
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153 | c3d2689d | balrog | # define OMAP_INT_310_McBSP2_TX 4 |
154 | c3d2689d | balrog | # define OMAP_INT_310_McBSP2_RX 5 |
155 | c3d2689d | balrog | # define OMAP_INT_310_HSB_MAILBOX1 12 |
156 | c3d2689d | balrog | # define OMAP_INT_310_HSAB_MMU 18 |
157 | c3d2689d | balrog | |
158 | c3d2689d | balrog | /*
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159 | c3d2689d | balrog | * OMAP-1610 specific IRQ numbers for level 1 interrupt handler
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160 | c3d2689d | balrog | */
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161 | c3d2689d | balrog | # define OMAP_INT_1610_IH2_IRQ 0 |
162 | c3d2689d | balrog | # define OMAP_INT_1610_IH2_FIQ 2 |
163 | c3d2689d | balrog | # define OMAP_INT_1610_McBSP2_TX 4 |
164 | c3d2689d | balrog | # define OMAP_INT_1610_McBSP2_RX 5 |
165 | c3d2689d | balrog | # define OMAP_INT_1610_DSP_MAILBOX1 10 |
166 | c3d2689d | balrog | # define OMAP_INT_1610_DSP_MAILBOX2 11 |
167 | c3d2689d | balrog | # define OMAP_INT_1610_LCD_LINE 12 |
168 | c3d2689d | balrog | # define OMAP_INT_1610_GPTIMER1 17 |
169 | c3d2689d | balrog | # define OMAP_INT_1610_GPTIMER2 18 |
170 | c3d2689d | balrog | # define OMAP_INT_1610_SSR_FIFO_0 29 |
171 | c3d2689d | balrog | |
172 | c3d2689d | balrog | /*
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173 | c3d2689d | balrog | * OMAP-730 specific IRQ numbers for level 1 interrupt handler
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174 | c3d2689d | balrog | */
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175 | c3d2689d | balrog | # define OMAP_INT_730_IH2_FIQ 0 |
176 | c3d2689d | balrog | # define OMAP_INT_730_IH2_IRQ 1 |
177 | c3d2689d | balrog | # define OMAP_INT_730_USB_NON_ISO 2 |
178 | c3d2689d | balrog | # define OMAP_INT_730_USB_ISO 3 |
179 | c3d2689d | balrog | # define OMAP_INT_730_ICR 4 |
180 | c3d2689d | balrog | # define OMAP_INT_730_EAC 5 |
181 | c3d2689d | balrog | # define OMAP_INT_730_GPIO_BANK1 6 |
182 | c3d2689d | balrog | # define OMAP_INT_730_GPIO_BANK2 7 |
183 | c3d2689d | balrog | # define OMAP_INT_730_GPIO_BANK3 8 |
184 | c3d2689d | balrog | # define OMAP_INT_730_McBSP2TX 10 |
185 | c3d2689d | balrog | # define OMAP_INT_730_McBSP2RX 11 |
186 | c3d2689d | balrog | # define OMAP_INT_730_McBSP2RX_OVF 12 |
187 | c3d2689d | balrog | # define OMAP_INT_730_LCD_LINE 14 |
188 | c3d2689d | balrog | # define OMAP_INT_730_GSM_PROTECT 15 |
189 | c3d2689d | balrog | # define OMAP_INT_730_TIMER3 16 |
190 | c3d2689d | balrog | # define OMAP_INT_730_GPIO_BANK5 17 |
191 | c3d2689d | balrog | # define OMAP_INT_730_GPIO_BANK6 18 |
192 | c3d2689d | balrog | # define OMAP_INT_730_SPGIO_WR 29 |
193 | c3d2689d | balrog | |
194 | c3d2689d | balrog | /*
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195 | c3d2689d | balrog | * Common IRQ numbers for level 2 interrupt handler
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196 | c3d2689d | balrog | */
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197 | c3d2689d | balrog | # define OMAP_INT_KEYBOARD 1 |
198 | c3d2689d | balrog | # define OMAP_INT_uWireTX 2 |
199 | c3d2689d | balrog | # define OMAP_INT_uWireRX 3 |
200 | c3d2689d | balrog | # define OMAP_INT_I2C 4 |
201 | c3d2689d | balrog | # define OMAP_INT_MPUIO 5 |
202 | c3d2689d | balrog | # define OMAP_INT_USB_HHC_1 6 |
203 | c3d2689d | balrog | # define OMAP_INT_McBSP3TX 10 |
204 | c3d2689d | balrog | # define OMAP_INT_McBSP3RX 11 |
205 | c3d2689d | balrog | # define OMAP_INT_McBSP1TX 12 |
206 | c3d2689d | balrog | # define OMAP_INT_McBSP1RX 13 |
207 | c3d2689d | balrog | # define OMAP_INT_UART1 14 |
208 | c3d2689d | balrog | # define OMAP_INT_UART2 15 |
209 | c3d2689d | balrog | # define OMAP_INT_USB_W2FC 20 |
210 | c3d2689d | balrog | # define OMAP_INT_1WIRE 21 |
211 | c3d2689d | balrog | # define OMAP_INT_OS_TIMER 22 |
212 | b30bb3a2 | balrog | # define OMAP_INT_OQN 23 |
213 | c3d2689d | balrog | # define OMAP_INT_GAUGE_32K 24 |
214 | c3d2689d | balrog | # define OMAP_INT_RTC_TIMER 25 |
215 | c3d2689d | balrog | # define OMAP_INT_RTC_ALARM 26 |
216 | c3d2689d | balrog | # define OMAP_INT_DSP_MMU 28 |
217 | c3d2689d | balrog | |
218 | c3d2689d | balrog | /*
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219 | c3d2689d | balrog | * OMAP-1510 specific IRQ numbers for level 2 interrupt handler
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220 | c3d2689d | balrog | */
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221 | c3d2689d | balrog | # define OMAP_INT_1510_BT_MCSI1TX 16 |
222 | c3d2689d | balrog | # define OMAP_INT_1510_BT_MCSI1RX 17 |
223 | c3d2689d | balrog | # define OMAP_INT_1510_SoSSI_MATCH 19 |
224 | c3d2689d | balrog | # define OMAP_INT_1510_MEM_STICK 27 |
225 | c3d2689d | balrog | # define OMAP_INT_1510_COM_SPI_RO 31 |
226 | c3d2689d | balrog | |
227 | c3d2689d | balrog | /*
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228 | c3d2689d | balrog | * OMAP-310 specific IRQ numbers for level 2 interrupt handler
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229 | c3d2689d | balrog | */
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230 | c3d2689d | balrog | # define OMAP_INT_310_FAC 0 |
231 | c3d2689d | balrog | # define OMAP_INT_310_USB_HHC_2 7 |
232 | c3d2689d | balrog | # define OMAP_INT_310_MCSI1_FE 16 |
233 | c3d2689d | balrog | # define OMAP_INT_310_MCSI2_FE 17 |
234 | c3d2689d | balrog | # define OMAP_INT_310_USB_W2FC_ISO 29 |
235 | c3d2689d | balrog | # define OMAP_INT_310_USB_W2FC_NON_ISO 30 |
236 | c3d2689d | balrog | # define OMAP_INT_310_McBSP2RX_OF 31 |
237 | c3d2689d | balrog | |
238 | c3d2689d | balrog | /*
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239 | c3d2689d | balrog | * OMAP-1610 specific IRQ numbers for level 2 interrupt handler
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240 | c3d2689d | balrog | */
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241 | c3d2689d | balrog | # define OMAP_INT_1610_FAC 0 |
242 | c3d2689d | balrog | # define OMAP_INT_1610_USB_HHC_2 7 |
243 | c3d2689d | balrog | # define OMAP_INT_1610_USB_OTG 8 |
244 | c3d2689d | balrog | # define OMAP_INT_1610_SoSSI 9 |
245 | c3d2689d | balrog | # define OMAP_INT_1610_BT_MCSI1TX 16 |
246 | c3d2689d | balrog | # define OMAP_INT_1610_BT_MCSI1RX 17 |
247 | c3d2689d | balrog | # define OMAP_INT_1610_SoSSI_MATCH 19 |
248 | c3d2689d | balrog | # define OMAP_INT_1610_MEM_STICK 27 |
249 | c3d2689d | balrog | # define OMAP_INT_1610_McBSP2RX_OF 31 |
250 | c3d2689d | balrog | # define OMAP_INT_1610_STI 32 |
251 | c3d2689d | balrog | # define OMAP_INT_1610_STI_WAKEUP 33 |
252 | c3d2689d | balrog | # define OMAP_INT_1610_GPTIMER3 34 |
253 | c3d2689d | balrog | # define OMAP_INT_1610_GPTIMER4 35 |
254 | c3d2689d | balrog | # define OMAP_INT_1610_GPTIMER5 36 |
255 | c3d2689d | balrog | # define OMAP_INT_1610_GPTIMER6 37 |
256 | c3d2689d | balrog | # define OMAP_INT_1610_GPTIMER7 38 |
257 | c3d2689d | balrog | # define OMAP_INT_1610_GPTIMER8 39 |
258 | c3d2689d | balrog | # define OMAP_INT_1610_GPIO_BANK2 40 |
259 | c3d2689d | balrog | # define OMAP_INT_1610_GPIO_BANK3 41 |
260 | c3d2689d | balrog | # define OMAP_INT_1610_MMC2 42 |
261 | c3d2689d | balrog | # define OMAP_INT_1610_CF 43 |
262 | c3d2689d | balrog | # define OMAP_INT_1610_WAKE_UP_REQ 46 |
263 | c3d2689d | balrog | # define OMAP_INT_1610_GPIO_BANK4 48 |
264 | c3d2689d | balrog | # define OMAP_INT_1610_SPI 49 |
265 | c3d2689d | balrog | # define OMAP_INT_1610_DMA_CH6 53 |
266 | c3d2689d | balrog | # define OMAP_INT_1610_DMA_CH7 54 |
267 | c3d2689d | balrog | # define OMAP_INT_1610_DMA_CH8 55 |
268 | c3d2689d | balrog | # define OMAP_INT_1610_DMA_CH9 56 |
269 | c3d2689d | balrog | # define OMAP_INT_1610_DMA_CH10 57 |
270 | c3d2689d | balrog | # define OMAP_INT_1610_DMA_CH11 58 |
271 | c3d2689d | balrog | # define OMAP_INT_1610_DMA_CH12 59 |
272 | c3d2689d | balrog | # define OMAP_INT_1610_DMA_CH13 60 |
273 | c3d2689d | balrog | # define OMAP_INT_1610_DMA_CH14 61 |
274 | c3d2689d | balrog | # define OMAP_INT_1610_DMA_CH15 62 |
275 | c3d2689d | balrog | # define OMAP_INT_1610_NAND 63 |
276 | c3d2689d | balrog | |
277 | c3d2689d | balrog | /*
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278 | c3d2689d | balrog | * OMAP-730 specific IRQ numbers for level 2 interrupt handler
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279 | c3d2689d | balrog | */
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280 | c3d2689d | balrog | # define OMAP_INT_730_HW_ERRORS 0 |
281 | c3d2689d | balrog | # define OMAP_INT_730_NFIQ_PWR_FAIL 1 |
282 | c3d2689d | balrog | # define OMAP_INT_730_CFCD 2 |
283 | c3d2689d | balrog | # define OMAP_INT_730_CFIREQ 3 |
284 | c3d2689d | balrog | # define OMAP_INT_730_I2C 4 |
285 | c3d2689d | balrog | # define OMAP_INT_730_PCC 5 |
286 | c3d2689d | balrog | # define OMAP_INT_730_MPU_EXT_NIRQ 6 |
287 | c3d2689d | balrog | # define OMAP_INT_730_SPI_100K_1 7 |
288 | c3d2689d | balrog | # define OMAP_INT_730_SYREN_SPI 8 |
289 | c3d2689d | balrog | # define OMAP_INT_730_VLYNQ 9 |
290 | c3d2689d | balrog | # define OMAP_INT_730_GPIO_BANK4 10 |
291 | c3d2689d | balrog | # define OMAP_INT_730_McBSP1TX 11 |
292 | c3d2689d | balrog | # define OMAP_INT_730_McBSP1RX 12 |
293 | c3d2689d | balrog | # define OMAP_INT_730_McBSP1RX_OF 13 |
294 | c3d2689d | balrog | # define OMAP_INT_730_UART_MODEM_IRDA_2 14 |
295 | c3d2689d | balrog | # define OMAP_INT_730_UART_MODEM_1 15 |
296 | c3d2689d | balrog | # define OMAP_INT_730_MCSI 16 |
297 | c3d2689d | balrog | # define OMAP_INT_730_uWireTX 17 |
298 | c3d2689d | balrog | # define OMAP_INT_730_uWireRX 18 |
299 | c3d2689d | balrog | # define OMAP_INT_730_SMC_CD 19 |
300 | c3d2689d | balrog | # define OMAP_INT_730_SMC_IREQ 20 |
301 | c3d2689d | balrog | # define OMAP_INT_730_HDQ_1WIRE 21 |
302 | c3d2689d | balrog | # define OMAP_INT_730_TIMER32K 22 |
303 | c3d2689d | balrog | # define OMAP_INT_730_MMC_SDIO 23 |
304 | c3d2689d | balrog | # define OMAP_INT_730_UPLD 24 |
305 | c3d2689d | balrog | # define OMAP_INT_730_USB_HHC_1 27 |
306 | c3d2689d | balrog | # define OMAP_INT_730_USB_HHC_2 28 |
307 | c3d2689d | balrog | # define OMAP_INT_730_USB_GENI 29 |
308 | c3d2689d | balrog | # define OMAP_INT_730_USB_OTG 30 |
309 | c3d2689d | balrog | # define OMAP_INT_730_CAMERA_IF 31 |
310 | c3d2689d | balrog | # define OMAP_INT_730_RNG 32 |
311 | c3d2689d | balrog | # define OMAP_INT_730_DUAL_MODE_TIMER 33 |
312 | c3d2689d | balrog | # define OMAP_INT_730_DBB_RF_EN 34 |
313 | c3d2689d | balrog | # define OMAP_INT_730_MPUIO_KEYPAD 35 |
314 | c3d2689d | balrog | # define OMAP_INT_730_SHA1_MD5 36 |
315 | c3d2689d | balrog | # define OMAP_INT_730_SPI_100K_2 37 |
316 | c3d2689d | balrog | # define OMAP_INT_730_RNG_IDLE 38 |
317 | c3d2689d | balrog | # define OMAP_INT_730_MPUIO 39 |
318 | c3d2689d | balrog | # define OMAP_INT_730_LLPC_LCD_CTRL_OFF 40 |
319 | c3d2689d | balrog | # define OMAP_INT_730_LLPC_OE_FALLING 41 |
320 | c3d2689d | balrog | # define OMAP_INT_730_LLPC_OE_RISING 42 |
321 | c3d2689d | balrog | # define OMAP_INT_730_LLPC_VSYNC 43 |
322 | c3d2689d | balrog | # define OMAP_INT_730_WAKE_UP_REQ 46 |
323 | c3d2689d | balrog | # define OMAP_INT_730_DMA_CH6 53 |
324 | c3d2689d | balrog | # define OMAP_INT_730_DMA_CH7 54 |
325 | c3d2689d | balrog | # define OMAP_INT_730_DMA_CH8 55 |
326 | c3d2689d | balrog | # define OMAP_INT_730_DMA_CH9 56 |
327 | c3d2689d | balrog | # define OMAP_INT_730_DMA_CH10 57 |
328 | c3d2689d | balrog | # define OMAP_INT_730_DMA_CH11 58 |
329 | c3d2689d | balrog | # define OMAP_INT_730_DMA_CH12 59 |
330 | c3d2689d | balrog | # define OMAP_INT_730_DMA_CH13 60 |
331 | c3d2689d | balrog | # define OMAP_INT_730_DMA_CH14 61 |
332 | c3d2689d | balrog | # define OMAP_INT_730_DMA_CH15 62 |
333 | c3d2689d | balrog | # define OMAP_INT_730_NAND 63 |
334 | c3d2689d | balrog | |
335 | c3d2689d | balrog | /*
|
336 | c3d2689d | balrog | * OMAP-24xx common IRQ numbers
|
337 | c3d2689d | balrog | */
|
338 | 54585ffe | balrog | # define OMAP_INT_24XX_STI 4 |
339 | c3d2689d | balrog | # define OMAP_INT_24XX_SYS_NIRQ 7 |
340 | 827df9f3 | balrog | # define OMAP_INT_24XX_L3_IRQ 10 |
341 | 827df9f3 | balrog | # define OMAP_INT_24XX_PRCM_MPU_IRQ 11 |
342 | c3d2689d | balrog | # define OMAP_INT_24XX_SDMA_IRQ0 12 |
343 | c3d2689d | balrog | # define OMAP_INT_24XX_SDMA_IRQ1 13 |
344 | c3d2689d | balrog | # define OMAP_INT_24XX_SDMA_IRQ2 14 |
345 | c3d2689d | balrog | # define OMAP_INT_24XX_SDMA_IRQ3 15 |
346 | 827df9f3 | balrog | # define OMAP_INT_243X_MCBSP2_IRQ 16 |
347 | 827df9f3 | balrog | # define OMAP_INT_243X_MCBSP3_IRQ 17 |
348 | 827df9f3 | balrog | # define OMAP_INT_243X_MCBSP4_IRQ 18 |
349 | 827df9f3 | balrog | # define OMAP_INT_243X_MCBSP5_IRQ 19 |
350 | 827df9f3 | balrog | # define OMAP_INT_24XX_GPMC_IRQ 20 |
351 | 827df9f3 | balrog | # define OMAP_INT_24XX_GUFFAW_IRQ 21 |
352 | 827df9f3 | balrog | # define OMAP_INT_24XX_IVA_IRQ 22 |
353 | 827df9f3 | balrog | # define OMAP_INT_24XX_EAC_IRQ 23 |
354 | c3d2689d | balrog | # define OMAP_INT_24XX_CAM_IRQ 24 |
355 | c3d2689d | balrog | # define OMAP_INT_24XX_DSS_IRQ 25 |
356 | c3d2689d | balrog | # define OMAP_INT_24XX_MAIL_U0_MPU 26 |
357 | c3d2689d | balrog | # define OMAP_INT_24XX_DSP_UMA 27 |
358 | c3d2689d | balrog | # define OMAP_INT_24XX_DSP_MMU 28 |
359 | c3d2689d | balrog | # define OMAP_INT_24XX_GPIO_BANK1 29 |
360 | c3d2689d | balrog | # define OMAP_INT_24XX_GPIO_BANK2 30 |
361 | c3d2689d | balrog | # define OMAP_INT_24XX_GPIO_BANK3 31 |
362 | c3d2689d | balrog | # define OMAP_INT_24XX_GPIO_BANK4 32 |
363 | 827df9f3 | balrog | # define OMAP_INT_243X_GPIO_BANK5 33 |
364 | c3d2689d | balrog | # define OMAP_INT_24XX_MAIL_U3_MPU 34 |
365 | 827df9f3 | balrog | # define OMAP_INT_24XX_WDT3 35 |
366 | 827df9f3 | balrog | # define OMAP_INT_24XX_WDT4 36 |
367 | c3d2689d | balrog | # define OMAP_INT_24XX_GPTIMER1 37 |
368 | c3d2689d | balrog | # define OMAP_INT_24XX_GPTIMER2 38 |
369 | c3d2689d | balrog | # define OMAP_INT_24XX_GPTIMER3 39 |
370 | c3d2689d | balrog | # define OMAP_INT_24XX_GPTIMER4 40 |
371 | c3d2689d | balrog | # define OMAP_INT_24XX_GPTIMER5 41 |
372 | c3d2689d | balrog | # define OMAP_INT_24XX_GPTIMER6 42 |
373 | c3d2689d | balrog | # define OMAP_INT_24XX_GPTIMER7 43 |
374 | c3d2689d | balrog | # define OMAP_INT_24XX_GPTIMER8 44 |
375 | c3d2689d | balrog | # define OMAP_INT_24XX_GPTIMER9 45 |
376 | c3d2689d | balrog | # define OMAP_INT_24XX_GPTIMER10 46 |
377 | c3d2689d | balrog | # define OMAP_INT_24XX_GPTIMER11 47 |
378 | c3d2689d | balrog | # define OMAP_INT_24XX_GPTIMER12 48 |
379 | 827df9f3 | balrog | # define OMAP_INT_24XX_PKA_IRQ 50 |
380 | 827df9f3 | balrog | # define OMAP_INT_24XX_SHA1MD5_IRQ 51 |
381 | 827df9f3 | balrog | # define OMAP_INT_24XX_RNG_IRQ 52 |
382 | 827df9f3 | balrog | # define OMAP_INT_24XX_MG_IRQ 53 |
383 | 827df9f3 | balrog | # define OMAP_INT_24XX_I2C1_IRQ 56 |
384 | 827df9f3 | balrog | # define OMAP_INT_24XX_I2C2_IRQ 57 |
385 | c3d2689d | balrog | # define OMAP_INT_24XX_MCBSP1_IRQ_TX 59 |
386 | c3d2689d | balrog | # define OMAP_INT_24XX_MCBSP1_IRQ_RX 60 |
387 | c3d2689d | balrog | # define OMAP_INT_24XX_MCBSP2_IRQ_TX 62 |
388 | c3d2689d | balrog | # define OMAP_INT_24XX_MCBSP2_IRQ_RX 63 |
389 | 827df9f3 | balrog | # define OMAP_INT_243X_MCBSP1_IRQ 64 |
390 | 827df9f3 | balrog | # define OMAP_INT_24XX_MCSPI1_IRQ 65 |
391 | 827df9f3 | balrog | # define OMAP_INT_24XX_MCSPI2_IRQ 66 |
392 | 827df9f3 | balrog | # define OMAP_INT_24XX_SSI1_IRQ0 67 |
393 | 827df9f3 | balrog | # define OMAP_INT_24XX_SSI1_IRQ1 68 |
394 | 827df9f3 | balrog | # define OMAP_INT_24XX_SSI2_IRQ0 69 |
395 | 827df9f3 | balrog | # define OMAP_INT_24XX_SSI2_IRQ1 70 |
396 | 827df9f3 | balrog | # define OMAP_INT_24XX_SSI_GDD_IRQ 71 |
397 | c3d2689d | balrog | # define OMAP_INT_24XX_UART1_IRQ 72 |
398 | c3d2689d | balrog | # define OMAP_INT_24XX_UART2_IRQ 73 |
399 | c3d2689d | balrog | # define OMAP_INT_24XX_UART3_IRQ 74 |
400 | c3d2689d | balrog | # define OMAP_INT_24XX_USB_IRQ_GEN 75 |
401 | c3d2689d | balrog | # define OMAP_INT_24XX_USB_IRQ_NISO 76 |
402 | c3d2689d | balrog | # define OMAP_INT_24XX_USB_IRQ_ISO 77 |
403 | c3d2689d | balrog | # define OMAP_INT_24XX_USB_IRQ_HGEN 78 |
404 | c3d2689d | balrog | # define OMAP_INT_24XX_USB_IRQ_HSOF 79 |
405 | c3d2689d | balrog | # define OMAP_INT_24XX_USB_IRQ_OTG 80 |
406 | 827df9f3 | balrog | # define OMAP_INT_24XX_VLYNQ_IRQ 81 |
407 | c3d2689d | balrog | # define OMAP_INT_24XX_MMC_IRQ 83 |
408 | 827df9f3 | balrog | # define OMAP_INT_24XX_MS_IRQ 84 |
409 | 827df9f3 | balrog | # define OMAP_INT_24XX_FAC_IRQ 85 |
410 | 827df9f3 | balrog | # define OMAP_INT_24XX_MCSPI3_IRQ 91 |
411 | c3d2689d | balrog | # define OMAP_INT_243X_HS_USB_MC 92 |
412 | c3d2689d | balrog | # define OMAP_INT_243X_HS_USB_DMA 93 |
413 | c3d2689d | balrog | # define OMAP_INT_243X_CARKIT 94 |
414 | 827df9f3 | balrog | # define OMAP_INT_34XX_GPTIMER12 95 |
415 | c3d2689d | balrog | |
416 | b4e3104b | balrog | /* omap_dma.c */
|
417 | 089b7c0a | balrog | enum omap_dma_model {
|
418 | b4e3104b | balrog | omap_dma_3_0, |
419 | b4e3104b | balrog | omap_dma_3_1, |
420 | b4e3104b | balrog | omap_dma_3_2, |
421 | b4e3104b | balrog | omap_dma_4, |
422 | 089b7c0a | balrog | }; |
423 | 089b7c0a | balrog | |
424 | afbb5194 | balrog | struct soc_dma_s;
|
425 | c227f099 | Anthony Liguori | struct soc_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs,
|
426 | 089b7c0a | balrog | qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk,
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427 | 089b7c0a | balrog | enum omap_dma_model model);
|
428 | c227f099 | Anthony Liguori | struct soc_dma_s *omap_dma4_init(target_phys_addr_t base, qemu_irq *irqs,
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429 | 827df9f3 | balrog | struct omap_mpu_state_s *mpu, int fifo, |
430 | 827df9f3 | balrog | int chans, omap_clk iclk, omap_clk fclk);
|
431 | afbb5194 | balrog | void omap_dma_reset(struct soc_dma_s *s); |
432 | c3d2689d | balrog | |
433 | b4e3104b | balrog | struct dma_irq_map {
|
434 | b4e3104b | balrog | int ih;
|
435 | b4e3104b | balrog | int intr;
|
436 | b4e3104b | balrog | }; |
437 | b4e3104b | balrog | |
438 | b4e3104b | balrog | /* Only used in OMAP DMA 3.x gigacells */
|
439 | c3d2689d | balrog | enum omap_dma_port {
|
440 | c3d2689d | balrog | emiff = 0,
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441 | c3d2689d | balrog | emifs, |
442 | 089b7c0a | balrog | imif, /* omap16xx: ocp_t1 */
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443 | c3d2689d | balrog | tipb, |
444 | 089b7c0a | balrog | local, /* omap16xx: ocp_t2 */
|
445 | c3d2689d | balrog | tipb_mpui, |
446 | 827df9f3 | balrog | __omap_dma_port_last, |
447 | c3d2689d | balrog | }; |
448 | c3d2689d | balrog | |
449 | 089b7c0a | balrog | typedef enum { |
450 | 089b7c0a | balrog | constant = 0,
|
451 | 089b7c0a | balrog | post_incremented, |
452 | 089b7c0a | balrog | single_index, |
453 | 089b7c0a | balrog | double_index, |
454 | c227f099 | Anthony Liguori | } omap_dma_addressing_t; |
455 | 089b7c0a | balrog | |
456 | b4e3104b | balrog | /* Only used in OMAP DMA 3.x gigacells */
|
457 | c3d2689d | balrog | struct omap_dma_lcd_channel_s {
|
458 | c3d2689d | balrog | enum omap_dma_port src;
|
459 | c227f099 | Anthony Liguori | target_phys_addr_t src_f1_top; |
460 | c227f099 | Anthony Liguori | target_phys_addr_t src_f1_bottom; |
461 | c227f099 | Anthony Liguori | target_phys_addr_t src_f2_top; |
462 | c227f099 | Anthony Liguori | target_phys_addr_t src_f2_bottom; |
463 | 089b7c0a | balrog | |
464 | 089b7c0a | balrog | /* Used in OMAP DMA 3.2 gigacell */
|
465 | 089b7c0a | balrog | unsigned char brust_f1; |
466 | 089b7c0a | balrog | unsigned char pack_f1; |
467 | 089b7c0a | balrog | unsigned char data_type_f1; |
468 | 089b7c0a | balrog | unsigned char brust_f2; |
469 | 089b7c0a | balrog | unsigned char pack_f2; |
470 | 089b7c0a | balrog | unsigned char data_type_f2; |
471 | 089b7c0a | balrog | unsigned char end_prog; |
472 | 089b7c0a | balrog | unsigned char repeat; |
473 | 089b7c0a | balrog | unsigned char auto_init; |
474 | 089b7c0a | balrog | unsigned char priority; |
475 | 089b7c0a | balrog | unsigned char fs; |
476 | 089b7c0a | balrog | unsigned char running; |
477 | 089b7c0a | balrog | unsigned char bs; |
478 | 089b7c0a | balrog | unsigned char omap_3_1_compatible_disable; |
479 | 089b7c0a | balrog | unsigned char dst; |
480 | 089b7c0a | balrog | unsigned char lch_type; |
481 | 089b7c0a | balrog | int16_t element_index_f1; |
482 | 089b7c0a | balrog | int16_t element_index_f2; |
483 | 089b7c0a | balrog | int32_t frame_index_f1; |
484 | 089b7c0a | balrog | int32_t frame_index_f2; |
485 | 089b7c0a | balrog | uint16_t elements_f1; |
486 | 089b7c0a | balrog | uint16_t frames_f1; |
487 | 089b7c0a | balrog | uint16_t elements_f2; |
488 | 089b7c0a | balrog | uint16_t frames_f2; |
489 | c227f099 | Anthony Liguori | omap_dma_addressing_t mode_f1; |
490 | c227f099 | Anthony Liguori | omap_dma_addressing_t mode_f2; |
491 | 089b7c0a | balrog | |
492 | c3d2689d | balrog | /* Destination port is fixed. */
|
493 | c3d2689d | balrog | int interrupts;
|
494 | c3d2689d | balrog | int condition;
|
495 | c3d2689d | balrog | int dual;
|
496 | c3d2689d | balrog | |
497 | c3d2689d | balrog | int current_frame;
|
498 | c227f099 | Anthony Liguori | target_phys_addr_t phys_framebuffer[2];
|
499 | c3d2689d | balrog | qemu_irq irq; |
500 | c3d2689d | balrog | struct omap_mpu_state_s *mpu;
|
501 | afbb5194 | balrog | } *omap_dma_get_lcdch(struct soc_dma_s *s);
|
502 | c3d2689d | balrog | |
503 | c3d2689d | balrog | /*
|
504 | c3d2689d | balrog | * DMA request numbers for OMAP1
|
505 | c3d2689d | balrog | * See /usr/include/asm-arm/arch-omap/dma.h in Linux.
|
506 | c3d2689d | balrog | */
|
507 | c3d2689d | balrog | # define OMAP_DMA_NO_DEVICE 0 |
508 | c3d2689d | balrog | # define OMAP_DMA_MCSI1_TX 1 |
509 | c3d2689d | balrog | # define OMAP_DMA_MCSI1_RX 2 |
510 | c3d2689d | balrog | # define OMAP_DMA_I2C_RX 3 |
511 | c3d2689d | balrog | # define OMAP_DMA_I2C_TX 4 |
512 | c3d2689d | balrog | # define OMAP_DMA_EXT_NDMA_REQ0 5 |
513 | c3d2689d | balrog | # define OMAP_DMA_EXT_NDMA_REQ1 6 |
514 | c3d2689d | balrog | # define OMAP_DMA_UWIRE_TX 7 |
515 | c3d2689d | balrog | # define OMAP_DMA_MCBSP1_TX 8 |
516 | c3d2689d | balrog | # define OMAP_DMA_MCBSP1_RX 9 |
517 | c3d2689d | balrog | # define OMAP_DMA_MCBSP3_TX 10 |
518 | c3d2689d | balrog | # define OMAP_DMA_MCBSP3_RX 11 |
519 | c3d2689d | balrog | # define OMAP_DMA_UART1_TX 12 |
520 | c3d2689d | balrog | # define OMAP_DMA_UART1_RX 13 |
521 | c3d2689d | balrog | # define OMAP_DMA_UART2_TX 14 |
522 | c3d2689d | balrog | # define OMAP_DMA_UART2_RX 15 |
523 | c3d2689d | balrog | # define OMAP_DMA_MCBSP2_TX 16 |
524 | c3d2689d | balrog | # define OMAP_DMA_MCBSP2_RX 17 |
525 | c3d2689d | balrog | # define OMAP_DMA_UART3_TX 18 |
526 | c3d2689d | balrog | # define OMAP_DMA_UART3_RX 19 |
527 | c3d2689d | balrog | # define OMAP_DMA_CAMERA_IF_RX 20 |
528 | c3d2689d | balrog | # define OMAP_DMA_MMC_TX 21 |
529 | c3d2689d | balrog | # define OMAP_DMA_MMC_RX 22 |
530 | c3d2689d | balrog | # define OMAP_DMA_NAND 23 /* Not in OMAP310 */ |
531 | c3d2689d | balrog | # define OMAP_DMA_IRQ_LCD_LINE 24 /* Not in OMAP310 */ |
532 | c3d2689d | balrog | # define OMAP_DMA_MEMORY_STICK 25 /* Not in OMAP310 */ |
533 | c3d2689d | balrog | # define OMAP_DMA_USB_W2FC_RX0 26 |
534 | c3d2689d | balrog | # define OMAP_DMA_USB_W2FC_RX1 27 |
535 | c3d2689d | balrog | # define OMAP_DMA_USB_W2FC_RX2 28 |
536 | c3d2689d | balrog | # define OMAP_DMA_USB_W2FC_TX0 29 |
537 | c3d2689d | balrog | # define OMAP_DMA_USB_W2FC_TX1 30 |
538 | c3d2689d | balrog | # define OMAP_DMA_USB_W2FC_TX2 31 |
539 | c3d2689d | balrog | |
540 | c3d2689d | balrog | /* These are only for 1610 */
|
541 | c3d2689d | balrog | # define OMAP_DMA_CRYPTO_DES_IN 32 |
542 | c3d2689d | balrog | # define OMAP_DMA_SPI_TX 33 |
543 | c3d2689d | balrog | # define OMAP_DMA_SPI_RX 34 |
544 | c3d2689d | balrog | # define OMAP_DMA_CRYPTO_HASH 35 |
545 | c3d2689d | balrog | # define OMAP_DMA_CCP_ATTN 36 |
546 | c3d2689d | balrog | # define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37 |
547 | c3d2689d | balrog | # define OMAP_DMA_CMT_APE_TX_CHAN_0 38 |
548 | c3d2689d | balrog | # define OMAP_DMA_CMT_APE_RV_CHAN_0 39 |
549 | c3d2689d | balrog | # define OMAP_DMA_CMT_APE_TX_CHAN_1 40 |
550 | c3d2689d | balrog | # define OMAP_DMA_CMT_APE_RV_CHAN_1 41 |
551 | c3d2689d | balrog | # define OMAP_DMA_CMT_APE_TX_CHAN_2 42 |
552 | c3d2689d | balrog | # define OMAP_DMA_CMT_APE_RV_CHAN_2 43 |
553 | c3d2689d | balrog | # define OMAP_DMA_CMT_APE_TX_CHAN_3 44 |
554 | c3d2689d | balrog | # define OMAP_DMA_CMT_APE_RV_CHAN_3 45 |
555 | c3d2689d | balrog | # define OMAP_DMA_CMT_APE_TX_CHAN_4 46 |
556 | c3d2689d | balrog | # define OMAP_DMA_CMT_APE_RV_CHAN_4 47 |
557 | c3d2689d | balrog | # define OMAP_DMA_CMT_APE_TX_CHAN_5 48 |
558 | c3d2689d | balrog | # define OMAP_DMA_CMT_APE_RV_CHAN_5 49 |
559 | c3d2689d | balrog | # define OMAP_DMA_CMT_APE_TX_CHAN_6 50 |
560 | c3d2689d | balrog | # define OMAP_DMA_CMT_APE_RV_CHAN_6 51 |
561 | c3d2689d | balrog | # define OMAP_DMA_CMT_APE_TX_CHAN_7 52 |
562 | c3d2689d | balrog | # define OMAP_DMA_CMT_APE_RV_CHAN_7 53 |
563 | c3d2689d | balrog | # define OMAP_DMA_MMC2_TX 54 |
564 | c3d2689d | balrog | # define OMAP_DMA_MMC2_RX 55 |
565 | c3d2689d | balrog | # define OMAP_DMA_CRYPTO_DES_OUT 56 |
566 | c3d2689d | balrog | |
567 | 827df9f3 | balrog | /*
|
568 | 827df9f3 | balrog | * DMA request numbers for the OMAP2
|
569 | 827df9f3 | balrog | */
|
570 | 827df9f3 | balrog | # define OMAP24XX_DMA_NO_DEVICE 0 |
571 | 827df9f3 | balrog | # define OMAP24XX_DMA_XTI_DMA 1 /* Not in OMAP2420 */ |
572 | 827df9f3 | balrog | # define OMAP24XX_DMA_EXT_DMAREQ0 2 |
573 | 827df9f3 | balrog | # define OMAP24XX_DMA_EXT_DMAREQ1 3 |
574 | 827df9f3 | balrog | # define OMAP24XX_DMA_GPMC 4 |
575 | 827df9f3 | balrog | # define OMAP24XX_DMA_GFX 5 /* Not in OMAP2420 */ |
576 | 827df9f3 | balrog | # define OMAP24XX_DMA_DSS 6 |
577 | 827df9f3 | balrog | # define OMAP24XX_DMA_VLYNQ_TX 7 /* Not in OMAP2420 */ |
578 | 827df9f3 | balrog | # define OMAP24XX_DMA_CWT 8 /* Not in OMAP2420 */ |
579 | 827df9f3 | balrog | # define OMAP24XX_DMA_AES_TX 9 /* Not in OMAP2420 */ |
580 | 827df9f3 | balrog | # define OMAP24XX_DMA_AES_RX 10 /* Not in OMAP2420 */ |
581 | 827df9f3 | balrog | # define OMAP24XX_DMA_DES_TX 11 /* Not in OMAP2420 */ |
582 | 827df9f3 | balrog | # define OMAP24XX_DMA_DES_RX 12 /* Not in OMAP2420 */ |
583 | 827df9f3 | balrog | # define OMAP24XX_DMA_SHA1MD5_RX 13 /* Not in OMAP2420 */ |
584 | 827df9f3 | balrog | # define OMAP24XX_DMA_EXT_DMAREQ2 14 |
585 | 827df9f3 | balrog | # define OMAP24XX_DMA_EXT_DMAREQ3 15 |
586 | 827df9f3 | balrog | # define OMAP24XX_DMA_EXT_DMAREQ4 16 |
587 | 827df9f3 | balrog | # define OMAP24XX_DMA_EAC_AC_RD 17 |
588 | 827df9f3 | balrog | # define OMAP24XX_DMA_EAC_AC_WR 18 |
589 | 827df9f3 | balrog | # define OMAP24XX_DMA_EAC_MD_UL_RD 19 |
590 | 827df9f3 | balrog | # define OMAP24XX_DMA_EAC_MD_UL_WR 20 |
591 | 827df9f3 | balrog | # define OMAP24XX_DMA_EAC_MD_DL_RD 21 |
592 | 827df9f3 | balrog | # define OMAP24XX_DMA_EAC_MD_DL_WR 22 |
593 | 827df9f3 | balrog | # define OMAP24XX_DMA_EAC_BT_UL_RD 23 |
594 | 827df9f3 | balrog | # define OMAP24XX_DMA_EAC_BT_UL_WR 24 |
595 | 827df9f3 | balrog | # define OMAP24XX_DMA_EAC_BT_DL_RD 25 |
596 | 827df9f3 | balrog | # define OMAP24XX_DMA_EAC_BT_DL_WR 26 |
597 | 827df9f3 | balrog | # define OMAP24XX_DMA_I2C1_TX 27 |
598 | 827df9f3 | balrog | # define OMAP24XX_DMA_I2C1_RX 28 |
599 | 827df9f3 | balrog | # define OMAP24XX_DMA_I2C2_TX 29 |
600 | 827df9f3 | balrog | # define OMAP24XX_DMA_I2C2_RX 30 |
601 | 827df9f3 | balrog | # define OMAP24XX_DMA_MCBSP1_TX 31 |
602 | 827df9f3 | balrog | # define OMAP24XX_DMA_MCBSP1_RX 32 |
603 | 827df9f3 | balrog | # define OMAP24XX_DMA_MCBSP2_TX 33 |
604 | 827df9f3 | balrog | # define OMAP24XX_DMA_MCBSP2_RX 34 |
605 | 827df9f3 | balrog | # define OMAP24XX_DMA_SPI1_TX0 35 |
606 | 827df9f3 | balrog | # define OMAP24XX_DMA_SPI1_RX0 36 |
607 | 827df9f3 | balrog | # define OMAP24XX_DMA_SPI1_TX1 37 |
608 | 827df9f3 | balrog | # define OMAP24XX_DMA_SPI1_RX1 38 |
609 | 827df9f3 | balrog | # define OMAP24XX_DMA_SPI1_TX2 39 |
610 | 827df9f3 | balrog | # define OMAP24XX_DMA_SPI1_RX2 40 |
611 | 827df9f3 | balrog | # define OMAP24XX_DMA_SPI1_TX3 41 |
612 | 827df9f3 | balrog | # define OMAP24XX_DMA_SPI1_RX3 42 |
613 | 827df9f3 | balrog | # define OMAP24XX_DMA_SPI2_TX0 43 |
614 | 827df9f3 | balrog | # define OMAP24XX_DMA_SPI2_RX0 44 |
615 | 827df9f3 | balrog | # define OMAP24XX_DMA_SPI2_TX1 45 |
616 | 827df9f3 | balrog | # define OMAP24XX_DMA_SPI2_RX1 46 |
617 | 827df9f3 | balrog | |
618 | 827df9f3 | balrog | # define OMAP24XX_DMA_UART1_TX 49 |
619 | 827df9f3 | balrog | # define OMAP24XX_DMA_UART1_RX 50 |
620 | 827df9f3 | balrog | # define OMAP24XX_DMA_UART2_TX 51 |
621 | 827df9f3 | balrog | # define OMAP24XX_DMA_UART2_RX 52 |
622 | 827df9f3 | balrog | # define OMAP24XX_DMA_UART3_TX 53 |
623 | 827df9f3 | balrog | # define OMAP24XX_DMA_UART3_RX 54 |
624 | 827df9f3 | balrog | # define OMAP24XX_DMA_USB_W2FC_TX0 55 |
625 | 827df9f3 | balrog | # define OMAP24XX_DMA_USB_W2FC_RX0 56 |
626 | 827df9f3 | balrog | # define OMAP24XX_DMA_USB_W2FC_TX1 57 |
627 | 827df9f3 | balrog | # define OMAP24XX_DMA_USB_W2FC_RX1 58 |
628 | 827df9f3 | balrog | # define OMAP24XX_DMA_USB_W2FC_TX2 59 |
629 | 827df9f3 | balrog | # define OMAP24XX_DMA_USB_W2FC_RX2 60 |
630 | 827df9f3 | balrog | # define OMAP24XX_DMA_MMC1_TX 61 |
631 | 827df9f3 | balrog | # define OMAP24XX_DMA_MMC1_RX 62 |
632 | 827df9f3 | balrog | # define OMAP24XX_DMA_MS 63 /* Not in OMAP2420 */ |
633 | 827df9f3 | balrog | # define OMAP24XX_DMA_EXT_DMAREQ5 64 |
634 | 827df9f3 | balrog | |
635 | b4e3104b | balrog | /* omap[123].c */
|
636 | c3d2689d | balrog | struct omap_mpu_timer_s;
|
637 | c227f099 | Anthony Liguori | struct omap_mpu_timer_s *omap_mpu_timer_init(target_phys_addr_t base,
|
638 | c3d2689d | balrog | qemu_irq irq, omap_clk clk); |
639 | c3d2689d | balrog | |
640 | c58d37cf | cmchao | /* OMAP2 gp timer */
|
641 | 827df9f3 | balrog | struct omap_gp_timer_s;
|
642 | 827df9f3 | balrog | struct omap_gp_timer_s *omap_gp_timer_init(struct omap_target_agent_s *ta, |
643 | 827df9f3 | balrog | qemu_irq irq, omap_clk fclk, omap_clk iclk); |
644 | c58d37cf | cmchao | void omap_gp_timer_reset(struct omap_gp_timer_s *s); |
645 | 827df9f3 | balrog | |
646 | c3d2689d | balrog | struct omap_watchdog_timer_s;
|
647 | c227f099 | Anthony Liguori | struct omap_watchdog_timer_s *omap_wd_timer_init(target_phys_addr_t base,
|
648 | c3d2689d | balrog | qemu_irq irq, omap_clk clk); |
649 | c3d2689d | balrog | |
650 | c3d2689d | balrog | struct omap_32khz_timer_s;
|
651 | c227f099 | Anthony Liguori | struct omap_32khz_timer_s *omap_os_timer_init(target_phys_addr_t base,
|
652 | c3d2689d | balrog | qemu_irq irq, omap_clk clk); |
653 | c3d2689d | balrog | |
654 | 011d87d0 | cmchao | /* OMAP2 sysctimer */
|
655 | 011d87d0 | cmchao | struct omap_synctimer_s;
|
656 | 011d87d0 | cmchao | struct omap_synctimer_s *omap_synctimer_init(struct omap_target_agent_s *ta, |
657 | 827df9f3 | balrog | struct omap_mpu_state_s *mpu, omap_clk fclk, omap_clk iclk);
|
658 | 011d87d0 | cmchao | void omap_synctimer_reset(struct omap_synctimer_s *s); |
659 | 827df9f3 | balrog | |
660 | c3d2689d | balrog | struct omap_tipb_bridge_s;
|
661 | c227f099 | Anthony Liguori | struct omap_tipb_bridge_s *omap_tipb_bridge_init(target_phys_addr_t base,
|
662 | c3d2689d | balrog | qemu_irq abort_irq, omap_clk clk); |
663 | c3d2689d | balrog | |
664 | c3d2689d | balrog | struct omap_uart_s;
|
665 | c227f099 | Anthony Liguori | struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
|
666 | 827df9f3 | balrog | qemu_irq irq, omap_clk fclk, omap_clk iclk, |
667 | 827df9f3 | balrog | qemu_irq txdma, qemu_irq rxdma, CharDriverState *chr); |
668 | 827df9f3 | balrog | struct omap_uart_s *omap2_uart_init(struct omap_target_agent_s *ta, |
669 | 827df9f3 | balrog | qemu_irq irq, omap_clk fclk, omap_clk iclk, |
670 | 827df9f3 | balrog | qemu_irq txdma, qemu_irq rxdma, CharDriverState *chr); |
671 | 827df9f3 | balrog | void omap_uart_reset(struct omap_uart_s *s); |
672 | 75554a3c | balrog | void omap_uart_attach(struct omap_uart_s *s, CharDriverState *chr); |
673 | c3d2689d | balrog | |
674 | fe71e81a | balrog | struct omap_mpuio_s;
|
675 | c227f099 | Anthony Liguori | struct omap_mpuio_s *omap_mpuio_init(target_phys_addr_t base,
|
676 | fe71e81a | balrog | qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup, |
677 | fe71e81a | balrog | omap_clk clk); |
678 | fe71e81a | balrog | qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s);
|
679 | fe71e81a | balrog | void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler); |
680 | fe71e81a | balrog | void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down); |
681 | fe71e81a | balrog | |
682 | d82310f7 | cmchao | /* omap1 gpio module interface */
|
683 | 64330148 | balrog | struct omap_gpio_s;
|
684 | c227f099 | Anthony Liguori | struct omap_gpio_s *omap_gpio_init(target_phys_addr_t base,
|
685 | 64330148 | balrog | qemu_irq irq, omap_clk clk); |
686 | e5c6b25a | cmchao | void omap_gpio_reset(struct omap_gpio_s *s); |
687 | 64330148 | balrog | qemu_irq *omap_gpio_in_get(struct omap_gpio_s *s);
|
688 | 64330148 | balrog | void omap_gpio_out_set(struct omap_gpio_s *s, int line, qemu_irq handler); |
689 | 64330148 | balrog | |
690 | d82310f7 | cmchao | /* omap2 gpio interface */
|
691 | 827df9f3 | balrog | struct omap_gpif_s;
|
692 | 827df9f3 | balrog | struct omap_gpif_s *omap2_gpio_init(struct omap_target_agent_s *ta, |
693 | 827df9f3 | balrog | qemu_irq *irq, omap_clk *fclk, omap_clk iclk, int modules);
|
694 | d82310f7 | cmchao | void omap_gpif_reset(struct omap_gpif_s *s); |
695 | 827df9f3 | balrog | qemu_irq *omap2_gpio_in_get(struct omap_gpif_s *s, int start); |
696 | 827df9f3 | balrog | void omap2_gpio_out_set(struct omap_gpif_s *s, int line, qemu_irq handler); |
697 | 827df9f3 | balrog | |
698 | bc24a225 | Paul Brook | struct uWireSlave {
|
699 | d951f6ff | balrog | uint16_t (*receive)(void *opaque);
|
700 | d951f6ff | balrog | void (*send)(void *opaque, uint16_t data); |
701 | d951f6ff | balrog | void *opaque;
|
702 | d951f6ff | balrog | }; |
703 | d951f6ff | balrog | struct omap_uwire_s;
|
704 | c227f099 | Anthony Liguori | struct omap_uwire_s *omap_uwire_init(target_phys_addr_t base,
|
705 | d951f6ff | balrog | qemu_irq *irq, qemu_irq dma, omap_clk clk); |
706 | d951f6ff | balrog | void omap_uwire_attach(struct omap_uwire_s *s, |
707 | bc24a225 | Paul Brook | uWireSlave *slave, int chipselect);
|
708 | d951f6ff | balrog | |
709 | 827df9f3 | balrog | struct omap_mcspi_s;
|
710 | 827df9f3 | balrog | struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum, |
711 | 827df9f3 | balrog | qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk); |
712 | 827df9f3 | balrog | void omap_mcspi_attach(struct omap_mcspi_s *s, |
713 | e927bb00 | balrog | uint32_t (*txrx)(void *opaque, uint32_t, int), void *opaque, |
714 | 827df9f3 | balrog | int chipselect);
|
715 | 827df9f3 | balrog | |
716 | 5c1c390f | balrog | struct omap_rtc_s;
|
717 | c227f099 | Anthony Liguori | struct omap_rtc_s *omap_rtc_init(target_phys_addr_t base,
|
718 | 5c1c390f | balrog | qemu_irq *irq, omap_clk clk); |
719 | 5c1c390f | balrog | |
720 | bc24a225 | Paul Brook | struct I2SCodec {
|
721 | d8f699cb | balrog | void *opaque;
|
722 | d8f699cb | balrog | |
723 | d8f699cb | balrog | /* The CPU can call this if it is generating the clock signal on the
|
724 | d8f699cb | balrog | * i2s port. The CODEC can ignore it if it is set up as a clock
|
725 | d8f699cb | balrog | * master and generates its own clock. */
|
726 | d8f699cb | balrog | void (*set_rate)(void *opaque, int in, int out); |
727 | d8f699cb | balrog | |
728 | d8f699cb | balrog | void (*tx_swallow)(void *opaque); |
729 | d8f699cb | balrog | qemu_irq rx_swallow; |
730 | d8f699cb | balrog | qemu_irq tx_start; |
731 | d8f699cb | balrog | |
732 | 73560bc8 | balrog | int tx_rate;
|
733 | 73560bc8 | balrog | int cts;
|
734 | 73560bc8 | balrog | int rx_rate;
|
735 | 73560bc8 | balrog | int rts;
|
736 | 73560bc8 | balrog | |
737 | d8f699cb | balrog | struct i2s_fifo_s {
|
738 | d8f699cb | balrog | uint8_t *fifo; |
739 | d8f699cb | balrog | int len;
|
740 | d8f699cb | balrog | int start;
|
741 | d8f699cb | balrog | int size;
|
742 | d8f699cb | balrog | } in, out; |
743 | d8f699cb | balrog | }; |
744 | d8f699cb | balrog | struct omap_mcbsp_s;
|
745 | c227f099 | Anthony Liguori | struct omap_mcbsp_s *omap_mcbsp_init(target_phys_addr_t base,
|
746 | d8f699cb | balrog | qemu_irq *irq, qemu_irq *dma, omap_clk clk); |
747 | bc24a225 | Paul Brook | void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, I2SCodec *slave); |
748 | d8f699cb | balrog | |
749 | f9d43072 | balrog | struct omap_lpg_s;
|
750 | c227f099 | Anthony Liguori | struct omap_lpg_s *omap_lpg_init(target_phys_addr_t base, omap_clk clk);
|
751 | f9d43072 | balrog | |
752 | 827df9f3 | balrog | void omap_tap_init(struct omap_target_agent_s *ta, |
753 | 827df9f3 | balrog | struct omap_mpu_state_s *mpu);
|
754 | 827df9f3 | balrog | |
755 | 99570a40 | balrog | struct omap_eac_s;
|
756 | 99570a40 | balrog | struct omap_eac_s *omap_eac_init(struct omap_target_agent_s *ta, |
757 | 99570a40 | balrog | qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk); |
758 | 99570a40 | balrog | |
759 | c3d2689d | balrog | /* omap_lcdc.c */
|
760 | c3d2689d | balrog | struct omap_lcd_panel_s;
|
761 | c3d2689d | balrog | void omap_lcdc_reset(struct omap_lcd_panel_s *s); |
762 | c227f099 | Anthony Liguori | struct omap_lcd_panel_s *omap_lcdc_init(target_phys_addr_t base, qemu_irq irq,
|
763 | 3023f332 | aliguori | struct omap_dma_lcd_channel_s *dma,
|
764 | c227f099 | Anthony Liguori | ram_addr_t imif_base, ram_addr_t emiff_base, omap_clk clk); |
765 | c3d2689d | balrog | |
766 | 827df9f3 | balrog | /* omap_dss.c */
|
767 | 827df9f3 | balrog | struct rfbi_chip_s {
|
768 | 827df9f3 | balrog | void *opaque;
|
769 | 827df9f3 | balrog | void (*write)(void *opaque, int dc, uint16_t value); |
770 | 827df9f3 | balrog | void (*block)(void *opaque, int dc, void *buf, size_t len, int pitch); |
771 | 827df9f3 | balrog | uint16_t (*read)(void *opaque, int dc); |
772 | 827df9f3 | balrog | }; |
773 | 827df9f3 | balrog | struct omap_dss_s;
|
774 | 827df9f3 | balrog | void omap_dss_reset(struct omap_dss_s *s); |
775 | 827df9f3 | balrog | struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta, |
776 | c227f099 | Anthony Liguori | target_phys_addr_t l3_base, |
777 | 827df9f3 | balrog | qemu_irq irq, qemu_irq drq, |
778 | 827df9f3 | balrog | omap_clk fck1, omap_clk fck2, omap_clk ck54m, |
779 | 827df9f3 | balrog | omap_clk ick1, omap_clk ick2); |
780 | 827df9f3 | balrog | void omap_rfbi_attach(struct omap_dss_s *s, int cs, struct rfbi_chip_s *chip); |
781 | 827df9f3 | balrog | |
782 | b30bb3a2 | balrog | /* omap_mmc.c */
|
783 | b30bb3a2 | balrog | struct omap_mmc_s;
|
784 | c227f099 | Anthony Liguori | struct omap_mmc_s *omap_mmc_init(target_phys_addr_t base,
|
785 | 87ecb68b | pbrook | BlockDriverState *bd, |
786 | b30bb3a2 | balrog | qemu_irq irq, qemu_irq dma[], omap_clk clk); |
787 | 827df9f3 | balrog | struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta, |
788 | 827df9f3 | balrog | BlockDriverState *bd, qemu_irq irq, qemu_irq dma[], |
789 | 827df9f3 | balrog | omap_clk fclk, omap_clk iclk); |
790 | b30bb3a2 | balrog | void omap_mmc_reset(struct omap_mmc_s *s); |
791 | 8e129e07 | balrog | void omap_mmc_handlers(struct omap_mmc_s *s, qemu_irq ro, qemu_irq cover); |
792 | 827df9f3 | balrog | void omap_mmc_enable(struct omap_mmc_s *s, int enable); |
793 | b30bb3a2 | balrog | |
794 | 02645926 | balrog | /* omap_i2c.c */
|
795 | 02645926 | balrog | struct omap_i2c_s;
|
796 | c227f099 | Anthony Liguori | struct omap_i2c_s *omap_i2c_init(target_phys_addr_t base,
|
797 | 02645926 | balrog | qemu_irq irq, qemu_irq *dma, omap_clk clk); |
798 | 29885477 | balrog | struct omap_i2c_s *omap2_i2c_init(struct omap_target_agent_s *ta, |
799 | 29885477 | balrog | qemu_irq irq, qemu_irq *dma, omap_clk fclk, omap_clk iclk); |
800 | 02645926 | balrog | void omap_i2c_reset(struct omap_i2c_s *s); |
801 | 02645926 | balrog | i2c_bus *omap_i2c_bus(struct omap_i2c_s *s);
|
802 | 02645926 | balrog | |
803 | c3d2689d | balrog | # define cpu_is_omap310(cpu) (cpu->mpu_model == omap310)
|
804 | c3d2689d | balrog | # define cpu_is_omap1510(cpu) (cpu->mpu_model == omap1510)
|
805 | 827df9f3 | balrog | # define cpu_is_omap1610(cpu) (cpu->mpu_model == omap1610)
|
806 | 827df9f3 | balrog | # define cpu_is_omap1710(cpu) (cpu->mpu_model == omap1710)
|
807 | 827df9f3 | balrog | # define cpu_is_omap2410(cpu) (cpu->mpu_model == omap2410)
|
808 | 827df9f3 | balrog | # define cpu_is_omap2420(cpu) (cpu->mpu_model == omap2420)
|
809 | 827df9f3 | balrog | # define cpu_is_omap2430(cpu) (cpu->mpu_model == omap2430)
|
810 | 827df9f3 | balrog | # define cpu_is_omap3430(cpu) (cpu->mpu_model == omap3430)
|
811 | 827df9f3 | balrog | |
812 | c3d2689d | balrog | # define cpu_is_omap15xx(cpu) \
|
813 | c3d2689d | balrog | (cpu_is_omap310(cpu) || cpu_is_omap1510(cpu)) |
814 | 827df9f3 | balrog | # define cpu_is_omap16xx(cpu) \
|
815 | 827df9f3 | balrog | (cpu_is_omap1610(cpu) || cpu_is_omap1710(cpu)) |
816 | 827df9f3 | balrog | # define cpu_is_omap24xx(cpu) \
|
817 | 827df9f3 | balrog | (cpu_is_omap2410(cpu) || cpu_is_omap2420(cpu) || cpu_is_omap2430(cpu)) |
818 | 827df9f3 | balrog | |
819 | 827df9f3 | balrog | # define cpu_class_omap1(cpu) \
|
820 | 827df9f3 | balrog | (cpu_is_omap15xx(cpu) || cpu_is_omap16xx(cpu)) |
821 | 827df9f3 | balrog | # define cpu_class_omap2(cpu) cpu_is_omap24xx(cpu)
|
822 | 827df9f3 | balrog | # define cpu_class_omap3(cpu) cpu_is_omap3430(cpu)
|
823 | c3d2689d | balrog | |
824 | c3d2689d | balrog | struct omap_mpu_state_s {
|
825 | 827df9f3 | balrog | enum omap_mpu_model {
|
826 | c3d2689d | balrog | omap310, |
827 | c3d2689d | balrog | omap1510, |
828 | 827df9f3 | balrog | omap1610, |
829 | 827df9f3 | balrog | omap1710, |
830 | 827df9f3 | balrog | omap2410, |
831 | 827df9f3 | balrog | omap2420, |
832 | 827df9f3 | balrog | omap2422, |
833 | 827df9f3 | balrog | omap2423, |
834 | 827df9f3 | balrog | omap2430, |
835 | 827df9f3 | balrog | omap3430, |
836 | c3d2689d | balrog | } mpu_model; |
837 | c3d2689d | balrog | |
838 | c3d2689d | balrog | CPUState *env; |
839 | c3d2689d | balrog | |
840 | c3d2689d | balrog | qemu_irq *irq[2];
|
841 | c3d2689d | balrog | qemu_irq *drq; |
842 | c3d2689d | balrog | |
843 | c3d2689d | balrog | qemu_irq wakeup; |
844 | c3d2689d | balrog | |
845 | c3d2689d | balrog | struct omap_dma_port_if_s {
|
846 | 5fafdf24 | ths | uint32_t (*read[3])(struct omap_mpu_state_s *s, |
847 | c227f099 | Anthony Liguori | target_phys_addr_t offset); |
848 | c3d2689d | balrog | void (*write[3])(struct omap_mpu_state_s *s, |
849 | c227f099 | Anthony Liguori | target_phys_addr_t offset, uint32_t value); |
850 | c3d2689d | balrog | int (*addr_valid)(struct omap_mpu_state_s *s, |
851 | c227f099 | Anthony Liguori | target_phys_addr_t addr); |
852 | 827df9f3 | balrog | } port[__omap_dma_port_last]; |
853 | c3d2689d | balrog | |
854 | c3d2689d | balrog | unsigned long sdram_size; |
855 | c3d2689d | balrog | unsigned long sram_size; |
856 | c3d2689d | balrog | |
857 | c3d2689d | balrog | /* MPUI-TIPB peripherals */
|
858 | d951f6ff | balrog | struct omap_uart_s *uart[3]; |
859 | d951f6ff | balrog | |
860 | d951f6ff | balrog | struct omap_gpio_s *gpio;
|
861 | c3d2689d | balrog | |
862 | d8f699cb | balrog | struct omap_mcbsp_s *mcbsp1;
|
863 | d8f699cb | balrog | struct omap_mcbsp_s *mcbsp3;
|
864 | d8f699cb | balrog | |
865 | c3d2689d | balrog | /* MPU public TIPB peripherals */
|
866 | c3d2689d | balrog | struct omap_32khz_timer_s *os_timer;
|
867 | c3d2689d | balrog | |
868 | b30bb3a2 | balrog | struct omap_mmc_s *mmc;
|
869 | b30bb3a2 | balrog | |
870 | d951f6ff | balrog | struct omap_mpuio_s *mpuio;
|
871 | d951f6ff | balrog | |
872 | d951f6ff | balrog | struct omap_uwire_s *microwire;
|
873 | d951f6ff | balrog | |
874 | 66450b15 | balrog | struct {
|
875 | 66450b15 | balrog | uint8_t output; |
876 | 66450b15 | balrog | uint8_t level; |
877 | 66450b15 | balrog | uint8_t enable; |
878 | 66450b15 | balrog | int clk;
|
879 | 66450b15 | balrog | } pwl; |
880 | 66450b15 | balrog | |
881 | f34c417b | balrog | struct {
|
882 | f34c417b | balrog | uint8_t frc; |
883 | f34c417b | balrog | uint8_t vrc; |
884 | f34c417b | balrog | uint8_t gcr; |
885 | f34c417b | balrog | omap_clk clk; |
886 | f34c417b | balrog | } pwt; |
887 | f34c417b | balrog | |
888 | 827df9f3 | balrog | struct omap_i2c_s *i2c[2]; |
889 | 4a2c8ac2 | balrog | |
890 | 02645926 | balrog | struct omap_rtc_s *rtc;
|
891 | 02645926 | balrog | |
892 | d8f699cb | balrog | struct omap_mcbsp_s *mcbsp2;
|
893 | d8f699cb | balrog | |
894 | f9d43072 | balrog | struct omap_lpg_s *led[2]; |
895 | f9d43072 | balrog | |
896 | c3d2689d | balrog | /* MPU private TIPB peripherals */
|
897 | c3d2689d | balrog | struct omap_intr_handler_s *ih[2]; |
898 | c3d2689d | balrog | |
899 | afbb5194 | balrog | struct soc_dma_s *dma;
|
900 | c3d2689d | balrog | |
901 | c3d2689d | balrog | struct omap_mpu_timer_s *timer[3]; |
902 | c3d2689d | balrog | struct omap_watchdog_timer_s *wdt;
|
903 | c3d2689d | balrog | |
904 | c3d2689d | balrog | struct omap_lcd_panel_s *lcd;
|
905 | c3d2689d | balrog | |
906 | c3d2689d | balrog | uint32_t ulpd_pm_regs[21];
|
907 | c3d2689d | balrog | int64_t ulpd_gauge_start; |
908 | c3d2689d | balrog | |
909 | c3d2689d | balrog | uint32_t func_mux_ctrl[14];
|
910 | c3d2689d | balrog | uint32_t comp_mode_ctrl[1];
|
911 | c3d2689d | balrog | uint32_t pull_dwn_ctrl[4];
|
912 | c3d2689d | balrog | uint32_t gate_inh_ctrl[1];
|
913 | c3d2689d | balrog | uint32_t voltage_ctrl[1];
|
914 | c3d2689d | balrog | uint32_t test_dbg_ctrl[1];
|
915 | c3d2689d | balrog | uint32_t mod_conf_ctrl[1];
|
916 | c3d2689d | balrog | int compat1509;
|
917 | c3d2689d | balrog | |
918 | c3d2689d | balrog | uint32_t mpui_ctrl; |
919 | c3d2689d | balrog | |
920 | c3d2689d | balrog | struct omap_tipb_bridge_s *private_tipb;
|
921 | c3d2689d | balrog | struct omap_tipb_bridge_s *public_tipb;
|
922 | c3d2689d | balrog | |
923 | c3d2689d | balrog | uint32_t tcmi_regs[17];
|
924 | c3d2689d | balrog | |
925 | c3d2689d | balrog | struct dpll_ctl_s {
|
926 | c3d2689d | balrog | uint16_t mode; |
927 | c3d2689d | balrog | omap_clk dpll; |
928 | c3d2689d | balrog | } dpll[3];
|
929 | c3d2689d | balrog | |
930 | c3d2689d | balrog | omap_clk clks; |
931 | c3d2689d | balrog | struct {
|
932 | c3d2689d | balrog | int cold_start;
|
933 | c3d2689d | balrog | int clocking_scheme;
|
934 | c3d2689d | balrog | uint16_t arm_ckctl; |
935 | c3d2689d | balrog | uint16_t arm_idlect1; |
936 | c3d2689d | balrog | uint16_t arm_idlect2; |
937 | c3d2689d | balrog | uint16_t arm_ewupct; |
938 | c3d2689d | balrog | uint16_t arm_rstct1; |
939 | c3d2689d | balrog | uint16_t arm_rstct2; |
940 | c3d2689d | balrog | uint16_t arm_ckout1; |
941 | c3d2689d | balrog | int dpll1_mode;
|
942 | c3d2689d | balrog | uint16_t dsp_idlect1; |
943 | c3d2689d | balrog | uint16_t dsp_idlect2; |
944 | c3d2689d | balrog | uint16_t dsp_rstct2; |
945 | c3d2689d | balrog | } clkm; |
946 | 827df9f3 | balrog | |
947 | 827df9f3 | balrog | /* OMAP2-only peripherals */
|
948 | 827df9f3 | balrog | struct omap_l4_s *l4;
|
949 | 827df9f3 | balrog | |
950 | 827df9f3 | balrog | struct omap_gp_timer_s *gptimer[12]; |
951 | 011d87d0 | cmchao | struct omap_synctimer_s *synctimer;
|
952 | 827df9f3 | balrog | |
953 | 827df9f3 | balrog | struct omap_prcm_s *prcm;
|
954 | 827df9f3 | balrog | struct omap_sdrc_s *sdrc;
|
955 | 827df9f3 | balrog | struct omap_gpmc_s *gpmc;
|
956 | 827df9f3 | balrog | struct omap_sysctl_s *sysc;
|
957 | 827df9f3 | balrog | |
958 | 827df9f3 | balrog | struct omap_gpif_s *gpif;
|
959 | 827df9f3 | balrog | |
960 | 827df9f3 | balrog | struct omap_mcspi_s *mcspi[2]; |
961 | 827df9f3 | balrog | |
962 | 827df9f3 | balrog | struct omap_dss_s *dss;
|
963 | 99570a40 | balrog | |
964 | 99570a40 | balrog | struct omap_eac_s *eac;
|
965 | 827df9f3 | balrog | }; |
966 | 827df9f3 | balrog | |
967 | 827df9f3 | balrog | /* omap1.c */
|
968 | 827df9f3 | balrog | struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size, |
969 | 3023f332 | aliguori | const char *core); |
970 | 827df9f3 | balrog | |
971 | 827df9f3 | balrog | /* omap2.c */
|
972 | 827df9f3 | balrog | struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size, |
973 | 3023f332 | aliguori | const char *core); |
974 | c3d2689d | balrog | |
975 | c3d2689d | balrog | # if TARGET_PHYS_ADDR_BITS == 32 |
976 | c3d2689d | balrog | # define OMAP_FMT_plx "%#08x" |
977 | c3d2689d | balrog | # elif TARGET_PHYS_ADDR_BITS == 64 |
978 | c3d2689d | balrog | # define OMAP_FMT_plx "%#08" PRIx64 |
979 | c3d2689d | balrog | # else
|
980 | c3d2689d | balrog | # error TARGET_PHYS_ADDR_BITS undefined
|
981 | c3d2689d | balrog | # endif
|
982 | c3d2689d | balrog | |
983 | c227f099 | Anthony Liguori | uint32_t omap_badwidth_read8(void *opaque, target_phys_addr_t addr);
|
984 | c227f099 | Anthony Liguori | void omap_badwidth_write8(void *opaque, target_phys_addr_t addr, |
985 | 9596ebb7 | pbrook | uint32_t value); |
986 | c227f099 | Anthony Liguori | uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr);
|
987 | c227f099 | Anthony Liguori | void omap_badwidth_write16(void *opaque, target_phys_addr_t addr, |
988 | b30bb3a2 | balrog | uint32_t value); |
989 | c227f099 | Anthony Liguori | uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr);
|
990 | c227f099 | Anthony Liguori | void omap_badwidth_write32(void *opaque, target_phys_addr_t addr, |
991 | b30bb3a2 | balrog | uint32_t value); |
992 | b30bb3a2 | balrog | |
993 | 827df9f3 | balrog | void omap_mpu_wakeup(void *opaque, int irq, int req); |
994 | 827df9f3 | balrog | |
995 | c3d2689d | balrog | # define OMAP_BAD_REG(paddr) \
|
996 | 827df9f3 | balrog | fprintf(stderr, "%s: Bad register " OMAP_FMT_plx "\n", \ |
997 | 827df9f3 | balrog | __FUNCTION__, paddr) |
998 | c3d2689d | balrog | # define OMAP_RO_REG(paddr) \
|
999 | 827df9f3 | balrog | fprintf(stderr, "%s: Read-only register " OMAP_FMT_plx "\n", \ |
1000 | c3d2689d | balrog | __FUNCTION__, paddr) |
1001 | b854bc19 | balrog | |
1002 | 827df9f3 | balrog | /* OMAP-specific Linux bootloader tags for the ATAG_BOARD area
|
1003 | 827df9f3 | balrog | (Board-specifc tags are not here) */
|
1004 | 827df9f3 | balrog | #define OMAP_TAG_CLOCK 0x4f01 |
1005 | 827df9f3 | balrog | #define OMAP_TAG_MMC 0x4f02 |
1006 | 827df9f3 | balrog | #define OMAP_TAG_SERIAL_CONSOLE 0x4f03 |
1007 | 827df9f3 | balrog | #define OMAP_TAG_USB 0x4f04 |
1008 | 827df9f3 | balrog | #define OMAP_TAG_LCD 0x4f05 |
1009 | 827df9f3 | balrog | #define OMAP_TAG_GPIO_SWITCH 0x4f06 |
1010 | 827df9f3 | balrog | #define OMAP_TAG_UART 0x4f07 |
1011 | 827df9f3 | balrog | #define OMAP_TAG_FBMEM 0x4f08 |
1012 | 827df9f3 | balrog | #define OMAP_TAG_STI_CONSOLE 0x4f09 |
1013 | 827df9f3 | balrog | #define OMAP_TAG_CAMERA_SENSOR 0x4f0a |
1014 | 827df9f3 | balrog | #define OMAP_TAG_PARTITION 0x4f0b |
1015 | 827df9f3 | balrog | #define OMAP_TAG_TEA5761 0x4f10 |
1016 | 827df9f3 | balrog | #define OMAP_TAG_TMP105 0x4f11 |
1017 | 827df9f3 | balrog | #define OMAP_TAG_BOOT_REASON 0x4f80 |
1018 | 827df9f3 | balrog | #define OMAP_TAG_FLASH_PART_STR 0x4f81 |
1019 | 827df9f3 | balrog | #define OMAP_TAG_VERSION_STR 0x4f82 |
1020 | 827df9f3 | balrog | |
1021 | e927bb00 | balrog | enum {
|
1022 | e927bb00 | balrog | OMAP_GPIOSW_TYPE_COVER = 0 << 4, |
1023 | e927bb00 | balrog | OMAP_GPIOSW_TYPE_CONNECTION = 1 << 4, |
1024 | e927bb00 | balrog | OMAP_GPIOSW_TYPE_ACTIVITY = 2 << 4, |
1025 | e927bb00 | balrog | }; |
1026 | e927bb00 | balrog | |
1027 | e927bb00 | balrog | #define OMAP_GPIOSW_INVERTED 0x0001 |
1028 | e927bb00 | balrog | #define OMAP_GPIOSW_OUTPUT 0x0002 |
1029 | e927bb00 | balrog | |
1030 | b854bc19 | balrog | # define TCMI_VERBOSE 1 |
1031 | d8f699cb | balrog | //# define MEM_VERBOSE 1
|
1032 | b854bc19 | balrog | |
1033 | b854bc19 | balrog | # ifdef TCMI_VERBOSE
|
1034 | b854bc19 | balrog | # define OMAP_8B_REG(paddr) \
|
1035 | 827df9f3 | balrog | fprintf(stderr, "%s: 8-bit register " OMAP_FMT_plx "\n", \ |
1036 | 66450b15 | balrog | __FUNCTION__, paddr) |
1037 | b854bc19 | balrog | # define OMAP_16B_REG(paddr) \
|
1038 | 827df9f3 | balrog | fprintf(stderr, "%s: 16-bit register " OMAP_FMT_plx "\n", \ |
1039 | c3d2689d | balrog | __FUNCTION__, paddr) |
1040 | b854bc19 | balrog | # define OMAP_32B_REG(paddr) \
|
1041 | 827df9f3 | balrog | fprintf(stderr, "%s: 32-bit register " OMAP_FMT_plx "\n", \ |
1042 | c3d2689d | balrog | __FUNCTION__, paddr) |
1043 | b854bc19 | balrog | # else
|
1044 | b854bc19 | balrog | # define OMAP_8B_REG(paddr)
|
1045 | b854bc19 | balrog | # define OMAP_16B_REG(paddr)
|
1046 | b854bc19 | balrog | # define OMAP_32B_REG(paddr)
|
1047 | b854bc19 | balrog | # endif
|
1048 | c3d2689d | balrog | |
1049 | cf965d24 | balrog | # define OMAP_MPUI_REG_MASK 0x000007ff |
1050 | cf965d24 | balrog | |
1051 | d8f699cb | balrog | # ifdef MEM_VERBOSE
|
1052 | d8f699cb | balrog | struct io_fn {
|
1053 | d60efc6b | Blue Swirl | CPUReadMemoryFunc * const *mem_read;
|
1054 | d60efc6b | Blue Swirl | CPUWriteMemoryFunc * const *mem_write;
|
1055 | d8f699cb | balrog | void *opaque;
|
1056 | d8f699cb | balrog | int in;
|
1057 | d8f699cb | balrog | }; |
1058 | d8f699cb | balrog | |
1059 | c227f099 | Anthony Liguori | static uint32_t io_readb(void *opaque, target_phys_addr_t addr) |
1060 | d8f699cb | balrog | { |
1061 | d8f699cb | balrog | struct io_fn *s = opaque;
|
1062 | d8f699cb | balrog | uint32_t ret; |
1063 | d8f699cb | balrog | |
1064 | d8f699cb | balrog | s->in ++; |
1065 | d8f699cb | balrog | ret = s->mem_read[0](s->opaque, addr);
|
1066 | d8f699cb | balrog | s->in --; |
1067 | d8f699cb | balrog | if (!s->in)
|
1068 | d8f699cb | balrog | fprintf(stderr, "%08x ---> %02x\n", (uint32_t) addr, ret);
|
1069 | d8f699cb | balrog | return ret;
|
1070 | d8f699cb | balrog | } |
1071 | c227f099 | Anthony Liguori | static uint32_t io_readh(void *opaque, target_phys_addr_t addr) |
1072 | d8f699cb | balrog | { |
1073 | d8f699cb | balrog | struct io_fn *s = opaque;
|
1074 | d8f699cb | balrog | uint32_t ret; |
1075 | d8f699cb | balrog | |
1076 | d8f699cb | balrog | s->in ++; |
1077 | d8f699cb | balrog | ret = s->mem_read[1](s->opaque, addr);
|
1078 | d8f699cb | balrog | s->in --; |
1079 | d8f699cb | balrog | if (!s->in)
|
1080 | d8f699cb | balrog | fprintf(stderr, "%08x ---> %04x\n", (uint32_t) addr, ret);
|
1081 | d8f699cb | balrog | return ret;
|
1082 | d8f699cb | balrog | } |
1083 | c227f099 | Anthony Liguori | static uint32_t io_readw(void *opaque, target_phys_addr_t addr) |
1084 | d8f699cb | balrog | { |
1085 | d8f699cb | balrog | struct io_fn *s = opaque;
|
1086 | d8f699cb | balrog | uint32_t ret; |
1087 | d8f699cb | balrog | |
1088 | d8f699cb | balrog | s->in ++; |
1089 | d8f699cb | balrog | ret = s->mem_read[2](s->opaque, addr);
|
1090 | d8f699cb | balrog | s->in --; |
1091 | d8f699cb | balrog | if (!s->in)
|
1092 | d8f699cb | balrog | fprintf(stderr, "%08x ---> %08x\n", (uint32_t) addr, ret);
|
1093 | d8f699cb | balrog | return ret;
|
1094 | d8f699cb | balrog | } |
1095 | c227f099 | Anthony Liguori | static void io_writeb(void *opaque, target_phys_addr_t addr, uint32_t value) |
1096 | d8f699cb | balrog | { |
1097 | d8f699cb | balrog | struct io_fn *s = opaque;
|
1098 | d8f699cb | balrog | |
1099 | d8f699cb | balrog | if (!s->in)
|
1100 | d8f699cb | balrog | fprintf(stderr, "%08x <--- %02x\n", (uint32_t) addr, value);
|
1101 | d8f699cb | balrog | s->in ++; |
1102 | d8f699cb | balrog | s->mem_write[0](s->opaque, addr, value);
|
1103 | d8f699cb | balrog | s->in --; |
1104 | d8f699cb | balrog | } |
1105 | c227f099 | Anthony Liguori | static void io_writeh(void *opaque, target_phys_addr_t addr, uint32_t value) |
1106 | d8f699cb | balrog | { |
1107 | d8f699cb | balrog | struct io_fn *s = opaque;
|
1108 | d8f699cb | balrog | |
1109 | d8f699cb | balrog | if (!s->in)
|
1110 | d8f699cb | balrog | fprintf(stderr, "%08x <--- %04x\n", (uint32_t) addr, value);
|
1111 | d8f699cb | balrog | s->in ++; |
1112 | d8f699cb | balrog | s->mem_write[1](s->opaque, addr, value);
|
1113 | d8f699cb | balrog | s->in --; |
1114 | d8f699cb | balrog | } |
1115 | c227f099 | Anthony Liguori | static void io_writew(void *opaque, target_phys_addr_t addr, uint32_t value) |
1116 | d8f699cb | balrog | { |
1117 | d8f699cb | balrog | struct io_fn *s = opaque;
|
1118 | d8f699cb | balrog | |
1119 | d8f699cb | balrog | if (!s->in)
|
1120 | d8f699cb | balrog | fprintf(stderr, "%08x <--- %08x\n", (uint32_t) addr, value);
|
1121 | d8f699cb | balrog | s->in ++; |
1122 | d8f699cb | balrog | s->mem_write[2](s->opaque, addr, value);
|
1123 | d8f699cb | balrog | s->in --; |
1124 | d8f699cb | balrog | } |
1125 | d8f699cb | balrog | |
1126 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const io_readfn[] = { io_readb, io_readh, io_readw, }; |
1127 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const io_writefn[] = { io_writeb, io_writeh, io_writew, }; |
1128 | d8f699cb | balrog | |
1129 | d60efc6b | Blue Swirl | inline static int debug_register_io_memory(CPUReadMemoryFunc * const *mem_read, |
1130 | d60efc6b | Blue Swirl | CPUWriteMemoryFunc * const *mem_write,
|
1131 | d60efc6b | Blue Swirl | void *opaque)
|
1132 | d8f699cb | balrog | { |
1133 | d8f699cb | balrog | struct io_fn *s = qemu_malloc(sizeof(struct io_fn)); |
1134 | d8f699cb | balrog | |
1135 | d8f699cb | balrog | s->mem_read = mem_read; |
1136 | d8f699cb | balrog | s->mem_write = mem_write; |
1137 | d8f699cb | balrog | s->opaque = opaque; |
1138 | d8f699cb | balrog | s->in = 0;
|
1139 | 1eed09cb | Avi Kivity | return cpu_register_io_memory(io_readfn, io_writefn, s);
|
1140 | d8f699cb | balrog | } |
1141 | d8f699cb | balrog | # define cpu_register_io_memory debug_register_io_memory
|
1142 | d8f699cb | balrog | # endif
|
1143 | d8f699cb | balrog | |
1144 | c66fb5bc | balrog | /* Define when we want to reduce the number of IO regions registered. */
|
1145 | 477b24ef | balrog | /*# define L4_MUX_HACK*/
|
1146 | c66fb5bc | balrog | |
1147 | c66fb5bc | balrog | # ifdef L4_MUX_HACK
|
1148 | c66fb5bc | balrog | # undef l4_register_io_memory
|
1149 | d60efc6b | Blue Swirl | int l4_register_io_memory(CPUReadMemoryFunc * const *mem_read, |
1150 | d60efc6b | Blue Swirl | CPUWriteMemoryFunc * const *mem_write, void *opaque); |
1151 | c66fb5bc | balrog | # endif
|
1152 | c66fb5bc | balrog | |
1153 | c3d2689d | balrog | #endif /* hw_omap_h */ |