Revision 7f132a21
b/Makefile.target | ||
---|---|---|
268 | 268 |
obj-arm-y += pxa2xx_lcd.o pxa2xx_mmci.o pxa2xx_pcmcia.o pxa2xx_keypad.o |
269 | 269 |
obj-arm-y += gumstix.o |
270 | 270 |
obj-arm-y += zaurus.o ide/microdrive.o spitz.o tosa.o tc6393xb.o |
271 |
obj-arm-y += omap1.o omap_lcdc.o omap_dma.o omap_clk.o omap_mmc.o omap_i2c.o omap_gpio.o |
|
271 |
obj-arm-y += omap1.o omap_lcdc.o omap_dma.o omap_clk.o omap_mmc.o omap_i2c.o omap_gpio.o omap_intc.o
|
|
272 | 272 |
obj-arm-y += omap2.o omap_dss.o soc_dma.o omap_gptimer.o omap_synctimer.o omap_gpmc.o omap_sdrc.o |
273 | 273 |
obj-arm-y += omap_sx1.o palm.o tsc210x.o |
274 | 274 |
obj-arm-y += nseries.o blizzard.o onenand.o vga.o cbus.o tusb6010.o usb-musb.o |
b/hw/omap.h | ||
---|---|---|
71 | 71 |
int iotype); |
72 | 72 |
# define l4_register_io_memory cpu_register_io_memory |
73 | 73 |
|
74 |
/* OMAP interrupt controller */ |
|
74 | 75 |
struct omap_intr_handler_s; |
75 | 76 |
struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base, |
76 | 77 |
unsigned long size, unsigned char nbanks, qemu_irq **pins, |
... | ... | |
80 | 81 |
qemu_irq parent_irq, qemu_irq parent_fiq, |
81 | 82 |
omap_clk fclk, omap_clk iclk); |
82 | 83 |
void omap_inth_reset(struct omap_intr_handler_s *s); |
84 |
qemu_irq omap_inth_get_pin(struct omap_intr_handler_s *s, int n); |
|
83 | 85 |
|
84 | 86 |
struct omap_prcm_s; |
85 | 87 |
struct omap_prcm_s *omap_prcm_init(struct omap_target_agent_s *ta, |
b/hw/omap1.c | ||
---|---|---|
79 | 79 |
cpu_physical_memory_write(addr, (void *) &value, 4); |
80 | 80 |
} |
81 | 81 |
|
82 |
/* Interrupt Handlers */ |
|
83 |
struct omap_intr_handler_bank_s { |
|
84 |
uint32_t irqs; |
|
85 |
uint32_t inputs; |
|
86 |
uint32_t mask; |
|
87 |
uint32_t fiq; |
|
88 |
uint32_t sens_edge; |
|
89 |
uint32_t swi; |
|
90 |
unsigned char priority[32]; |
|
91 |
}; |
|
92 |
|
|
93 |
struct omap_intr_handler_s { |
|
94 |
qemu_irq *pins; |
|
95 |
qemu_irq parent_intr[2]; |
|
96 |
unsigned char nbanks; |
|
97 |
int level_only; |
|
98 |
|
|
99 |
/* state */ |
|
100 |
uint32_t new_agr[2]; |
|
101 |
int sir_intr[2]; |
|
102 |
int autoidle; |
|
103 |
uint32_t mask; |
|
104 |
struct omap_intr_handler_bank_s bank[]; |
|
105 |
}; |
|
106 |
|
|
107 |
static void omap_inth_sir_update(struct omap_intr_handler_s *s, int is_fiq) |
|
108 |
{ |
|
109 |
int i, j, sir_intr, p_intr, p, f; |
|
110 |
uint32_t level; |
|
111 |
sir_intr = 0; |
|
112 |
p_intr = 255; |
|
113 |
|
|
114 |
/* Find the interrupt line with the highest dynamic priority. |
|
115 |
* Note: 0 denotes the hightest priority. |
|
116 |
* If all interrupts have the same priority, the default order is IRQ_N, |
|
117 |
* IRQ_N-1,...,IRQ_0. */ |
|
118 |
for (j = 0; j < s->nbanks; ++j) { |
|
119 |
level = s->bank[j].irqs & ~s->bank[j].mask & |
|
120 |
(is_fiq ? s->bank[j].fiq : ~s->bank[j].fiq); |
|
121 |
for (f = ffs(level), i = f - 1, level >>= f - 1; f; i += f, |
|
122 |
level >>= f) { |
|
123 |
p = s->bank[j].priority[i]; |
|
124 |
if (p <= p_intr) { |
|
125 |
p_intr = p; |
|
126 |
sir_intr = 32 * j + i; |
|
127 |
} |
|
128 |
f = ffs(level >> 1); |
|
129 |
} |
|
130 |
} |
|
131 |
s->sir_intr[is_fiq] = sir_intr; |
|
132 |
} |
|
133 |
|
|
134 |
static inline void omap_inth_update(struct omap_intr_handler_s *s, int is_fiq) |
|
135 |
{ |
|
136 |
int i; |
|
137 |
uint32_t has_intr = 0; |
|
138 |
|
|
139 |
for (i = 0; i < s->nbanks; ++i) |
|
140 |
has_intr |= s->bank[i].irqs & ~s->bank[i].mask & |
|
141 |
(is_fiq ? s->bank[i].fiq : ~s->bank[i].fiq); |
|
142 |
|
|
143 |
if (s->new_agr[is_fiq] & has_intr & s->mask) { |
|
144 |
s->new_agr[is_fiq] = 0; |
|
145 |
omap_inth_sir_update(s, is_fiq); |
|
146 |
qemu_set_irq(s->parent_intr[is_fiq], 1); |
|
147 |
} |
|
148 |
} |
|
149 |
|
|
150 |
#define INT_FALLING_EDGE 0 |
|
151 |
#define INT_LOW_LEVEL 1 |
|
152 |
|
|
153 |
static void omap_set_intr(void *opaque, int irq, int req) |
|
154 |
{ |
|
155 |
struct omap_intr_handler_s *ih = (struct omap_intr_handler_s *) opaque; |
|
156 |
uint32_t rise; |
|
157 |
|
|
158 |
struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5]; |
|
159 |
int n = irq & 31; |
|
160 |
|
|
161 |
if (req) { |
|
162 |
rise = ~bank->irqs & (1 << n); |
|
163 |
if (~bank->sens_edge & (1 << n)) |
|
164 |
rise &= ~bank->inputs; |
|
165 |
|
|
166 |
bank->inputs |= (1 << n); |
|
167 |
if (rise) { |
|
168 |
bank->irqs |= rise; |
|
169 |
omap_inth_update(ih, 0); |
|
170 |
omap_inth_update(ih, 1); |
|
171 |
} |
|
172 |
} else { |
|
173 |
rise = bank->sens_edge & bank->irqs & (1 << n); |
|
174 |
bank->irqs &= ~rise; |
|
175 |
bank->inputs &= ~(1 << n); |
|
176 |
} |
|
177 |
} |
|
178 |
|
|
179 |
/* Simplified version with no edge detection */ |
|
180 |
static void omap_set_intr_noedge(void *opaque, int irq, int req) |
|
181 |
{ |
|
182 |
struct omap_intr_handler_s *ih = (struct omap_intr_handler_s *) opaque; |
|
183 |
uint32_t rise; |
|
184 |
|
|
185 |
struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5]; |
|
186 |
int n = irq & 31; |
|
187 |
|
|
188 |
if (req) { |
|
189 |
rise = ~bank->inputs & (1 << n); |
|
190 |
if (rise) { |
|
191 |
bank->irqs |= bank->inputs |= rise; |
|
192 |
omap_inth_update(ih, 0); |
|
193 |
omap_inth_update(ih, 1); |
|
194 |
} |
|
195 |
} else |
|
196 |
bank->irqs = (bank->inputs &= ~(1 << n)) | bank->swi; |
|
197 |
} |
|
198 |
|
|
199 |
static uint32_t omap_inth_read(void *opaque, target_phys_addr_t addr) |
|
200 |
{ |
|
201 |
struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque; |
|
202 |
int i, offset = addr; |
|
203 |
int bank_no = offset >> 8; |
|
204 |
int line_no; |
|
205 |
struct omap_intr_handler_bank_s *bank = &s->bank[bank_no]; |
|
206 |
offset &= 0xff; |
|
207 |
|
|
208 |
switch (offset) { |
|
209 |
case 0x00: /* ITR */ |
|
210 |
return bank->irqs; |
|
211 |
|
|
212 |
case 0x04: /* MIR */ |
|
213 |
return bank->mask; |
|
214 |
|
|
215 |
case 0x10: /* SIR_IRQ_CODE */ |
|
216 |
case 0x14: /* SIR_FIQ_CODE */ |
|
217 |
if (bank_no != 0) |
|
218 |
break; |
|
219 |
line_no = s->sir_intr[(offset - 0x10) >> 2]; |
|
220 |
bank = &s->bank[line_no >> 5]; |
|
221 |
i = line_no & 31; |
|
222 |
if (((bank->sens_edge >> i) & 1) == INT_FALLING_EDGE) |
|
223 |
bank->irqs &= ~(1 << i); |
|
224 |
return line_no; |
|
225 |
|
|
226 |
case 0x18: /* CONTROL_REG */ |
|
227 |
if (bank_no != 0) |
|
228 |
break; |
|
229 |
return 0; |
|
230 |
|
|
231 |
case 0x1c: /* ILR0 */ |
|
232 |
case 0x20: /* ILR1 */ |
|
233 |
case 0x24: /* ILR2 */ |
|
234 |
case 0x28: /* ILR3 */ |
|
235 |
case 0x2c: /* ILR4 */ |
|
236 |
case 0x30: /* ILR5 */ |
|
237 |
case 0x34: /* ILR6 */ |
|
238 |
case 0x38: /* ILR7 */ |
|
239 |
case 0x3c: /* ILR8 */ |
|
240 |
case 0x40: /* ILR9 */ |
|
241 |
case 0x44: /* ILR10 */ |
|
242 |
case 0x48: /* ILR11 */ |
|
243 |
case 0x4c: /* ILR12 */ |
|
244 |
case 0x50: /* ILR13 */ |
|
245 |
case 0x54: /* ILR14 */ |
|
246 |
case 0x58: /* ILR15 */ |
|
247 |
case 0x5c: /* ILR16 */ |
|
248 |
case 0x60: /* ILR17 */ |
|
249 |
case 0x64: /* ILR18 */ |
|
250 |
case 0x68: /* ILR19 */ |
|
251 |
case 0x6c: /* ILR20 */ |
|
252 |
case 0x70: /* ILR21 */ |
|
253 |
case 0x74: /* ILR22 */ |
|
254 |
case 0x78: /* ILR23 */ |
|
255 |
case 0x7c: /* ILR24 */ |
|
256 |
case 0x80: /* ILR25 */ |
|
257 |
case 0x84: /* ILR26 */ |
|
258 |
case 0x88: /* ILR27 */ |
|
259 |
case 0x8c: /* ILR28 */ |
|
260 |
case 0x90: /* ILR29 */ |
|
261 |
case 0x94: /* ILR30 */ |
|
262 |
case 0x98: /* ILR31 */ |
|
263 |
i = (offset - 0x1c) >> 2; |
|
264 |
return (bank->priority[i] << 2) | |
|
265 |
(((bank->sens_edge >> i) & 1) << 1) | |
|
266 |
((bank->fiq >> i) & 1); |
|
267 |
|
|
268 |
case 0x9c: /* ISR */ |
|
269 |
return 0x00000000; |
|
270 |
|
|
271 |
} |
|
272 |
OMAP_BAD_REG(addr); |
|
273 |
return 0; |
|
274 |
} |
|
275 |
|
|
276 |
static void omap_inth_write(void *opaque, target_phys_addr_t addr, |
|
277 |
uint32_t value) |
|
278 |
{ |
|
279 |
struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque; |
|
280 |
int i, offset = addr; |
|
281 |
int bank_no = offset >> 8; |
|
282 |
struct omap_intr_handler_bank_s *bank = &s->bank[bank_no]; |
|
283 |
offset &= 0xff; |
|
284 |
|
|
285 |
switch (offset) { |
|
286 |
case 0x00: /* ITR */ |
|
287 |
/* Important: ignore the clearing if the IRQ is level-triggered and |
|
288 |
the input bit is 1 */ |
|
289 |
bank->irqs &= value | (bank->inputs & bank->sens_edge); |
|
290 |
return; |
|
291 |
|
|
292 |
case 0x04: /* MIR */ |
|
293 |
bank->mask = value; |
|
294 |
omap_inth_update(s, 0); |
|
295 |
omap_inth_update(s, 1); |
|
296 |
return; |
|
297 |
|
|
298 |
case 0x10: /* SIR_IRQ_CODE */ |
|
299 |
case 0x14: /* SIR_FIQ_CODE */ |
|
300 |
OMAP_RO_REG(addr); |
|
301 |
break; |
|
302 |
|
|
303 |
case 0x18: /* CONTROL_REG */ |
|
304 |
if (bank_no != 0) |
|
305 |
break; |
|
306 |
if (value & 2) { |
|
307 |
qemu_set_irq(s->parent_intr[1], 0); |
|
308 |
s->new_agr[1] = ~0; |
|
309 |
omap_inth_update(s, 1); |
|
310 |
} |
|
311 |
if (value & 1) { |
|
312 |
qemu_set_irq(s->parent_intr[0], 0); |
|
313 |
s->new_agr[0] = ~0; |
|
314 |
omap_inth_update(s, 0); |
|
315 |
} |
|
316 |
return; |
|
317 |
|
|
318 |
case 0x1c: /* ILR0 */ |
|
319 |
case 0x20: /* ILR1 */ |
|
320 |
case 0x24: /* ILR2 */ |
|
321 |
case 0x28: /* ILR3 */ |
|
322 |
case 0x2c: /* ILR4 */ |
|
323 |
case 0x30: /* ILR5 */ |
|
324 |
case 0x34: /* ILR6 */ |
|
325 |
case 0x38: /* ILR7 */ |
|
326 |
case 0x3c: /* ILR8 */ |
|
327 |
case 0x40: /* ILR9 */ |
|
328 |
case 0x44: /* ILR10 */ |
|
329 |
case 0x48: /* ILR11 */ |
|
330 |
case 0x4c: /* ILR12 */ |
|
331 |
case 0x50: /* ILR13 */ |
|
332 |
case 0x54: /* ILR14 */ |
|
333 |
case 0x58: /* ILR15 */ |
|
334 |
case 0x5c: /* ILR16 */ |
|
335 |
case 0x60: /* ILR17 */ |
|
336 |
case 0x64: /* ILR18 */ |
|
337 |
case 0x68: /* ILR19 */ |
|
338 |
case 0x6c: /* ILR20 */ |
|
339 |
case 0x70: /* ILR21 */ |
|
340 |
case 0x74: /* ILR22 */ |
|
341 |
case 0x78: /* ILR23 */ |
|
342 |
case 0x7c: /* ILR24 */ |
|
343 |
case 0x80: /* ILR25 */ |
|
344 |
case 0x84: /* ILR26 */ |
|
345 |
case 0x88: /* ILR27 */ |
|
346 |
case 0x8c: /* ILR28 */ |
|
347 |
case 0x90: /* ILR29 */ |
|
348 |
case 0x94: /* ILR30 */ |
|
349 |
case 0x98: /* ILR31 */ |
|
350 |
i = (offset - 0x1c) >> 2; |
|
351 |
bank->priority[i] = (value >> 2) & 0x1f; |
|
352 |
bank->sens_edge &= ~(1 << i); |
|
353 |
bank->sens_edge |= ((value >> 1) & 1) << i; |
|
354 |
bank->fiq &= ~(1 << i); |
|
355 |
bank->fiq |= (value & 1) << i; |
|
356 |
return; |
|
357 |
|
|
358 |
case 0x9c: /* ISR */ |
|
359 |
for (i = 0; i < 32; i ++) |
|
360 |
if (value & (1 << i)) { |
|
361 |
omap_set_intr(s, 32 * bank_no + i, 1); |
|
362 |
return; |
|
363 |
} |
|
364 |
return; |
|
365 |
} |
|
366 |
OMAP_BAD_REG(addr); |
|
367 |
} |
|
368 |
|
|
369 |
static CPUReadMemoryFunc * const omap_inth_readfn[] = { |
|
370 |
omap_badwidth_read32, |
|
371 |
omap_badwidth_read32, |
|
372 |
omap_inth_read, |
|
373 |
}; |
|
374 |
|
|
375 |
static CPUWriteMemoryFunc * const omap_inth_writefn[] = { |
|
376 |
omap_inth_write, |
|
377 |
omap_inth_write, |
|
378 |
omap_inth_write, |
|
379 |
}; |
|
380 |
|
|
381 |
void omap_inth_reset(struct omap_intr_handler_s *s) |
|
382 |
{ |
|
383 |
int i; |
|
384 |
|
|
385 |
for (i = 0; i < s->nbanks; ++i){ |
|
386 |
s->bank[i].irqs = 0x00000000; |
|
387 |
s->bank[i].mask = 0xffffffff; |
|
388 |
s->bank[i].sens_edge = 0x00000000; |
|
389 |
s->bank[i].fiq = 0x00000000; |
|
390 |
s->bank[i].inputs = 0x00000000; |
|
391 |
s->bank[i].swi = 0x00000000; |
|
392 |
memset(s->bank[i].priority, 0, sizeof(s->bank[i].priority)); |
|
393 |
|
|
394 |
if (s->level_only) |
|
395 |
s->bank[i].sens_edge = 0xffffffff; |
|
396 |
} |
|
397 |
|
|
398 |
s->new_agr[0] = ~0; |
|
399 |
s->new_agr[1] = ~0; |
|
400 |
s->sir_intr[0] = 0; |
|
401 |
s->sir_intr[1] = 0; |
|
402 |
s->autoidle = 0; |
|
403 |
s->mask = ~0; |
|
404 |
|
|
405 |
qemu_set_irq(s->parent_intr[0], 0); |
|
406 |
qemu_set_irq(s->parent_intr[1], 0); |
|
407 |
} |
|
408 |
|
|
409 |
struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base, |
|
410 |
unsigned long size, unsigned char nbanks, qemu_irq **pins, |
|
411 |
qemu_irq parent_irq, qemu_irq parent_fiq, omap_clk clk) |
|
412 |
{ |
|
413 |
int iomemtype; |
|
414 |
struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) |
|
415 |
qemu_mallocz(sizeof(struct omap_intr_handler_s) + |
|
416 |
sizeof(struct omap_intr_handler_bank_s) * nbanks); |
|
417 |
|
|
418 |
s->parent_intr[0] = parent_irq; |
|
419 |
s->parent_intr[1] = parent_fiq; |
|
420 |
s->nbanks = nbanks; |
|
421 |
s->pins = qemu_allocate_irqs(omap_set_intr, s, nbanks * 32); |
|
422 |
if (pins) |
|
423 |
*pins = s->pins; |
|
424 |
|
|
425 |
omap_inth_reset(s); |
|
426 |
|
|
427 |
iomemtype = cpu_register_io_memory(omap_inth_readfn, |
|
428 |
omap_inth_writefn, s); |
|
429 |
cpu_register_physical_memory(base, size, iomemtype); |
|
430 |
|
|
431 |
return s; |
|
432 |
} |
|
433 |
|
|
434 |
static uint32_t omap2_inth_read(void *opaque, target_phys_addr_t addr) |
|
435 |
{ |
|
436 |
struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque; |
|
437 |
int offset = addr; |
|
438 |
int bank_no, line_no; |
|
439 |
struct omap_intr_handler_bank_s *bank = NULL; |
|
440 |
|
|
441 |
if ((offset & 0xf80) == 0x80) { |
|
442 |
bank_no = (offset & 0x60) >> 5; |
|
443 |
if (bank_no < s->nbanks) { |
|
444 |
offset &= ~0x60; |
|
445 |
bank = &s->bank[bank_no]; |
|
446 |
} |
|
447 |
} |
|
448 |
|
|
449 |
switch (offset) { |
|
450 |
case 0x00: /* INTC_REVISION */ |
|
451 |
return 0x21; |
|
452 |
|
|
453 |
case 0x10: /* INTC_SYSCONFIG */ |
|
454 |
return (s->autoidle >> 2) & 1; |
|
455 |
|
|
456 |
case 0x14: /* INTC_SYSSTATUS */ |
|
457 |
return 1; /* RESETDONE */ |
|
458 |
|
|
459 |
case 0x40: /* INTC_SIR_IRQ */ |
|
460 |
return s->sir_intr[0]; |
|
461 |
|
|
462 |
case 0x44: /* INTC_SIR_FIQ */ |
|
463 |
return s->sir_intr[1]; |
|
464 |
|
|
465 |
case 0x48: /* INTC_CONTROL */ |
|
466 |
return (!s->mask) << 2; /* GLOBALMASK */ |
|
467 |
|
|
468 |
case 0x4c: /* INTC_PROTECTION */ |
|
469 |
return 0; |
|
470 |
|
|
471 |
case 0x50: /* INTC_IDLE */ |
|
472 |
return s->autoidle & 3; |
|
473 |
|
|
474 |
/* Per-bank registers */ |
|
475 |
case 0x80: /* INTC_ITR */ |
|
476 |
return bank->inputs; |
|
477 |
|
|
478 |
case 0x84: /* INTC_MIR */ |
|
479 |
return bank->mask; |
|
480 |
|
|
481 |
case 0x88: /* INTC_MIR_CLEAR */ |
|
482 |
case 0x8c: /* INTC_MIR_SET */ |
|
483 |
return 0; |
|
484 |
|
|
485 |
case 0x90: /* INTC_ISR_SET */ |
|
486 |
return bank->swi; |
|
487 |
|
|
488 |
case 0x94: /* INTC_ISR_CLEAR */ |
|
489 |
return 0; |
|
490 |
|
|
491 |
case 0x98: /* INTC_PENDING_IRQ */ |
|
492 |
return bank->irqs & ~bank->mask & ~bank->fiq; |
|
493 |
|
|
494 |
case 0x9c: /* INTC_PENDING_FIQ */ |
|
495 |
return bank->irqs & ~bank->mask & bank->fiq; |
|
496 |
|
|
497 |
/* Per-line registers */ |
|
498 |
case 0x100 ... 0x300: /* INTC_ILR */ |
|
499 |
bank_no = (offset - 0x100) >> 7; |
|
500 |
if (bank_no > s->nbanks) |
|
501 |
break; |
|
502 |
bank = &s->bank[bank_no]; |
|
503 |
line_no = (offset & 0x7f) >> 2; |
|
504 |
return (bank->priority[line_no] << 2) | |
|
505 |
((bank->fiq >> line_no) & 1); |
|
506 |
} |
|
507 |
OMAP_BAD_REG(addr); |
|
508 |
return 0; |
|
509 |
} |
|
510 |
|
|
511 |
static void omap2_inth_write(void *opaque, target_phys_addr_t addr, |
|
512 |
uint32_t value) |
|
513 |
{ |
|
514 |
struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque; |
|
515 |
int offset = addr; |
|
516 |
int bank_no, line_no; |
|
517 |
struct omap_intr_handler_bank_s *bank = NULL; |
|
518 |
|
|
519 |
if ((offset & 0xf80) == 0x80) { |
|
520 |
bank_no = (offset & 0x60) >> 5; |
|
521 |
if (bank_no < s->nbanks) { |
|
522 |
offset &= ~0x60; |
|
523 |
bank = &s->bank[bank_no]; |
|
524 |
} |
|
525 |
} |
|
526 |
|
|
527 |
switch (offset) { |
|
528 |
case 0x10: /* INTC_SYSCONFIG */ |
|
529 |
s->autoidle &= 4; |
|
530 |
s->autoidle |= (value & 1) << 2; |
|
531 |
if (value & 2) /* SOFTRESET */ |
|
532 |
omap_inth_reset(s); |
|
533 |
return; |
|
534 |
|
|
535 |
case 0x48: /* INTC_CONTROL */ |
|
536 |
s->mask = (value & 4) ? 0 : ~0; /* GLOBALMASK */ |
|
537 |
if (value & 2) { /* NEWFIQAGR */ |
|
538 |
qemu_set_irq(s->parent_intr[1], 0); |
|
539 |
s->new_agr[1] = ~0; |
|
540 |
omap_inth_update(s, 1); |
|
541 |
} |
|
542 |
if (value & 1) { /* NEWIRQAGR */ |
|
543 |
qemu_set_irq(s->parent_intr[0], 0); |
|
544 |
s->new_agr[0] = ~0; |
|
545 |
omap_inth_update(s, 0); |
|
546 |
} |
|
547 |
return; |
|
548 |
|
|
549 |
case 0x4c: /* INTC_PROTECTION */ |
|
550 |
/* TODO: Make a bitmap (or sizeof(char)map) of access privileges |
|
551 |
* for every register, see Chapter 3 and 4 for privileged mode. */ |
|
552 |
if (value & 1) |
|
553 |
fprintf(stderr, "%s: protection mode enable attempt\n", |
|
554 |
__FUNCTION__); |
|
555 |
return; |
|
556 |
|
|
557 |
case 0x50: /* INTC_IDLE */ |
|
558 |
s->autoidle &= ~3; |
|
559 |
s->autoidle |= value & 3; |
|
560 |
return; |
|
561 |
|
|
562 |
/* Per-bank registers */ |
|
563 |
case 0x84: /* INTC_MIR */ |
|
564 |
bank->mask = value; |
|
565 |
omap_inth_update(s, 0); |
|
566 |
omap_inth_update(s, 1); |
|
567 |
return; |
|
568 |
|
|
569 |
case 0x88: /* INTC_MIR_CLEAR */ |
|
570 |
bank->mask &= ~value; |
|
571 |
omap_inth_update(s, 0); |
|
572 |
omap_inth_update(s, 1); |
|
573 |
return; |
|
574 |
|
|
575 |
case 0x8c: /* INTC_MIR_SET */ |
|
576 |
bank->mask |= value; |
|
577 |
return; |
|
578 |
|
|
579 |
case 0x90: /* INTC_ISR_SET */ |
|
580 |
bank->irqs |= bank->swi |= value; |
|
581 |
omap_inth_update(s, 0); |
|
582 |
omap_inth_update(s, 1); |
|
583 |
return; |
|
584 |
|
|
585 |
case 0x94: /* INTC_ISR_CLEAR */ |
|
586 |
bank->swi &= ~value; |
|
587 |
bank->irqs = bank->swi & bank->inputs; |
|
588 |
return; |
|
589 |
|
|
590 |
/* Per-line registers */ |
|
591 |
case 0x100 ... 0x300: /* INTC_ILR */ |
|
592 |
bank_no = (offset - 0x100) >> 7; |
|
593 |
if (bank_no > s->nbanks) |
|
594 |
break; |
|
595 |
bank = &s->bank[bank_no]; |
|
596 |
line_no = (offset & 0x7f) >> 2; |
|
597 |
bank->priority[line_no] = (value >> 2) & 0x3f; |
|
598 |
bank->fiq &= ~(1 << line_no); |
|
599 |
bank->fiq |= (value & 1) << line_no; |
|
600 |
return; |
|
601 |
|
|
602 |
case 0x00: /* INTC_REVISION */ |
|
603 |
case 0x14: /* INTC_SYSSTATUS */ |
|
604 |
case 0x40: /* INTC_SIR_IRQ */ |
|
605 |
case 0x44: /* INTC_SIR_FIQ */ |
|
606 |
case 0x80: /* INTC_ITR */ |
|
607 |
case 0x98: /* INTC_PENDING_IRQ */ |
|
608 |
case 0x9c: /* INTC_PENDING_FIQ */ |
|
609 |
OMAP_RO_REG(addr); |
|
610 |
return; |
|
611 |
} |
|
612 |
OMAP_BAD_REG(addr); |
|
613 |
} |
|
614 |
|
|
615 |
static CPUReadMemoryFunc * const omap2_inth_readfn[] = { |
|
616 |
omap_badwidth_read32, |
|
617 |
omap_badwidth_read32, |
|
618 |
omap2_inth_read, |
|
619 |
}; |
|
620 |
|
|
621 |
static CPUWriteMemoryFunc * const omap2_inth_writefn[] = { |
|
622 |
omap2_inth_write, |
|
623 |
omap2_inth_write, |
|
624 |
omap2_inth_write, |
|
625 |
}; |
|
626 |
|
|
627 |
struct omap_intr_handler_s *omap2_inth_init(target_phys_addr_t base, |
|
628 |
int size, int nbanks, qemu_irq **pins, |
|
629 |
qemu_irq parent_irq, qemu_irq parent_fiq, |
|
630 |
omap_clk fclk, omap_clk iclk) |
|
631 |
{ |
|
632 |
int iomemtype; |
|
633 |
struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) |
|
634 |
qemu_mallocz(sizeof(struct omap_intr_handler_s) + |
|
635 |
sizeof(struct omap_intr_handler_bank_s) * nbanks); |
|
636 |
|
|
637 |
s->parent_intr[0] = parent_irq; |
|
638 |
s->parent_intr[1] = parent_fiq; |
|
639 |
s->nbanks = nbanks; |
|
640 |
s->level_only = 1; |
|
641 |
s->pins = qemu_allocate_irqs(omap_set_intr_noedge, s, nbanks * 32); |
|
642 |
if (pins) |
|
643 |
*pins = s->pins; |
|
644 |
|
|
645 |
omap_inth_reset(s); |
|
646 |
|
|
647 |
iomemtype = cpu_register_io_memory(omap2_inth_readfn, |
|
648 |
omap2_inth_writefn, s); |
|
649 |
cpu_register_physical_memory(base, size, iomemtype); |
|
650 |
|
|
651 |
return s; |
|
652 |
} |
|
653 |
|
|
654 | 82 |
/* MPU OS timers */ |
655 | 83 |
struct omap_mpu_timer_s { |
656 | 84 |
qemu_irq irq; |
... | ... | |
4485 | 3913 |
cpu_irq[ARM_PIC_CPU_IRQ], cpu_irq[ARM_PIC_CPU_FIQ], |
4486 | 3914 |
omap_findclk(s, "arminth_ck")); |
4487 | 3915 |
s->ih[1] = omap_inth_init(0xfffe0000, 0x800, 1, &s->irq[1], |
4488 |
s->ih[0]->pins[OMAP_INT_15XX_IH2_IRQ], NULL,
|
|
4489 |
omap_findclk(s, "arminth_ck"));
|
|
3916 |
omap_inth_get_pin(s->ih[0], OMAP_INT_15XX_IH2_IRQ),
|
|
3917 |
NULL, omap_findclk(s, "arminth_ck"));
|
|
4490 | 3918 |
|
4491 | 3919 |
for (i = 0; i < 6; i ++) |
4492 | 3920 |
dma_irqs[i] = |
b/hw/omap_intc.c | ||
---|---|---|
1 |
/* |
|
2 |
* TI OMAP interrupt controller emulation. |
|
3 |
* |
|
4 |
* Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org> |
|
5 |
* Copyright (C) 2007-2008 Nokia Corporation |
|
6 |
* |
|
7 |
* This program is free software; you can redistribute it and/or |
|
8 |
* modify it under the terms of the GNU General Public License as |
|
9 |
* published by the Free Software Foundation; either version 2 or |
|
10 |
* (at your option) version 3 of the License. |
|
11 |
* |
|
12 |
* This program is distributed in the hope that it will be useful, |
|
13 |
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
14 |
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
15 |
* GNU General Public License for more details. |
|
16 |
* |
|
17 |
* You should have received a copy of the GNU General Public License along |
|
18 |
* with this program; if not, see <http://www.gnu.org/licenses/>. |
|
19 |
*/ |
|
20 |
#include "hw.h" |
|
21 |
#include "omap.h" |
|
22 |
|
|
23 |
/* Interrupt Handlers */ |
|
24 |
struct omap_intr_handler_bank_s { |
|
25 |
uint32_t irqs; |
|
26 |
uint32_t inputs; |
|
27 |
uint32_t mask; |
|
28 |
uint32_t fiq; |
|
29 |
uint32_t sens_edge; |
|
30 |
uint32_t swi; |
|
31 |
unsigned char priority[32]; |
|
32 |
}; |
|
33 |
|
|
34 |
struct omap_intr_handler_s { |
|
35 |
qemu_irq *pins; |
|
36 |
qemu_irq parent_intr[2]; |
|
37 |
unsigned char nbanks; |
|
38 |
int level_only; |
|
39 |
|
|
40 |
/* state */ |
|
41 |
uint32_t new_agr[2]; |
|
42 |
int sir_intr[2]; |
|
43 |
int autoidle; |
|
44 |
uint32_t mask; |
|
45 |
struct omap_intr_handler_bank_s bank[]; |
|
46 |
}; |
|
47 |
|
|
48 |
inline qemu_irq omap_inth_get_pin(struct omap_intr_handler_s *s, int n) |
|
49 |
{ |
|
50 |
return s->pins[n]; |
|
51 |
} |
|
52 |
|
|
53 |
static void omap_inth_sir_update(struct omap_intr_handler_s *s, int is_fiq) |
|
54 |
{ |
|
55 |
int i, j, sir_intr, p_intr, p, f; |
|
56 |
uint32_t level; |
|
57 |
sir_intr = 0; |
|
58 |
p_intr = 255; |
|
59 |
|
|
60 |
/* Find the interrupt line with the highest dynamic priority. |
|
61 |
* Note: 0 denotes the hightest priority. |
|
62 |
* If all interrupts have the same priority, the default order is IRQ_N, |
|
63 |
* IRQ_N-1,...,IRQ_0. */ |
|
64 |
for (j = 0; j < s->nbanks; ++j) { |
|
65 |
level = s->bank[j].irqs & ~s->bank[j].mask & |
|
66 |
(is_fiq ? s->bank[j].fiq : ~s->bank[j].fiq); |
|
67 |
for (f = ffs(level), i = f - 1, level >>= f - 1; f; i += f, |
|
68 |
level >>= f) { |
|
69 |
p = s->bank[j].priority[i]; |
|
70 |
if (p <= p_intr) { |
|
71 |
p_intr = p; |
|
72 |
sir_intr = 32 * j + i; |
|
73 |
} |
|
74 |
f = ffs(level >> 1); |
|
75 |
} |
|
76 |
} |
|
77 |
s->sir_intr[is_fiq] = sir_intr; |
|
78 |
} |
|
79 |
|
|
80 |
static inline void omap_inth_update(struct omap_intr_handler_s *s, int is_fiq) |
|
81 |
{ |
|
82 |
int i; |
|
83 |
uint32_t has_intr = 0; |
|
84 |
|
|
85 |
for (i = 0; i < s->nbanks; ++i) |
|
86 |
has_intr |= s->bank[i].irqs & ~s->bank[i].mask & |
|
87 |
(is_fiq ? s->bank[i].fiq : ~s->bank[i].fiq); |
|
88 |
|
|
89 |
if (s->new_agr[is_fiq] & has_intr & s->mask) { |
|
90 |
s->new_agr[is_fiq] = 0; |
|
91 |
omap_inth_sir_update(s, is_fiq); |
|
92 |
qemu_set_irq(s->parent_intr[is_fiq], 1); |
|
93 |
} |
|
94 |
} |
|
95 |
|
|
96 |
#define INT_FALLING_EDGE 0 |
|
97 |
#define INT_LOW_LEVEL 1 |
|
98 |
|
|
99 |
static void omap_set_intr(void *opaque, int irq, int req) |
|
100 |
{ |
|
101 |
struct omap_intr_handler_s *ih = (struct omap_intr_handler_s *) opaque; |
|
102 |
uint32_t rise; |
|
103 |
|
|
104 |
struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5]; |
|
105 |
int n = irq & 31; |
|
106 |
|
|
107 |
if (req) { |
|
108 |
rise = ~bank->irqs & (1 << n); |
|
109 |
if (~bank->sens_edge & (1 << n)) |
|
110 |
rise &= ~bank->inputs; |
|
111 |
|
|
112 |
bank->inputs |= (1 << n); |
|
113 |
if (rise) { |
|
114 |
bank->irqs |= rise; |
|
115 |
omap_inth_update(ih, 0); |
|
116 |
omap_inth_update(ih, 1); |
|
117 |
} |
|
118 |
} else { |
|
119 |
rise = bank->sens_edge & bank->irqs & (1 << n); |
|
120 |
bank->irqs &= ~rise; |
|
121 |
bank->inputs &= ~(1 << n); |
|
122 |
} |
|
123 |
} |
|
124 |
|
|
125 |
/* Simplified version with no edge detection */ |
|
126 |
static void omap_set_intr_noedge(void *opaque, int irq, int req) |
|
127 |
{ |
|
128 |
struct omap_intr_handler_s *ih = (struct omap_intr_handler_s *) opaque; |
|
129 |
uint32_t rise; |
|
130 |
|
|
131 |
struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5]; |
|
132 |
int n = irq & 31; |
|
133 |
|
|
134 |
if (req) { |
|
135 |
rise = ~bank->inputs & (1 << n); |
|
136 |
if (rise) { |
|
137 |
bank->irqs |= bank->inputs |= rise; |
|
138 |
omap_inth_update(ih, 0); |
|
139 |
omap_inth_update(ih, 1); |
|
140 |
} |
|
141 |
} else |
|
142 |
bank->irqs = (bank->inputs &= ~(1 << n)) | bank->swi; |
|
143 |
} |
|
144 |
|
|
145 |
static uint32_t omap_inth_read(void *opaque, target_phys_addr_t addr) |
|
146 |
{ |
|
147 |
struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque; |
|
148 |
int i, offset = addr; |
|
149 |
int bank_no = offset >> 8; |
|
150 |
int line_no; |
|
151 |
struct omap_intr_handler_bank_s *bank = &s->bank[bank_no]; |
|
152 |
offset &= 0xff; |
|
153 |
|
|
154 |
switch (offset) { |
|
155 |
case 0x00: /* ITR */ |
|
156 |
return bank->irqs; |
|
157 |
|
|
158 |
case 0x04: /* MIR */ |
|
159 |
return bank->mask; |
|
160 |
|
|
161 |
case 0x10: /* SIR_IRQ_CODE */ |
|
162 |
case 0x14: /* SIR_FIQ_CODE */ |
|
163 |
if (bank_no != 0) |
|
164 |
break; |
|
165 |
line_no = s->sir_intr[(offset - 0x10) >> 2]; |
|
166 |
bank = &s->bank[line_no >> 5]; |
|
167 |
i = line_no & 31; |
|
168 |
if (((bank->sens_edge >> i) & 1) == INT_FALLING_EDGE) |
|
169 |
bank->irqs &= ~(1 << i); |
|
170 |
return line_no; |
|
171 |
|
|
172 |
case 0x18: /* CONTROL_REG */ |
|
173 |
if (bank_no != 0) |
|
174 |
break; |
|
175 |
return 0; |
|
176 |
|
|
177 |
case 0x1c: /* ILR0 */ |
|
178 |
case 0x20: /* ILR1 */ |
|
179 |
case 0x24: /* ILR2 */ |
|
180 |
case 0x28: /* ILR3 */ |
|
181 |
case 0x2c: /* ILR4 */ |
|
182 |
case 0x30: /* ILR5 */ |
|
183 |
case 0x34: /* ILR6 */ |
|
184 |
case 0x38: /* ILR7 */ |
|
185 |
case 0x3c: /* ILR8 */ |
|
186 |
case 0x40: /* ILR9 */ |
|
187 |
case 0x44: /* ILR10 */ |
|
188 |
case 0x48: /* ILR11 */ |
|
189 |
case 0x4c: /* ILR12 */ |
|
190 |
case 0x50: /* ILR13 */ |
|
191 |
case 0x54: /* ILR14 */ |
|
192 |
case 0x58: /* ILR15 */ |
|
193 |
case 0x5c: /* ILR16 */ |
|
194 |
case 0x60: /* ILR17 */ |
|
195 |
case 0x64: /* ILR18 */ |
|
196 |
case 0x68: /* ILR19 */ |
|
197 |
case 0x6c: /* ILR20 */ |
|
198 |
case 0x70: /* ILR21 */ |
|
199 |
case 0x74: /* ILR22 */ |
|
200 |
case 0x78: /* ILR23 */ |
|
201 |
case 0x7c: /* ILR24 */ |
|
202 |
case 0x80: /* ILR25 */ |
|
203 |
case 0x84: /* ILR26 */ |
|
204 |
case 0x88: /* ILR27 */ |
|
205 |
case 0x8c: /* ILR28 */ |
|
206 |
case 0x90: /* ILR29 */ |
|
207 |
case 0x94: /* ILR30 */ |
|
208 |
case 0x98: /* ILR31 */ |
|
209 |
i = (offset - 0x1c) >> 2; |
|
210 |
return (bank->priority[i] << 2) | |
|
211 |
(((bank->sens_edge >> i) & 1) << 1) | |
|
212 |
((bank->fiq >> i) & 1); |
|
213 |
|
|
214 |
case 0x9c: /* ISR */ |
|
215 |
return 0x00000000; |
|
216 |
|
|
217 |
} |
|
218 |
OMAP_BAD_REG(addr); |
|
219 |
return 0; |
|
220 |
} |
|
221 |
|
|
222 |
static void omap_inth_write(void *opaque, target_phys_addr_t addr, |
|
223 |
uint32_t value) |
|
224 |
{ |
|
225 |
struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque; |
|
226 |
int i, offset = addr; |
|
227 |
int bank_no = offset >> 8; |
|
228 |
struct omap_intr_handler_bank_s *bank = &s->bank[bank_no]; |
|
229 |
offset &= 0xff; |
|
230 |
|
|
231 |
switch (offset) { |
|
232 |
case 0x00: /* ITR */ |
|
233 |
/* Important: ignore the clearing if the IRQ is level-triggered and |
|
234 |
the input bit is 1 */ |
|
235 |
bank->irqs &= value | (bank->inputs & bank->sens_edge); |
|
236 |
return; |
|
237 |
|
|
238 |
case 0x04: /* MIR */ |
|
239 |
bank->mask = value; |
|
240 |
omap_inth_update(s, 0); |
|
241 |
omap_inth_update(s, 1); |
|
242 |
return; |
|
243 |
|
|
244 |
case 0x10: /* SIR_IRQ_CODE */ |
|
245 |
case 0x14: /* SIR_FIQ_CODE */ |
|
246 |
OMAP_RO_REG(addr); |
|
247 |
break; |
|
248 |
|
|
249 |
case 0x18: /* CONTROL_REG */ |
|
250 |
if (bank_no != 0) |
|
251 |
break; |
|
252 |
if (value & 2) { |
|
253 |
qemu_set_irq(s->parent_intr[1], 0); |
|
254 |
s->new_agr[1] = ~0; |
|
255 |
omap_inth_update(s, 1); |
|
256 |
} |
|
257 |
if (value & 1) { |
|
258 |
qemu_set_irq(s->parent_intr[0], 0); |
|
259 |
s->new_agr[0] = ~0; |
|
260 |
omap_inth_update(s, 0); |
|
261 |
} |
|
262 |
return; |
|
263 |
|
|
264 |
case 0x1c: /* ILR0 */ |
|
265 |
case 0x20: /* ILR1 */ |
|
266 |
case 0x24: /* ILR2 */ |
|
267 |
case 0x28: /* ILR3 */ |
|
268 |
case 0x2c: /* ILR4 */ |
|
269 |
case 0x30: /* ILR5 */ |
|
270 |
case 0x34: /* ILR6 */ |
|
271 |
case 0x38: /* ILR7 */ |
|
272 |
case 0x3c: /* ILR8 */ |
|
273 |
case 0x40: /* ILR9 */ |
|
274 |
case 0x44: /* ILR10 */ |
|
275 |
case 0x48: /* ILR11 */ |
|
276 |
case 0x4c: /* ILR12 */ |
|
277 |
case 0x50: /* ILR13 */ |
|
278 |
case 0x54: /* ILR14 */ |
|
279 |
case 0x58: /* ILR15 */ |
|
280 |
case 0x5c: /* ILR16 */ |
|
281 |
case 0x60: /* ILR17 */ |
|
282 |
case 0x64: /* ILR18 */ |
|
283 |
case 0x68: /* ILR19 */ |
|
284 |
case 0x6c: /* ILR20 */ |
|
285 |
case 0x70: /* ILR21 */ |
|
286 |
case 0x74: /* ILR22 */ |
|
287 |
case 0x78: /* ILR23 */ |
|
288 |
case 0x7c: /* ILR24 */ |
|
289 |
case 0x80: /* ILR25 */ |
|
290 |
case 0x84: /* ILR26 */ |
|
291 |
case 0x88: /* ILR27 */ |
|
292 |
case 0x8c: /* ILR28 */ |
|
293 |
case 0x90: /* ILR29 */ |
|
294 |
case 0x94: /* ILR30 */ |
|
295 |
case 0x98: /* ILR31 */ |
|
296 |
i = (offset - 0x1c) >> 2; |
|
297 |
bank->priority[i] = (value >> 2) & 0x1f; |
|
298 |
bank->sens_edge &= ~(1 << i); |
|
299 |
bank->sens_edge |= ((value >> 1) & 1) << i; |
|
300 |
bank->fiq &= ~(1 << i); |
|
301 |
bank->fiq |= (value & 1) << i; |
|
302 |
return; |
|
303 |
|
|
304 |
case 0x9c: /* ISR */ |
|
305 |
for (i = 0; i < 32; i ++) |
|
306 |
if (value & (1 << i)) { |
|
307 |
omap_set_intr(s, 32 * bank_no + i, 1); |
|
308 |
return; |
|
309 |
} |
|
310 |
return; |
|
311 |
} |
|
312 |
OMAP_BAD_REG(addr); |
|
313 |
} |
|
314 |
|
|
315 |
static CPUReadMemoryFunc * const omap_inth_readfn[] = { |
|
316 |
omap_badwidth_read32, |
|
317 |
omap_badwidth_read32, |
|
318 |
omap_inth_read, |
|
319 |
}; |
|
320 |
|
|
321 |
static CPUWriteMemoryFunc * const omap_inth_writefn[] = { |
|
322 |
omap_inth_write, |
|
323 |
omap_inth_write, |
|
324 |
omap_inth_write, |
|
325 |
}; |
|
326 |
|
|
327 |
void omap_inth_reset(struct omap_intr_handler_s *s) |
|
328 |
{ |
|
329 |
int i; |
|
330 |
|
|
331 |
for (i = 0; i < s->nbanks; ++i){ |
|
332 |
s->bank[i].irqs = 0x00000000; |
|
333 |
s->bank[i].mask = 0xffffffff; |
|
334 |
s->bank[i].sens_edge = 0x00000000; |
|
335 |
s->bank[i].fiq = 0x00000000; |
|
336 |
s->bank[i].inputs = 0x00000000; |
|
337 |
s->bank[i].swi = 0x00000000; |
|
338 |
memset(s->bank[i].priority, 0, sizeof(s->bank[i].priority)); |
|
339 |
|
|
340 |
if (s->level_only) |
|
341 |
s->bank[i].sens_edge = 0xffffffff; |
|
342 |
} |
|
343 |
|
|
344 |
s->new_agr[0] = ~0; |
|
345 |
s->new_agr[1] = ~0; |
|
346 |
s->sir_intr[0] = 0; |
|
347 |
s->sir_intr[1] = 0; |
|
348 |
s->autoidle = 0; |
|
349 |
s->mask = ~0; |
|
350 |
|
|
351 |
qemu_set_irq(s->parent_intr[0], 0); |
|
352 |
qemu_set_irq(s->parent_intr[1], 0); |
|
353 |
} |
|
354 |
|
|
355 |
struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base, |
|
356 |
unsigned long size, unsigned char nbanks, qemu_irq **pins, |
|
357 |
qemu_irq parent_irq, qemu_irq parent_fiq, omap_clk clk) |
|
358 |
{ |
|
359 |
int iomemtype; |
|
360 |
struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) |
|
361 |
qemu_mallocz(sizeof(struct omap_intr_handler_s) + |
|
362 |
sizeof(struct omap_intr_handler_bank_s) * nbanks); |
|
363 |
|
|
364 |
s->parent_intr[0] = parent_irq; |
|
365 |
s->parent_intr[1] = parent_fiq; |
|
366 |
s->nbanks = nbanks; |
|
367 |
s->pins = qemu_allocate_irqs(omap_set_intr, s, nbanks * 32); |
|
368 |
if (pins) |
|
369 |
*pins = s->pins; |
|
370 |
|
|
371 |
omap_inth_reset(s); |
|
372 |
|
|
373 |
iomemtype = cpu_register_io_memory(omap_inth_readfn, |
|
374 |
omap_inth_writefn, s); |
|
375 |
cpu_register_physical_memory(base, size, iomemtype); |
|
376 |
|
|
377 |
return s; |
|
378 |
} |
|
379 |
|
|
380 |
static uint32_t omap2_inth_read(void *opaque, target_phys_addr_t addr) |
|
381 |
{ |
|
382 |
struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque; |
|
383 |
int offset = addr; |
|
384 |
int bank_no, line_no; |
|
385 |
struct omap_intr_handler_bank_s *bank = NULL; |
|
386 |
|
|
387 |
if ((offset & 0xf80) == 0x80) { |
|
388 |
bank_no = (offset & 0x60) >> 5; |
|
389 |
if (bank_no < s->nbanks) { |
|
390 |
offset &= ~0x60; |
|
391 |
bank = &s->bank[bank_no]; |
|
392 |
} |
|
393 |
} |
|
394 |
|
|
395 |
switch (offset) { |
|
396 |
case 0x00: /* INTC_REVISION */ |
|
397 |
return 0x21; |
|
398 |
|
|
399 |
case 0x10: /* INTC_SYSCONFIG */ |
|
400 |
return (s->autoidle >> 2) & 1; |
|
401 |
|
|
402 |
case 0x14: /* INTC_SYSSTATUS */ |
|
403 |
return 1; /* RESETDONE */ |
|
404 |
|
|
405 |
case 0x40: /* INTC_SIR_IRQ */ |
|
406 |
return s->sir_intr[0]; |
|
407 |
|
|
408 |
case 0x44: /* INTC_SIR_FIQ */ |
|
409 |
return s->sir_intr[1]; |
|
410 |
|
|
411 |
case 0x48: /* INTC_CONTROL */ |
|
412 |
return (!s->mask) << 2; /* GLOBALMASK */ |
|
413 |
|
|
414 |
case 0x4c: /* INTC_PROTECTION */ |
|
415 |
return 0; |
|
416 |
|
|
417 |
case 0x50: /* INTC_IDLE */ |
|
418 |
return s->autoidle & 3; |
|
419 |
|
|
420 |
/* Per-bank registers */ |
|
421 |
case 0x80: /* INTC_ITR */ |
|
422 |
return bank->inputs; |
|
423 |
|
|
424 |
case 0x84: /* INTC_MIR */ |
|
425 |
return bank->mask; |
|
426 |
|
|
427 |
case 0x88: /* INTC_MIR_CLEAR */ |
|
428 |
case 0x8c: /* INTC_MIR_SET */ |
|
429 |
return 0; |
|
430 |
|
|
431 |
case 0x90: /* INTC_ISR_SET */ |
|
432 |
return bank->swi; |
|
433 |
|
|
434 |
case 0x94: /* INTC_ISR_CLEAR */ |
|
435 |
return 0; |
|
436 |
|
|
437 |
case 0x98: /* INTC_PENDING_IRQ */ |
|
438 |
return bank->irqs & ~bank->mask & ~bank->fiq; |
|
439 |
|
|
440 |
case 0x9c: /* INTC_PENDING_FIQ */ |
|
441 |
return bank->irqs & ~bank->mask & bank->fiq; |
|
442 |
|
|
443 |
/* Per-line registers */ |
|
444 |
case 0x100 ... 0x300: /* INTC_ILR */ |
|
445 |
bank_no = (offset - 0x100) >> 7; |
|
446 |
if (bank_no > s->nbanks) |
|
447 |
break; |
|
448 |
bank = &s->bank[bank_no]; |
|
449 |
line_no = (offset & 0x7f) >> 2; |
|
450 |
return (bank->priority[line_no] << 2) | |
|
451 |
((bank->fiq >> line_no) & 1); |
|
452 |
} |
|
453 |
OMAP_BAD_REG(addr); |
|
454 |
return 0; |
|
455 |
} |
|
456 |
|
|
457 |
static void omap2_inth_write(void *opaque, target_phys_addr_t addr, |
|
458 |
uint32_t value) |
|
459 |
{ |
|
460 |
struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque; |
|
461 |
int offset = addr; |
|
462 |
int bank_no, line_no; |
|
463 |
struct omap_intr_handler_bank_s *bank = NULL; |
|
464 |
|
|
465 |
if ((offset & 0xf80) == 0x80) { |
|
466 |
bank_no = (offset & 0x60) >> 5; |
|
467 |
if (bank_no < s->nbanks) { |
|
468 |
offset &= ~0x60; |
|
469 |
bank = &s->bank[bank_no]; |
|
470 |
} |
|
471 |
} |
|
472 |
|
|
473 |
switch (offset) { |
|
474 |
case 0x10: /* INTC_SYSCONFIG */ |
|
475 |
s->autoidle &= 4; |
|
476 |
s->autoidle |= (value & 1) << 2; |
|
477 |
if (value & 2) /* SOFTRESET */ |
|
478 |
omap_inth_reset(s); |
|
479 |
return; |
|
480 |
|
|
481 |
case 0x48: /* INTC_CONTROL */ |
|
482 |
s->mask = (value & 4) ? 0 : ~0; /* GLOBALMASK */ |
|
483 |
if (value & 2) { /* NEWFIQAGR */ |
|
484 |
qemu_set_irq(s->parent_intr[1], 0); |
|
485 |
s->new_agr[1] = ~0; |
|
486 |
omap_inth_update(s, 1); |
|
487 |
} |
|
488 |
if (value & 1) { /* NEWIRQAGR */ |
|
489 |
qemu_set_irq(s->parent_intr[0], 0); |
|
490 |
s->new_agr[0] = ~0; |
|
491 |
omap_inth_update(s, 0); |
|
492 |
} |
|
493 |
return; |
|
494 |
|
|
495 |
case 0x4c: /* INTC_PROTECTION */ |
|
496 |
/* TODO: Make a bitmap (or sizeof(char)map) of access privileges |
|
497 |
* for every register, see Chapter 3 and 4 for privileged mode. */ |
|
498 |
if (value & 1) |
|
499 |
fprintf(stderr, "%s: protection mode enable attempt\n", |
|
500 |
__FUNCTION__); |
|
501 |
return; |
|
502 |
|
|
503 |
case 0x50: /* INTC_IDLE */ |
|
504 |
s->autoidle &= ~3; |
|
505 |
s->autoidle |= value & 3; |
|
506 |
return; |
|
507 |
|
|
508 |
/* Per-bank registers */ |
|
509 |
case 0x84: /* INTC_MIR */ |
|
510 |
bank->mask = value; |
|
511 |
omap_inth_update(s, 0); |
|
512 |
omap_inth_update(s, 1); |
|
513 |
return; |
|
514 |
|
|
515 |
case 0x88: /* INTC_MIR_CLEAR */ |
|
516 |
bank->mask &= ~value; |
|
517 |
omap_inth_update(s, 0); |
|
518 |
omap_inth_update(s, 1); |
|
519 |
return; |
|
520 |
|
|
521 |
case 0x8c: /* INTC_MIR_SET */ |
|
522 |
bank->mask |= value; |
|
523 |
return; |
|
524 |
|
|
525 |
case 0x90: /* INTC_ISR_SET */ |
|
526 |
bank->irqs |= bank->swi |= value; |
|
527 |
omap_inth_update(s, 0); |
|
528 |
omap_inth_update(s, 1); |
|
529 |
return; |
|
530 |
|
|
531 |
case 0x94: /* INTC_ISR_CLEAR */ |
|
532 |
bank->swi &= ~value; |
|
533 |
bank->irqs = bank->swi & bank->inputs; |
|
534 |
return; |
|
535 |
|
|
536 |
/* Per-line registers */ |
|
537 |
case 0x100 ... 0x300: /* INTC_ILR */ |
|
538 |
bank_no = (offset - 0x100) >> 7; |
|
539 |
if (bank_no > s->nbanks) |
|
540 |
break; |
|
541 |
bank = &s->bank[bank_no]; |
|
542 |
line_no = (offset & 0x7f) >> 2; |
|
543 |
bank->priority[line_no] = (value >> 2) & 0x3f; |
|
544 |
bank->fiq &= ~(1 << line_no); |
|
545 |
bank->fiq |= (value & 1) << line_no; |
|
546 |
return; |
|
547 |
|
|
548 |
case 0x00: /* INTC_REVISION */ |
|
549 |
case 0x14: /* INTC_SYSSTATUS */ |
|
550 |
case 0x40: /* INTC_SIR_IRQ */ |
|
551 |
case 0x44: /* INTC_SIR_FIQ */ |
|
552 |
case 0x80: /* INTC_ITR */ |
|
553 |
case 0x98: /* INTC_PENDING_IRQ */ |
|
554 |
case 0x9c: /* INTC_PENDING_FIQ */ |
|
555 |
OMAP_RO_REG(addr); |
|
556 |
return; |
|
557 |
} |
|
558 |
OMAP_BAD_REG(addr); |
|
559 |
} |
|
560 |
|
|
561 |
static CPUReadMemoryFunc * const omap2_inth_readfn[] = { |
|
562 |
omap_badwidth_read32, |
|
563 |
omap_badwidth_read32, |
|
564 |
omap2_inth_read, |
|
565 |
}; |
|
566 |
|
|
567 |
static CPUWriteMemoryFunc * const omap2_inth_writefn[] = { |
|
568 |
omap2_inth_write, |
|
569 |
omap2_inth_write, |
|
570 |
omap2_inth_write, |
|
571 |
}; |
|
572 |
|
|
573 |
struct omap_intr_handler_s *omap2_inth_init(target_phys_addr_t base, |
|
574 |
int size, int nbanks, qemu_irq **pins, |
|
575 |
qemu_irq parent_irq, qemu_irq parent_fiq, |
|
576 |
omap_clk fclk, omap_clk iclk) |
|
577 |
{ |
|
578 |
int iomemtype; |
|
579 |
struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) |
|
580 |
qemu_mallocz(sizeof(struct omap_intr_handler_s) + |
|
581 |
sizeof(struct omap_intr_handler_bank_s) * nbanks); |
|
582 |
|
|
583 |
s->parent_intr[0] = parent_irq; |
|
584 |
s->parent_intr[1] = parent_fiq; |
|
585 |
s->nbanks = nbanks; |
|
586 |
s->level_only = 1; |
|
587 |
s->pins = qemu_allocate_irqs(omap_set_intr_noedge, s, nbanks * 32); |
|
588 |
if (pins) |
|
589 |
*pins = s->pins; |
|
590 |
|
|
591 |
omap_inth_reset(s); |
|
592 |
|
|
593 |
iomemtype = cpu_register_io_memory(omap2_inth_readfn, |
|
594 |
omap2_inth_writefn, s); |
|
595 |
cpu_register_physical_memory(base, size, iomemtype); |
|
596 |
|
|
597 |
return s; |
|
598 |
} |
Also available in: Unified diff