root / target-arm / machine.c @ 7f23f812
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1 | 8dd3dca3 | aurel32 | #include "hw/hw.h" |
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2 | 8dd3dca3 | aurel32 | #include "hw/boards.h" |
3 | 8dd3dca3 | aurel32 | |
4 | 8dd3dca3 | aurel32 | void cpu_save(QEMUFile *f, void *opaque) |
5 | 8dd3dca3 | aurel32 | { |
6 | 8dd3dca3 | aurel32 | int i;
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7 | 8dd3dca3 | aurel32 | CPUARMState *env = (CPUARMState *)opaque; |
8 | 8dd3dca3 | aurel32 | |
9 | 8dd3dca3 | aurel32 | for (i = 0; i < 16; i++) { |
10 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->regs[i]); |
11 | 8dd3dca3 | aurel32 | } |
12 | 8dd3dca3 | aurel32 | qemu_put_be32(f, cpsr_read(env)); |
13 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->spsr); |
14 | 8dd3dca3 | aurel32 | for (i = 0; i < 6; i++) { |
15 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->banked_spsr[i]); |
16 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->banked_r13[i]); |
17 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->banked_r14[i]); |
18 | 8dd3dca3 | aurel32 | } |
19 | 8dd3dca3 | aurel32 | for (i = 0; i < 5; i++) { |
20 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->usr_regs[i]); |
21 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->fiq_regs[i]); |
22 | 8dd3dca3 | aurel32 | } |
23 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c0_cpuid); |
24 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c0_cachetype); |
25 | ffe47d33 | Paul Brook | qemu_put_be32(f, env->cp15.c0_cssel); |
26 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c1_sys); |
27 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c1_coproc); |
28 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c1_xscaleauxcr); |
29 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c2_base0); |
30 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c2_base1); |
31 | ffe47d33 | Paul Brook | qemu_put_be32(f, env->cp15.c2_control); |
32 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c2_mask); |
33 | ffe47d33 | Paul Brook | qemu_put_be32(f, env->cp15.c2_base_mask); |
34 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c2_data); |
35 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c2_insn); |
36 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c3); |
37 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c5_insn); |
38 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c5_data); |
39 | 8dd3dca3 | aurel32 | for (i = 0; i < 8; i++) { |
40 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c6_region[i]); |
41 | 8dd3dca3 | aurel32 | } |
42 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c6_insn); |
43 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c6_data); |
44 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c9_insn); |
45 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c9_data); |
46 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c13_fcse); |
47 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c13_context); |
48 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c13_tls1); |
49 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c13_tls2); |
50 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c13_tls3); |
51 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c15_cpar); |
52 | 8dd3dca3 | aurel32 | |
53 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->features); |
54 | 8dd3dca3 | aurel32 | |
55 | 8dd3dca3 | aurel32 | if (arm_feature(env, ARM_FEATURE_VFP)) {
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56 | 8dd3dca3 | aurel32 | for (i = 0; i < 16; i++) { |
57 | 8dd3dca3 | aurel32 | CPU_DoubleU u; |
58 | 8dd3dca3 | aurel32 | u.d = env->vfp.regs[i]; |
59 | 8dd3dca3 | aurel32 | qemu_put_be32(f, u.l.upper); |
60 | 8dd3dca3 | aurel32 | qemu_put_be32(f, u.l.lower); |
61 | 8dd3dca3 | aurel32 | } |
62 | 8dd3dca3 | aurel32 | for (i = 0; i < 16; i++) { |
63 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->vfp.xregs[i]); |
64 | 8dd3dca3 | aurel32 | } |
65 | 8dd3dca3 | aurel32 | |
66 | 8dd3dca3 | aurel32 | /* TODO: Should use proper FPSCR access functions. */
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67 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->vfp.vec_len); |
68 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->vfp.vec_stride); |
69 | 8dd3dca3 | aurel32 | |
70 | 8dd3dca3 | aurel32 | if (arm_feature(env, ARM_FEATURE_VFP3)) {
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71 | 8dd3dca3 | aurel32 | for (i = 16; i < 32; i++) { |
72 | 8dd3dca3 | aurel32 | CPU_DoubleU u; |
73 | 8dd3dca3 | aurel32 | u.d = env->vfp.regs[i]; |
74 | 8dd3dca3 | aurel32 | qemu_put_be32(f, u.l.upper); |
75 | 8dd3dca3 | aurel32 | qemu_put_be32(f, u.l.lower); |
76 | 8dd3dca3 | aurel32 | } |
77 | 8dd3dca3 | aurel32 | } |
78 | 8dd3dca3 | aurel32 | } |
79 | 8dd3dca3 | aurel32 | |
80 | 8dd3dca3 | aurel32 | if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
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81 | 8dd3dca3 | aurel32 | for (i = 0; i < 16; i++) { |
82 | 8dd3dca3 | aurel32 | qemu_put_be64(f, env->iwmmxt.regs[i]); |
83 | 8dd3dca3 | aurel32 | } |
84 | 8dd3dca3 | aurel32 | for (i = 0; i < 16; i++) { |
85 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->iwmmxt.cregs[i]); |
86 | 8dd3dca3 | aurel32 | } |
87 | 8dd3dca3 | aurel32 | } |
88 | 8dd3dca3 | aurel32 | |
89 | 8dd3dca3 | aurel32 | if (arm_feature(env, ARM_FEATURE_M)) {
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90 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->v7m.other_sp); |
91 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->v7m.vecbase); |
92 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->v7m.basepri); |
93 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->v7m.control); |
94 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->v7m.current_sp); |
95 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->v7m.exception); |
96 | 8dd3dca3 | aurel32 | } |
97 | ffe47d33 | Paul Brook | |
98 | ffe47d33 | Paul Brook | if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
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99 | ffe47d33 | Paul Brook | qemu_put_be32(f, env->teecr); |
100 | ffe47d33 | Paul Brook | qemu_put_be32(f, env->teehbr); |
101 | ffe47d33 | Paul Brook | } |
102 | 8dd3dca3 | aurel32 | } |
103 | 8dd3dca3 | aurel32 | |
104 | 8dd3dca3 | aurel32 | int cpu_load(QEMUFile *f, void *opaque, int version_id) |
105 | 8dd3dca3 | aurel32 | { |
106 | 8dd3dca3 | aurel32 | CPUARMState *env = (CPUARMState *)opaque; |
107 | 8dd3dca3 | aurel32 | int i;
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108 | ffe47d33 | Paul Brook | uint32_t val; |
109 | 8dd3dca3 | aurel32 | |
110 | b3c7724c | pbrook | if (version_id != CPU_SAVE_VERSION)
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111 | 8dd3dca3 | aurel32 | return -EINVAL;
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112 | 8dd3dca3 | aurel32 | |
113 | 8dd3dca3 | aurel32 | for (i = 0; i < 16; i++) { |
114 | 8dd3dca3 | aurel32 | env->regs[i] = qemu_get_be32(f); |
115 | 8dd3dca3 | aurel32 | } |
116 | ffe47d33 | Paul Brook | val = qemu_get_be32(f); |
117 | ffe47d33 | Paul Brook | /* Avoid mode switch when restoring CPSR. */
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118 | ffe47d33 | Paul Brook | env->uncached_cpsr = val & CPSR_M; |
119 | ffe47d33 | Paul Brook | cpsr_write(env, val, 0xffffffff);
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120 | 8dd3dca3 | aurel32 | env->spsr = qemu_get_be32(f); |
121 | 8dd3dca3 | aurel32 | for (i = 0; i < 6; i++) { |
122 | 8dd3dca3 | aurel32 | env->banked_spsr[i] = qemu_get_be32(f); |
123 | 8dd3dca3 | aurel32 | env->banked_r13[i] = qemu_get_be32(f); |
124 | 8dd3dca3 | aurel32 | env->banked_r14[i] = qemu_get_be32(f); |
125 | 8dd3dca3 | aurel32 | } |
126 | 8dd3dca3 | aurel32 | for (i = 0; i < 5; i++) { |
127 | 8dd3dca3 | aurel32 | env->usr_regs[i] = qemu_get_be32(f); |
128 | 8dd3dca3 | aurel32 | env->fiq_regs[i] = qemu_get_be32(f); |
129 | 8dd3dca3 | aurel32 | } |
130 | 8dd3dca3 | aurel32 | env->cp15.c0_cpuid = qemu_get_be32(f); |
131 | 8dd3dca3 | aurel32 | env->cp15.c0_cachetype = qemu_get_be32(f); |
132 | ffe47d33 | Paul Brook | env->cp15.c0_cssel = qemu_get_be32(f); |
133 | 8dd3dca3 | aurel32 | env->cp15.c1_sys = qemu_get_be32(f); |
134 | 8dd3dca3 | aurel32 | env->cp15.c1_coproc = qemu_get_be32(f); |
135 | 8dd3dca3 | aurel32 | env->cp15.c1_xscaleauxcr = qemu_get_be32(f); |
136 | 8dd3dca3 | aurel32 | env->cp15.c2_base0 = qemu_get_be32(f); |
137 | 8dd3dca3 | aurel32 | env->cp15.c2_base1 = qemu_get_be32(f); |
138 | ffe47d33 | Paul Brook | env->cp15.c2_control = qemu_get_be32(f); |
139 | 8dd3dca3 | aurel32 | env->cp15.c2_mask = qemu_get_be32(f); |
140 | ffe47d33 | Paul Brook | env->cp15.c2_base_mask = qemu_get_be32(f); |
141 | 8dd3dca3 | aurel32 | env->cp15.c2_data = qemu_get_be32(f); |
142 | 8dd3dca3 | aurel32 | env->cp15.c2_insn = qemu_get_be32(f); |
143 | 8dd3dca3 | aurel32 | env->cp15.c3 = qemu_get_be32(f); |
144 | 8dd3dca3 | aurel32 | env->cp15.c5_insn = qemu_get_be32(f); |
145 | 8dd3dca3 | aurel32 | env->cp15.c5_data = qemu_get_be32(f); |
146 | 8dd3dca3 | aurel32 | for (i = 0; i < 8; i++) { |
147 | 8dd3dca3 | aurel32 | env->cp15.c6_region[i] = qemu_get_be32(f); |
148 | 8dd3dca3 | aurel32 | } |
149 | 8dd3dca3 | aurel32 | env->cp15.c6_insn = qemu_get_be32(f); |
150 | 8dd3dca3 | aurel32 | env->cp15.c6_data = qemu_get_be32(f); |
151 | 8dd3dca3 | aurel32 | env->cp15.c9_insn = qemu_get_be32(f); |
152 | 8dd3dca3 | aurel32 | env->cp15.c9_data = qemu_get_be32(f); |
153 | 8dd3dca3 | aurel32 | env->cp15.c13_fcse = qemu_get_be32(f); |
154 | 8dd3dca3 | aurel32 | env->cp15.c13_context = qemu_get_be32(f); |
155 | 8dd3dca3 | aurel32 | env->cp15.c13_tls1 = qemu_get_be32(f); |
156 | 8dd3dca3 | aurel32 | env->cp15.c13_tls2 = qemu_get_be32(f); |
157 | 8dd3dca3 | aurel32 | env->cp15.c13_tls3 = qemu_get_be32(f); |
158 | 8dd3dca3 | aurel32 | env->cp15.c15_cpar = qemu_get_be32(f); |
159 | 8dd3dca3 | aurel32 | |
160 | 8dd3dca3 | aurel32 | env->features = qemu_get_be32(f); |
161 | 8dd3dca3 | aurel32 | |
162 | 8dd3dca3 | aurel32 | if (arm_feature(env, ARM_FEATURE_VFP)) {
|
163 | 8dd3dca3 | aurel32 | for (i = 0; i < 16; i++) { |
164 | 8dd3dca3 | aurel32 | CPU_DoubleU u; |
165 | 8dd3dca3 | aurel32 | u.l.upper = qemu_get_be32(f); |
166 | 8dd3dca3 | aurel32 | u.l.lower = qemu_get_be32(f); |
167 | 8dd3dca3 | aurel32 | env->vfp.regs[i] = u.d; |
168 | 8dd3dca3 | aurel32 | } |
169 | 8dd3dca3 | aurel32 | for (i = 0; i < 16; i++) { |
170 | 8dd3dca3 | aurel32 | env->vfp.xregs[i] = qemu_get_be32(f); |
171 | 8dd3dca3 | aurel32 | } |
172 | 8dd3dca3 | aurel32 | |
173 | 8dd3dca3 | aurel32 | /* TODO: Should use proper FPSCR access functions. */
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174 | 8dd3dca3 | aurel32 | env->vfp.vec_len = qemu_get_be32(f); |
175 | 8dd3dca3 | aurel32 | env->vfp.vec_stride = qemu_get_be32(f); |
176 | 8dd3dca3 | aurel32 | |
177 | 8dd3dca3 | aurel32 | if (arm_feature(env, ARM_FEATURE_VFP3)) {
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178 | 8dd3dca3 | aurel32 | for (i = 0; i < 16; i++) { |
179 | 8dd3dca3 | aurel32 | CPU_DoubleU u; |
180 | 8dd3dca3 | aurel32 | u.l.upper = qemu_get_be32(f); |
181 | 8dd3dca3 | aurel32 | u.l.lower = qemu_get_be32(f); |
182 | 8dd3dca3 | aurel32 | env->vfp.regs[i] = u.d; |
183 | 8dd3dca3 | aurel32 | } |
184 | 8dd3dca3 | aurel32 | } |
185 | 8dd3dca3 | aurel32 | } |
186 | 8dd3dca3 | aurel32 | |
187 | 8dd3dca3 | aurel32 | if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
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188 | 8dd3dca3 | aurel32 | for (i = 0; i < 16; i++) { |
189 | 8dd3dca3 | aurel32 | env->iwmmxt.regs[i] = qemu_get_be64(f); |
190 | 8dd3dca3 | aurel32 | } |
191 | 8dd3dca3 | aurel32 | for (i = 0; i < 16; i++) { |
192 | 8dd3dca3 | aurel32 | env->iwmmxt.cregs[i] = qemu_get_be32(f); |
193 | 8dd3dca3 | aurel32 | } |
194 | 8dd3dca3 | aurel32 | } |
195 | 8dd3dca3 | aurel32 | |
196 | 8dd3dca3 | aurel32 | if (arm_feature(env, ARM_FEATURE_M)) {
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197 | 8dd3dca3 | aurel32 | env->v7m.other_sp = qemu_get_be32(f); |
198 | 8dd3dca3 | aurel32 | env->v7m.vecbase = qemu_get_be32(f); |
199 | 8dd3dca3 | aurel32 | env->v7m.basepri = qemu_get_be32(f); |
200 | 8dd3dca3 | aurel32 | env->v7m.control = qemu_get_be32(f); |
201 | 8dd3dca3 | aurel32 | env->v7m.current_sp = qemu_get_be32(f); |
202 | 8dd3dca3 | aurel32 | env->v7m.exception = qemu_get_be32(f); |
203 | 8dd3dca3 | aurel32 | } |
204 | 8dd3dca3 | aurel32 | |
205 | ffe47d33 | Paul Brook | if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
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206 | ffe47d33 | Paul Brook | env->teecr = qemu_get_be32(f); |
207 | ffe47d33 | Paul Brook | env->teehbr = qemu_get_be32(f); |
208 | ffe47d33 | Paul Brook | } |
209 | ffe47d33 | Paul Brook | |
210 | 8dd3dca3 | aurel32 | return 0; |
211 | 8dd3dca3 | aurel32 | } |