root / hw / tc58128.c @ 7f27bae6
History | View | Annotate | Download (4.2 kB)
1 | 27c7ca7e | bellard | #include <assert.h> |
---|---|---|---|
2 | 27c7ca7e | bellard | #include "vl.h" |
3 | 27c7ca7e | bellard | |
4 | 27c7ca7e | bellard | #define CE1 0x0100 |
5 | 27c7ca7e | bellard | #define CE2 0x0200 |
6 | 27c7ca7e | bellard | #define RE 0x0400 |
7 | 27c7ca7e | bellard | #define WE 0x0800 |
8 | 27c7ca7e | bellard | #define ALE 0x1000 |
9 | 27c7ca7e | bellard | #define CLE 0x2000 |
10 | 27c7ca7e | bellard | #define RDY1 0x4000 |
11 | 27c7ca7e | bellard | #define RDY2 0x8000 |
12 | 27c7ca7e | bellard | #define RDY(n) ((n) == 0 ? RDY1 : RDY2) |
13 | 27c7ca7e | bellard | |
14 | 27c7ca7e | bellard | typedef enum { WAIT, READ1, READ2, READ3 } state_t; |
15 | 27c7ca7e | bellard | |
16 | 27c7ca7e | bellard | typedef struct { |
17 | 27c7ca7e | bellard | uint8_t *flash_contents; |
18 | 27c7ca7e | bellard | state_t state; |
19 | 27c7ca7e | bellard | uint32_t address; |
20 | 27c7ca7e | bellard | uint8_t address_cycle; |
21 | 27c7ca7e | bellard | } tc58128_dev; |
22 | 27c7ca7e | bellard | |
23 | 27c7ca7e | bellard | static tc58128_dev tc58128_devs[2]; |
24 | 27c7ca7e | bellard | |
25 | 27c7ca7e | bellard | #define FLASH_SIZE (16*1024*1024) |
26 | 27c7ca7e | bellard | |
27 | 27c7ca7e | bellard | void init_dev(tc58128_dev * dev, char *filename) |
28 | 27c7ca7e | bellard | { |
29 | 27c7ca7e | bellard | int ret, blocks;
|
30 | 27c7ca7e | bellard | |
31 | 27c7ca7e | bellard | dev->state = WAIT; |
32 | 27c7ca7e | bellard | dev->flash_contents = qemu_mallocz(FLASH_SIZE); |
33 | 27c7ca7e | bellard | memset(dev->flash_contents, 0xff, FLASH_SIZE);
|
34 | 27c7ca7e | bellard | if (!dev->flash_contents) {
|
35 | 27c7ca7e | bellard | fprintf(stderr, "could not alloc memory for flash\n");
|
36 | 27c7ca7e | bellard | exit(1);
|
37 | 27c7ca7e | bellard | } |
38 | 27c7ca7e | bellard | if (filename) {
|
39 | 27c7ca7e | bellard | /* Load flash image skipping the first block */
|
40 | 27c7ca7e | bellard | ret = load_image(filename, dev->flash_contents + 528 * 32); |
41 | 27c7ca7e | bellard | if (ret < 0) { |
42 | 27c7ca7e | bellard | fprintf(stderr, "ret=%d\n", ret);
|
43 | 27c7ca7e | bellard | fprintf(stderr, "qemu: could not load flash image %s\n",
|
44 | 27c7ca7e | bellard | filename); |
45 | 27c7ca7e | bellard | exit(1);
|
46 | 27c7ca7e | bellard | } else {
|
47 | 27c7ca7e | bellard | /* Build first block with number of blocks */
|
48 | 27c7ca7e | bellard | blocks = (ret + 528 * 32 - 1) / (528 * 32); |
49 | 27c7ca7e | bellard | dev->flash_contents[0] = blocks & 0xff; |
50 | 27c7ca7e | bellard | dev->flash_contents[1] = (blocks >> 8) & 0xff; |
51 | 27c7ca7e | bellard | dev->flash_contents[2] = (blocks >> 16) & 0xff; |
52 | 27c7ca7e | bellard | dev->flash_contents[3] = (blocks >> 24) & 0xff; |
53 | 27c7ca7e | bellard | fprintf(stderr, "loaded %d bytes for %s into flash\n", ret,
|
54 | 27c7ca7e | bellard | filename); |
55 | 27c7ca7e | bellard | } |
56 | 27c7ca7e | bellard | } |
57 | 27c7ca7e | bellard | } |
58 | 27c7ca7e | bellard | |
59 | 27c7ca7e | bellard | void handle_command(tc58128_dev * dev, uint8_t command)
|
60 | 27c7ca7e | bellard | { |
61 | 27c7ca7e | bellard | switch (command) {
|
62 | 27c7ca7e | bellard | case 0xff: |
63 | 27c7ca7e | bellard | fprintf(stderr, "reset flash device\n");
|
64 | 27c7ca7e | bellard | dev->state = WAIT; |
65 | 27c7ca7e | bellard | break;
|
66 | 27c7ca7e | bellard | case 0x00: |
67 | 27c7ca7e | bellard | fprintf(stderr, "read mode 1\n");
|
68 | 27c7ca7e | bellard | dev->state = READ1; |
69 | 27c7ca7e | bellard | dev->address_cycle = 0;
|
70 | 27c7ca7e | bellard | break;
|
71 | 27c7ca7e | bellard | case 0x01: |
72 | 27c7ca7e | bellard | fprintf(stderr, "read mode 2\n");
|
73 | 27c7ca7e | bellard | dev->state = READ2; |
74 | 27c7ca7e | bellard | dev->address_cycle = 0;
|
75 | 27c7ca7e | bellard | break;
|
76 | 27c7ca7e | bellard | case 0x50: |
77 | 27c7ca7e | bellard | fprintf(stderr, "read mode 3\n");
|
78 | 27c7ca7e | bellard | dev->state = READ3; |
79 | 27c7ca7e | bellard | dev->address_cycle = 0;
|
80 | 27c7ca7e | bellard | break;
|
81 | 27c7ca7e | bellard | default:
|
82 | 27c7ca7e | bellard | fprintf(stderr, "unknown flash command 0x%02x\n", command);
|
83 | 27c7ca7e | bellard | assert(0);
|
84 | 27c7ca7e | bellard | } |
85 | 27c7ca7e | bellard | } |
86 | 27c7ca7e | bellard | |
87 | 27c7ca7e | bellard | void handle_address(tc58128_dev * dev, uint8_t data)
|
88 | 27c7ca7e | bellard | { |
89 | 27c7ca7e | bellard | switch (dev->state) {
|
90 | 27c7ca7e | bellard | case READ1:
|
91 | 27c7ca7e | bellard | case READ2:
|
92 | 27c7ca7e | bellard | case READ3:
|
93 | 27c7ca7e | bellard | switch (dev->address_cycle) {
|
94 | 27c7ca7e | bellard | case 0: |
95 | 27c7ca7e | bellard | dev->address = data; |
96 | 27c7ca7e | bellard | if (dev->state == READ2)
|
97 | 27c7ca7e | bellard | dev->address |= 0x100;
|
98 | 27c7ca7e | bellard | else if (dev->state == READ3) |
99 | 27c7ca7e | bellard | dev->address |= 0x200;
|
100 | 27c7ca7e | bellard | break;
|
101 | 27c7ca7e | bellard | case 1: |
102 | 27c7ca7e | bellard | dev->address += data * 528 * 0x100; |
103 | 27c7ca7e | bellard | break;
|
104 | 27c7ca7e | bellard | case 2: |
105 | 27c7ca7e | bellard | dev->address += data * 528;
|
106 | 27c7ca7e | bellard | fprintf(stderr, "address pointer in flash: 0x%08x\n",
|
107 | 27c7ca7e | bellard | dev->address); |
108 | 27c7ca7e | bellard | break;
|
109 | 27c7ca7e | bellard | default:
|
110 | 27c7ca7e | bellard | /* Invalid data */
|
111 | 27c7ca7e | bellard | assert(0);
|
112 | 27c7ca7e | bellard | } |
113 | 27c7ca7e | bellard | dev->address_cycle++; |
114 | 27c7ca7e | bellard | break;
|
115 | 27c7ca7e | bellard | default:
|
116 | 27c7ca7e | bellard | assert(0);
|
117 | 27c7ca7e | bellard | } |
118 | 27c7ca7e | bellard | } |
119 | 27c7ca7e | bellard | |
120 | 27c7ca7e | bellard | uint8_t handle_read(tc58128_dev * dev) |
121 | 27c7ca7e | bellard | { |
122 | 27c7ca7e | bellard | #if 0
|
123 | 27c7ca7e | bellard | if (dev->address % 0x100000 == 0)
|
124 | 27c7ca7e | bellard | fprintf(stderr, "reading flash at address 0x%08x\n", dev->address);
|
125 | 27c7ca7e | bellard | #endif
|
126 | 27c7ca7e | bellard | return dev->flash_contents[dev->address++];
|
127 | 27c7ca7e | bellard | } |
128 | 27c7ca7e | bellard | |
129 | 27c7ca7e | bellard | /* We never mark the device as busy, so interrupts cannot be triggered
|
130 | 27c7ca7e | bellard | XXXXX */
|
131 | 27c7ca7e | bellard | |
132 | 27c7ca7e | bellard | int tc58128_cb(uint16_t porta, uint16_t portb,
|
133 | 27c7ca7e | bellard | uint16_t * periph_pdtra, uint16_t * periph_portadir, |
134 | 27c7ca7e | bellard | uint16_t * periph_pdtrb, uint16_t * periph_portbdir) |
135 | 27c7ca7e | bellard | { |
136 | 27c7ca7e | bellard | int dev;
|
137 | 27c7ca7e | bellard | |
138 | 27c7ca7e | bellard | if ((porta & CE1) == 0) |
139 | 27c7ca7e | bellard | dev = 0;
|
140 | 27c7ca7e | bellard | else if ((porta & CE2) == 0) |
141 | 27c7ca7e | bellard | dev = 1;
|
142 | 27c7ca7e | bellard | else
|
143 | 27c7ca7e | bellard | return 0; /* No device selected */ |
144 | 27c7ca7e | bellard | |
145 | 27c7ca7e | bellard | if ((porta & RE) && (porta & WE)) {
|
146 | 27c7ca7e | bellard | /* Nothing to do, assert ready and return to input state */
|
147 | 27c7ca7e | bellard | *periph_portadir &= 0xff00;
|
148 | 27c7ca7e | bellard | *periph_portadir |= RDY(dev); |
149 | 27c7ca7e | bellard | *periph_pdtra |= RDY(dev); |
150 | 27c7ca7e | bellard | return 1; |
151 | 27c7ca7e | bellard | } |
152 | 27c7ca7e | bellard | |
153 | 27c7ca7e | bellard | if (porta & CLE) {
|
154 | 27c7ca7e | bellard | /* Command */
|
155 | 27c7ca7e | bellard | assert((porta & WE) == 0);
|
156 | 27c7ca7e | bellard | handle_command(&tc58128_devs[dev], porta & 0x00ff);
|
157 | 27c7ca7e | bellard | } else if (porta & ALE) { |
158 | 27c7ca7e | bellard | assert((porta & WE) == 0);
|
159 | 27c7ca7e | bellard | handle_address(&tc58128_devs[dev], porta & 0x00ff);
|
160 | 27c7ca7e | bellard | } else if ((porta & RE) == 0) { |
161 | 27c7ca7e | bellard | *periph_portadir |= 0x00ff;
|
162 | 27c7ca7e | bellard | *periph_pdtra &= 0xff00;
|
163 | 27c7ca7e | bellard | *periph_pdtra |= handle_read(&tc58128_devs[dev]); |
164 | 27c7ca7e | bellard | } else {
|
165 | 27c7ca7e | bellard | assert(0);
|
166 | 27c7ca7e | bellard | } |
167 | 27c7ca7e | bellard | return 1; |
168 | 27c7ca7e | bellard | } |
169 | 27c7ca7e | bellard | |
170 | 27c7ca7e | bellard | static sh7750_io_device tc58128 = {
|
171 | 27c7ca7e | bellard | RE | WE, /* Port A triggers */
|
172 | 27c7ca7e | bellard | 0, /* Port B triggers */ |
173 | 27c7ca7e | bellard | tc58128_cb /* Callback */
|
174 | 27c7ca7e | bellard | }; |
175 | 27c7ca7e | bellard | |
176 | 27c7ca7e | bellard | int tc58128_init(struct SH7750State *s, char *zone1, char *zone2) |
177 | 27c7ca7e | bellard | { |
178 | 27c7ca7e | bellard | init_dev(&tc58128_devs[0], zone1);
|
179 | 27c7ca7e | bellard | init_dev(&tc58128_devs[1], zone2);
|
180 | 27c7ca7e | bellard | return sh7750_register_io_device(s, &tc58128);
|
181 | 27c7ca7e | bellard | } |