Statistics
| Branch: | Revision:

root / hw / sb16.c @ 7f647cf6

History | View | Annotate | Download (17.3 kB)

1 27503323 bellard
/*
2 27503323 bellard
 * QEMU Soundblaster 16 emulation
3 27503323 bellard
 * 
4 27503323 bellard
 * Copyright (c) 2003 Vassili Karpov (malc)
5 27503323 bellard
 * 
6 27503323 bellard
 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 27503323 bellard
 * of this software and associated documentation files (the "Software"), to deal
8 27503323 bellard
 * in the Software without restriction, including without limitation the rights
9 27503323 bellard
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 27503323 bellard
 * copies of the Software, and to permit persons to whom the Software is
11 27503323 bellard
 * furnished to do so, subject to the following conditions:
12 27503323 bellard
 *
13 27503323 bellard
 * The above copyright notice and this permission notice shall be included in
14 27503323 bellard
 * all copies or substantial portions of the Software.
15 27503323 bellard
 *
16 27503323 bellard
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 27503323 bellard
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 27503323 bellard
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 27503323 bellard
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 27503323 bellard
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 27503323 bellard
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 27503323 bellard
 * THE SOFTWARE.
23 27503323 bellard
 */
24 27503323 bellard
#include "vl.h"
25 27503323 bellard
26 27503323 bellard
#define MIN(a, b) ((a)>(b)?(b):(a))
27 27503323 bellard
#define LENOFA(a) ((int) (sizeof(a)/sizeof(a[0])))
28 27503323 bellard
29 d329a6fb bellard
#define log(...) do {                           \
30 d329a6fb bellard
    fprintf (stderr, "sb16: " __VA_ARGS__);     \
31 d329a6fb bellard
    fputc ('\n', stderr);                       \
32 d329a6fb bellard
} while (0)
33 27503323 bellard
34 bc0b1dc1 bellard
/* #define DEBUG_SB16 */
35 27503323 bellard
#ifdef DEBUG_SB16
36 27503323 bellard
#define lwarn(...) fprintf (stderr, "sb16: " __VA_ARGS__)
37 27503323 bellard
#define linfo(...) fprintf (stderr, "sb16: " __VA_ARGS__)
38 27503323 bellard
#define ldebug(...) fprintf (stderr, "sb16: " __VA_ARGS__)
39 27503323 bellard
#else
40 27503323 bellard
#define lwarn(...)
41 27503323 bellard
#define linfo(...)
42 27503323 bellard
#define ldebug(...)
43 27503323 bellard
#endif
44 27503323 bellard
45 27503323 bellard
#define IO_READ_PROTO(name) \
46 7d977de7 bellard
    uint32_t name (void *opaque, uint32_t nport)
47 27503323 bellard
#define IO_WRITE_PROTO(name) \
48 7d977de7 bellard
    void name (void *opaque, uint32_t nport, uint32_t val)
49 27503323 bellard
50 d329a6fb bellard
static const char e3[] = "COPYRIGHT (C) CREATIVE TECHNOLOGY LTD, 1992.";
51 d329a6fb bellard
52 27503323 bellard
static struct {
53 27503323 bellard
    int ver_lo;
54 27503323 bellard
    int ver_hi;
55 27503323 bellard
    int irq;
56 27503323 bellard
    int dma;
57 27503323 bellard
    int hdma;
58 27503323 bellard
    int port;
59 27503323 bellard
    int mix_block;
60 bc0b1dc1 bellard
} sb = {5, 4, 5, 1, 5, 0x220, -1};
61 27503323 bellard
62 27503323 bellard
static int mix_block, noirq;
63 27503323 bellard
64 5e2a6443 bellard
typedef struct SB16State {
65 27503323 bellard
    int in_index;
66 27503323 bellard
    int out_data_len;
67 27503323 bellard
    int fmt_stereo;
68 27503323 bellard
    int fmt_signed;
69 27503323 bellard
    int fmt_bits;
70 27503323 bellard
    int dma_auto;
71 27503323 bellard
    int dma_buffer_size;
72 27503323 bellard
    int fifo;
73 27503323 bellard
    int freq;
74 27503323 bellard
    int time_const;
75 27503323 bellard
    int speaker;
76 27503323 bellard
    int needed_bytes;
77 27503323 bellard
    int cmd;
78 27503323 bellard
    int dma_pos;
79 27503323 bellard
    int use_hdma;
80 27503323 bellard
81 27503323 bellard
    int v2x6;
82 27503323 bellard
83 27503323 bellard
    uint8_t in_data[10];
84 d329a6fb bellard
    uint8_t out_data[50];
85 27503323 bellard
86 27503323 bellard
    int left_till_irq;
87 27503323 bellard
88 5e2a6443 bellard
    /* mixer state */
89 5e2a6443 bellard
    int mixer_nreg;
90 202a456a bellard
    uint8_t mixer_regs[256];
91 5e2a6443 bellard
} SB16State;
92 27503323 bellard
93 5e2a6443 bellard
/* XXX: suppress that and use a context */
94 5e2a6443 bellard
static struct SB16State dsp;
95 27503323 bellard
96 5e2a6443 bellard
static void log_dsp (SB16State *dsp)
97 5e2a6443 bellard
{
98 27503323 bellard
    linfo ("%c:%c:%d:%c:dmabuf=%d:pos=%d:freq=%d:timeconst=%d:speaker=%d\n",
99 5e2a6443 bellard
           dsp->fmt_stereo ? 'S' : 'M',
100 5e2a6443 bellard
           dsp->fmt_signed ? 'S' : 'U',
101 5e2a6443 bellard
           dsp->fmt_bits,
102 5e2a6443 bellard
           dsp->dma_auto ? 'a' : 's',
103 5e2a6443 bellard
           dsp->dma_buffer_size,
104 5e2a6443 bellard
           dsp->dma_pos,
105 5e2a6443 bellard
           dsp->freq,
106 5e2a6443 bellard
           dsp->time_const,
107 5e2a6443 bellard
           dsp->speaker);
108 27503323 bellard
}
109 27503323 bellard
110 27503323 bellard
static void control (int hold)
111 27503323 bellard
{
112 27503323 bellard
    linfo ("%d high %d\n", hold, dsp.use_hdma);
113 27503323 bellard
    if (hold) {
114 27503323 bellard
        if (dsp.use_hdma)
115 27503323 bellard
            DMA_hold_DREQ (sb.hdma);
116 27503323 bellard
        else
117 27503323 bellard
            DMA_hold_DREQ (sb.dma);
118 27503323 bellard
    }
119 27503323 bellard
    else {
120 27503323 bellard
        if (dsp.use_hdma)
121 27503323 bellard
            DMA_release_DREQ (sb.hdma);
122 27503323 bellard
        else
123 27503323 bellard
            DMA_release_DREQ (sb.dma);
124 27503323 bellard
    }
125 27503323 bellard
}
126 27503323 bellard
127 27503323 bellard
static void dma_cmd (uint8_t cmd, uint8_t d0, int dma_len)
128 27503323 bellard
{
129 27503323 bellard
    int bps;
130 27503323 bellard
    audfmt_e fmt;
131 27503323 bellard
132 27503323 bellard
    dsp.use_hdma = cmd < 0xc0;
133 27503323 bellard
    dsp.fifo = (cmd >> 1) & 1;
134 27503323 bellard
    dsp.dma_auto = (cmd >> 2) & 1;
135 27503323 bellard
136 27503323 bellard
    switch (cmd >> 4) {
137 27503323 bellard
    case 11:
138 27503323 bellard
        dsp.fmt_bits = 16;
139 27503323 bellard
        break;
140 27503323 bellard
141 27503323 bellard
    case 12:
142 27503323 bellard
        dsp.fmt_bits = 8;
143 27503323 bellard
        break;
144 27503323 bellard
    }
145 27503323 bellard
146 27503323 bellard
    dsp.fmt_signed = (d0 >> 4) & 1;
147 27503323 bellard
    dsp.fmt_stereo = (d0 >> 5) & 1;
148 27503323 bellard
149 27503323 bellard
    if (-1 != dsp.time_const) {
150 27503323 bellard
        int tmp;
151 27503323 bellard
152 27503323 bellard
        tmp = 256 - dsp.time_const;
153 27503323 bellard
        dsp.freq = (1000000 + (tmp / 2)) / tmp;
154 27503323 bellard
    }
155 27503323 bellard
    bps = 1 << (16 == dsp.fmt_bits);
156 27503323 bellard
157 27503323 bellard
    if (-1 != dma_len)
158 27503323 bellard
        dsp.dma_buffer_size = (dma_len + 1) * bps;
159 27503323 bellard
160 27503323 bellard
    linfo ("frequency %d, stereo %d, signed %d, bits %d, size %d, auto %d\n",
161 27503323 bellard
           dsp.freq, dsp.fmt_stereo, dsp.fmt_signed, dsp.fmt_bits,
162 27503323 bellard
           dsp.dma_buffer_size, dsp.dma_auto);
163 27503323 bellard
164 27503323 bellard
    if (16 == dsp.fmt_bits) {
165 27503323 bellard
        if (dsp.fmt_signed) {
166 27503323 bellard
            fmt = AUD_FMT_S16;
167 27503323 bellard
        }
168 27503323 bellard
        else {
169 27503323 bellard
            fmt = AUD_FMT_U16;
170 27503323 bellard
        }
171 27503323 bellard
    }
172 27503323 bellard
    else {
173 27503323 bellard
        if (dsp.fmt_signed) {
174 27503323 bellard
            fmt = AUD_FMT_S8;
175 27503323 bellard
        }
176 27503323 bellard
        else {
177 27503323 bellard
            fmt = AUD_FMT_U8;
178 27503323 bellard
        }
179 27503323 bellard
    }
180 27503323 bellard
181 27503323 bellard
    dsp.dma_pos = 0;
182 27503323 bellard
    dsp.left_till_irq = dsp.dma_buffer_size;
183 27503323 bellard
184 27503323 bellard
    if (sb.mix_block) {
185 27503323 bellard
        mix_block = sb.mix_block;
186 27503323 bellard
    }
187 27503323 bellard
    else {
188 27503323 bellard
        int align;
189 27503323 bellard
190 27503323 bellard
        align = bps << dsp.fmt_stereo;
191 27503323 bellard
        mix_block = ((dsp.freq * align) / 100) & ~(align - 1);
192 27503323 bellard
    }
193 27503323 bellard
194 27503323 bellard
    AUD_reset (dsp.freq, 1 << dsp.fmt_stereo, fmt);
195 27503323 bellard
    control (1);
196 27503323 bellard
    dsp.speaker = 1;
197 27503323 bellard
}
198 27503323 bellard
199 202a456a bellard
static inline void dsp_out_data(SB16State *dsp, int val)
200 202a456a bellard
{
201 202a456a bellard
    if (dsp->out_data_len < sizeof(dsp->out_data))
202 202a456a bellard
        dsp->out_data[dsp->out_data_len++] = val;
203 202a456a bellard
}
204 202a456a bellard
205 5e2a6443 bellard
static void command (SB16State *dsp, uint8_t cmd)
206 27503323 bellard
{
207 27503323 bellard
    linfo ("%#x\n", cmd);
208 27503323 bellard
209 27503323 bellard
    if (cmd > 0xaf && cmd < 0xd0) {
210 27503323 bellard
        if (cmd & 8)
211 27503323 bellard
            goto error;
212 27503323 bellard
213 27503323 bellard
        switch (cmd >> 4) {
214 27503323 bellard
        case 11:
215 27503323 bellard
        case 12:
216 27503323 bellard
            break;
217 27503323 bellard
        default:
218 5e2a6443 bellard
            log("%#x wrong bits", cmd);
219 27503323 bellard
            goto error;
220 27503323 bellard
        }
221 5e2a6443 bellard
        dsp->needed_bytes = 3;
222 27503323 bellard
    }
223 27503323 bellard
    else {
224 27503323 bellard
        switch (cmd) {
225 bc0b1dc1 bellard
        case 0x00:
226 bc0b1dc1 bellard
        case 0x03:
227 bc0b1dc1 bellard
        case 0xe7:
228 bc0b1dc1 bellard
            /* IMS uses those when probing for sound devices */
229 bc0b1dc1 bellard
            return;
230 bc0b1dc1 bellard
231 d329a6fb bellard
        case 0x04:
232 d329a6fb bellard
            dsp->needed_bytes = 1;
233 d329a6fb bellard
            break;
234 d329a6fb bellard
235 d329a6fb bellard
        case 0x05:
236 d329a6fb bellard
        case 0x0e:
237 d329a6fb bellard
            dsp->needed_bytes = 2;
238 d329a6fb bellard
            break;
239 d329a6fb bellard
240 d329a6fb bellard
        case 0x0f:
241 d329a6fb bellard
            dsp->needed_bytes = 1;
242 d329a6fb bellard
            dsp_out_data (dsp, 0);
243 d329a6fb bellard
            break;
244 d329a6fb bellard
245 27503323 bellard
        case 0x10:
246 5e2a6443 bellard
            dsp->needed_bytes = 1;
247 27503323 bellard
            break;
248 27503323 bellard
249 27503323 bellard
        case 0x14:
250 5e2a6443 bellard
            dsp->needed_bytes = 2;
251 5e2a6443 bellard
            dsp->dma_buffer_size = 0;
252 27503323 bellard
            break;
253 27503323 bellard
254 27503323 bellard
        case 0x20:
255 202a456a bellard
            dsp_out_data(dsp, 0xff);
256 27503323 bellard
            break;
257 27503323 bellard
258 27503323 bellard
        case 0x35:
259 27503323 bellard
            lwarn ("MIDI commands not implemented\n");
260 27503323 bellard
            break;
261 27503323 bellard
262 27503323 bellard
        case 0x40:
263 5e2a6443 bellard
            dsp->freq = -1;
264 5e2a6443 bellard
            dsp->time_const = -1;
265 5e2a6443 bellard
            dsp->needed_bytes = 1;
266 27503323 bellard
            break;
267 27503323 bellard
268 27503323 bellard
        case 0x41:
269 27503323 bellard
        case 0x42:
270 5e2a6443 bellard
            dsp->freq = -1;
271 5e2a6443 bellard
            dsp->time_const = -1;
272 5e2a6443 bellard
            dsp->needed_bytes = 2;
273 27503323 bellard
            break;
274 27503323 bellard
275 27503323 bellard
        case 0x47:                /* Continue Auto-Initialize DMA 16bit */
276 27503323 bellard
            break;
277 27503323 bellard
278 27503323 bellard
        case 0x48:
279 5e2a6443 bellard
            dsp->needed_bytes = 2;
280 27503323 bellard
            break;
281 27503323 bellard
282 27503323 bellard
        case 0x27:                /* ????????? */
283 27503323 bellard
        case 0x4e:
284 27503323 bellard
            return;
285 27503323 bellard
286 27503323 bellard
        case 0x80:
287 5e2a6443 bellard
            cmd = -1;
288 27503323 bellard
            break;
289 27503323 bellard
290 27503323 bellard
        case 0x90:
291 27503323 bellard
        case 0x91:
292 27503323 bellard
            {
293 27503323 bellard
                uint8_t d0;
294 27503323 bellard
295 27503323 bellard
                d0 = 4;
296 d329a6fb bellard
                /* if (dsp->fmt_signed) d0 |= 16; */
297 d329a6fb bellard
                /* if (dsp->fmt_stereo) d0 |= 32; */
298 27503323 bellard
                dma_cmd (cmd == 0x90 ? 0xc4 : 0xc0, d0, -1);
299 5e2a6443 bellard
                cmd = -1;
300 27503323 bellard
                break;
301 27503323 bellard
            }
302 27503323 bellard
303 27503323 bellard
        case 0xd0:                /* XXX */
304 27503323 bellard
            control (0);
305 27503323 bellard
            return;
306 27503323 bellard
307 27503323 bellard
        case 0xd1:
308 5e2a6443 bellard
            dsp->speaker = 1;
309 27503323 bellard
            break;
310 27503323 bellard
311 27503323 bellard
        case 0xd3:
312 5e2a6443 bellard
            dsp->speaker = 0;
313 27503323 bellard
            return;
314 27503323 bellard
315 27503323 bellard
        case 0xd4:
316 27503323 bellard
            control (1);
317 27503323 bellard
            break;
318 27503323 bellard
319 27503323 bellard
        case 0xd5:
320 27503323 bellard
            control (0);
321 27503323 bellard
            break;
322 27503323 bellard
323 27503323 bellard
        case 0xd6:
324 27503323 bellard
            control (1);
325 27503323 bellard
            break;
326 27503323 bellard
327 27503323 bellard
        case 0xd9:
328 27503323 bellard
            control (0);
329 5e2a6443 bellard
            dsp->dma_auto = 0;
330 27503323 bellard
            return;
331 27503323 bellard
332 27503323 bellard
        case 0xda:
333 27503323 bellard
            control (0);
334 5e2a6443 bellard
            dsp->dma_auto = 0;
335 27503323 bellard
            break;
336 27503323 bellard
337 27503323 bellard
        case 0xe0:
338 5e2a6443 bellard
            dsp->needed_bytes = 1;
339 27503323 bellard
            break;
340 27503323 bellard
341 27503323 bellard
        case 0xe1:
342 202a456a bellard
            dsp_out_data(dsp, sb.ver_lo);
343 202a456a bellard
            dsp_out_data(dsp, sb.ver_hi);
344 27503323 bellard
            return;
345 27503323 bellard
346 d329a6fb bellard
        case 0xe3:
347 d329a6fb bellard
            {
348 d329a6fb bellard
                int i;
349 d329a6fb bellard
                for (i = sizeof (e3) - 1; i >= 0; --i)
350 d329a6fb bellard
                    dsp_out_data (dsp, e3[i]);
351 d329a6fb bellard
                return;
352 d329a6fb bellard
            }
353 d329a6fb bellard
354 27503323 bellard
        case 0xf2:
355 202a456a bellard
            dsp_out_data(dsp, 0xaa);
356 5e2a6443 bellard
            dsp->mixer_regs[0x82] |= dsp->mixer_regs[0x80];
357 27503323 bellard
            pic_set_irq (sb.irq, 1);
358 27503323 bellard
            return;
359 27503323 bellard
360 27503323 bellard
        default:
361 5e2a6443 bellard
            log("%#x is unknown", cmd);
362 27503323 bellard
            goto error;
363 27503323 bellard
        }
364 27503323 bellard
    }
365 5e2a6443 bellard
    dsp->cmd = cmd;
366 27503323 bellard
    return;
367 27503323 bellard
368 27503323 bellard
 error:
369 27503323 bellard
    return;
370 27503323 bellard
}
371 27503323 bellard
372 5e2a6443 bellard
static void complete (SB16State *dsp)
373 27503323 bellard
{
374 27503323 bellard
    linfo ("complete command %#x, in_index %d, needed_bytes %d\n",
375 5e2a6443 bellard
           dsp->cmd, dsp->in_index, dsp->needed_bytes);
376 27503323 bellard
377 5e2a6443 bellard
    if (dsp->cmd > 0xaf && dsp->cmd < 0xd0) {
378 27503323 bellard
        int d0, d1, d2;
379 27503323 bellard
380 5e2a6443 bellard
        d0 = dsp->in_data[0];
381 5e2a6443 bellard
        d1 = dsp->in_data[1];
382 5e2a6443 bellard
        d2 = dsp->in_data[2];
383 27503323 bellard
384 27503323 bellard
        ldebug ("d0 = %d, d1 = %d, d2 = %d\n",
385 27503323 bellard
                d0, d1, d2);
386 5e2a6443 bellard
        dma_cmd (dsp->cmd, d0, d1 + (d2 << 8));
387 27503323 bellard
    }
388 27503323 bellard
    else {
389 5e2a6443 bellard
        switch (dsp->cmd) {
390 d329a6fb bellard
        case 0x05:
391 d329a6fb bellard
        case 0x04:
392 d329a6fb bellard
        case 0x0e:
393 d329a6fb bellard
        case 0x0f:
394 d329a6fb bellard
            break;
395 27503323 bellard
396 27503323 bellard
        case 0x10:
397 27503323 bellard
            break;
398 27503323 bellard
399 27503323 bellard
        case 0x14:
400 27503323 bellard
            {
401 27503323 bellard
                int d0, d1;
402 27503323 bellard
                int save_left;
403 27503323 bellard
                int save_pos;
404 27503323 bellard
405 5e2a6443 bellard
                d0 = dsp->in_data[0];
406 5e2a6443 bellard
                d1 = dsp->in_data[1];
407 27503323 bellard
408 5e2a6443 bellard
                save_left = dsp->left_till_irq;
409 5e2a6443 bellard
                save_pos = dsp->dma_pos;
410 27503323 bellard
                dma_cmd (0xc0, 0, d0 + (d1 << 8));
411 5e2a6443 bellard
                dsp->left_till_irq = save_left;
412 5e2a6443 bellard
                dsp->dma_pos = save_pos;
413 27503323 bellard
414 27503323 bellard
                linfo ("set buffer size data[%d, %d] %d pos %d\n",
415 5e2a6443 bellard
                       d0, d1, dsp->dma_buffer_size, dsp->dma_pos);
416 27503323 bellard
                break;
417 27503323 bellard
            }
418 27503323 bellard
419 27503323 bellard
        case 0x40:
420 5e2a6443 bellard
            dsp->time_const = dsp->in_data[0];
421 5e2a6443 bellard
            linfo ("set time const %d\n", dsp->time_const);
422 27503323 bellard
            break;
423 27503323 bellard
424 27503323 bellard
        case 0x41:
425 27503323 bellard
        case 0x42:
426 5e2a6443 bellard
            dsp->freq = dsp->in_data[1] + (dsp->in_data[0] << 8);
427 27503323 bellard
            linfo ("set freq %#x, %#x = %d\n",
428 5e2a6443 bellard
                   dsp->in_data[1], dsp->in_data[0], dsp->freq);
429 27503323 bellard
            break;
430 27503323 bellard
431 27503323 bellard
        case 0x48:
432 5e2a6443 bellard
            dsp->dma_buffer_size = dsp->in_data[1] + (dsp->in_data[0] << 8);
433 27503323 bellard
            linfo ("set dma len %#x, %#x = %d\n",
434 5e2a6443 bellard
                   dsp->in_data[1], dsp->in_data[0], dsp->dma_buffer_size);
435 27503323 bellard
            break;
436 27503323 bellard
437 27503323 bellard
        case 0xe0:
438 202a456a bellard
            dsp->out_data_len = 0;
439 5e2a6443 bellard
            linfo ("data = %#x\n", dsp->in_data[0]);
440 202a456a bellard
            dsp_out_data(dsp, dsp->in_data[0] ^ 0xff);
441 27503323 bellard
            break;
442 27503323 bellard
443 27503323 bellard
        default:
444 5e2a6443 bellard
            log ("unrecognized command %#x", dsp->cmd);
445 5e2a6443 bellard
            return;
446 27503323 bellard
        }
447 27503323 bellard
    }
448 27503323 bellard
449 5e2a6443 bellard
    dsp->cmd = -1;
450 27503323 bellard
    return;
451 27503323 bellard
}
452 27503323 bellard
453 27503323 bellard
static IO_WRITE_PROTO (dsp_write)
454 27503323 bellard
{
455 5e2a6443 bellard
    SB16State *dsp = opaque;
456 27503323 bellard
    int iport;
457 27503323 bellard
458 27503323 bellard
    iport = nport - sb.port;
459 27503323 bellard
460 d329a6fb bellard
    ldebug ("write %#x %#x\n", nport, iport);
461 27503323 bellard
    switch (iport) {
462 27503323 bellard
    case 0x6:
463 d329a6fb bellard
        control (0);
464 27503323 bellard
        if (0 == val)
465 5e2a6443 bellard
            dsp->v2x6 = 0;
466 5e2a6443 bellard
        else if ((1 == val) && (0 == dsp->v2x6)) {
467 5e2a6443 bellard
            dsp->v2x6 = 1;
468 202a456a bellard
            dsp_out_data(dsp, 0xaa);
469 27503323 bellard
        }
470 27503323 bellard
        else
471 5e2a6443 bellard
            dsp->v2x6 = ~0;
472 27503323 bellard
        break;
473 27503323 bellard
474 27503323 bellard
    case 0xc:                   /* write data or command | write status */
475 5e2a6443 bellard
        if (0 == dsp->needed_bytes) {
476 5e2a6443 bellard
            command (dsp, val);
477 5e2a6443 bellard
            if (0 == dsp->needed_bytes) {
478 5e2a6443 bellard
                log_dsp (dsp);
479 27503323 bellard
            }
480 27503323 bellard
        }
481 27503323 bellard
        else {
482 5e2a6443 bellard
            dsp->in_data[dsp->in_index++] = val;
483 5e2a6443 bellard
            if (dsp->in_index == dsp->needed_bytes) {
484 5e2a6443 bellard
                dsp->needed_bytes = 0;
485 5e2a6443 bellard
                dsp->in_index = 0;
486 5e2a6443 bellard
                complete (dsp);
487 5e2a6443 bellard
                log_dsp (dsp);
488 27503323 bellard
            }
489 27503323 bellard
        }
490 27503323 bellard
        break;
491 27503323 bellard
492 27503323 bellard
    default:
493 5e2a6443 bellard
        log ("(nport=%#x, val=%#x)", nport, val);
494 5e2a6443 bellard
        break;
495 27503323 bellard
    }
496 27503323 bellard
}
497 27503323 bellard
498 27503323 bellard
static IO_READ_PROTO (dsp_read)
499 27503323 bellard
{
500 5e2a6443 bellard
    SB16State *dsp = opaque;
501 27503323 bellard
    int iport, retval;
502 27503323 bellard
503 27503323 bellard
    iport = nport - sb.port;
504 27503323 bellard
505 27503323 bellard
    switch (iport) {
506 27503323 bellard
507 27503323 bellard
    case 0x6:                   /* reset */
508 27503323 bellard
        return 0;
509 27503323 bellard
510 27503323 bellard
    case 0xa:                   /* read data */
511 5e2a6443 bellard
        if (dsp->out_data_len) {
512 5e2a6443 bellard
            retval = dsp->out_data[--dsp->out_data_len];
513 5e2a6443 bellard
        } else {
514 d329a6fb bellard
            log("empty output buffer");
515 27503323 bellard
            goto error;
516 27503323 bellard
        }
517 27503323 bellard
        break;
518 27503323 bellard
519 27503323 bellard
    case 0xc:                   /* 0 can write */
520 27503323 bellard
        retval = 0;
521 27503323 bellard
        break;
522 27503323 bellard
523 27503323 bellard
    case 0xd:                   /* timer interrupt clear */
524 d329a6fb bellard
        log("timer interrupt clear");
525 27503323 bellard
        goto error;
526 27503323 bellard
527 27503323 bellard
    case 0xe:                   /* data available status | irq 8 ack */
528 bc0b1dc1 bellard
        /* XXX drop pic irq line here? */
529 bc0b1dc1 bellard
        ldebug ("8 ack\n");
530 5e2a6443 bellard
        retval = (0 == dsp->out_data_len) ? 0 : 0x80;
531 5e2a6443 bellard
        dsp->mixer_regs[0x82] &= ~dsp->mixer_regs[0x80];
532 bc0b1dc1 bellard
        pic_set_irq (sb.irq, 0);
533 27503323 bellard
        break;
534 27503323 bellard
535 27503323 bellard
    case 0xf:                   /* irq 16 ack */
536 bc0b1dc1 bellard
        /* XXX drop pic irq line here? */
537 27503323 bellard
        ldebug ("16 ack\n");
538 bc0b1dc1 bellard
        retval = 0xff;
539 5e2a6443 bellard
        dsp->mixer_regs[0x82] &= ~dsp->mixer_regs[0x80];
540 bc0b1dc1 bellard
        pic_set_irq (sb.irq, 0);
541 27503323 bellard
        break;
542 27503323 bellard
543 27503323 bellard
    default:
544 27503323 bellard
        goto error;
545 27503323 bellard
    }
546 27503323 bellard
547 27503323 bellard
    if ((0xc != iport) && (0xe != iport)) {
548 bc0b1dc1 bellard
        ldebug ("nport=%#x iport %#x = %#x\n",
549 bc0b1dc1 bellard
                nport, iport, retval);
550 27503323 bellard
    }
551 27503323 bellard
552 27503323 bellard
    return retval;
553 27503323 bellard
554 27503323 bellard
 error:
555 5e2a6443 bellard
    return 0;
556 27503323 bellard
}
557 27503323 bellard
558 27503323 bellard
static IO_WRITE_PROTO(mixer_write_indexb)
559 27503323 bellard
{
560 5e2a6443 bellard
    SB16State *dsp = opaque;
561 202a456a bellard
    dsp->mixer_nreg = val;
562 27503323 bellard
}
563 27503323 bellard
564 27503323 bellard
static IO_WRITE_PROTO(mixer_write_datab)
565 27503323 bellard
{
566 5e2a6443 bellard
    SB16State *dsp = opaque;
567 202a456a bellard
568 202a456a bellard
    if (dsp->mixer_nreg > 0x83)
569 202a456a bellard
        return;
570 5e2a6443 bellard
    dsp->mixer_regs[dsp->mixer_nreg] = val;
571 27503323 bellard
}
572 27503323 bellard
573 27503323 bellard
static IO_WRITE_PROTO(mixer_write_indexw)
574 27503323 bellard
{
575 7d977de7 bellard
    mixer_write_indexb (opaque, nport, val & 0xff);
576 7d977de7 bellard
    mixer_write_datab (opaque, nport, (val >> 8) & 0xff);
577 27503323 bellard
}
578 27503323 bellard
579 27503323 bellard
static IO_READ_PROTO(mixer_read)
580 27503323 bellard
{
581 5e2a6443 bellard
    SB16State *dsp = opaque;
582 5e2a6443 bellard
    return dsp->mixer_regs[dsp->mixer_nreg];
583 27503323 bellard
}
584 27503323 bellard
585 27503323 bellard
void SB16_run (void)
586 27503323 bellard
{
587 27503323 bellard
    if (0 == dsp.speaker)
588 27503323 bellard
        return;
589 27503323 bellard
590 27503323 bellard
    AUD_run ();
591 27503323 bellard
}
592 27503323 bellard
593 27503323 bellard
static int write_audio (uint32_t addr, int len, int size)
594 27503323 bellard
{
595 27503323 bellard
    int temp, net;
596 f9e92e97 bellard
    uint8_t tmpbuf[4096];
597 27503323 bellard
598 27503323 bellard
    temp = size;
599 27503323 bellard
600 27503323 bellard
    net = 0;
601 27503323 bellard
602 27503323 bellard
    while (temp) {
603 27503323 bellard
        int left_till_end;
604 27503323 bellard
        int to_copy;
605 27503323 bellard
        int copied;
606 27503323 bellard
607 27503323 bellard
        left_till_end = len - dsp.dma_pos;
608 27503323 bellard
609 27503323 bellard
        to_copy = MIN (temp, left_till_end);
610 f9e92e97 bellard
        if (to_copy > sizeof(tmpbuf))
611 f9e92e97 bellard
            to_copy = sizeof(tmpbuf);
612 f9e92e97 bellard
        cpu_physical_memory_read(addr + dsp.dma_pos, tmpbuf, to_copy);
613 f9e92e97 bellard
        copied = AUD_write (tmpbuf, to_copy);
614 27503323 bellard
615 27503323 bellard
        temp -= copied;
616 27503323 bellard
        dsp.dma_pos += copied;
617 27503323 bellard
618 27503323 bellard
        if (dsp.dma_pos == len) {
619 27503323 bellard
            dsp.dma_pos = 0;
620 27503323 bellard
        }
621 27503323 bellard
622 27503323 bellard
        net += copied;
623 27503323 bellard
624 27503323 bellard
        if (copied != to_copy)
625 27503323 bellard
            return net;
626 27503323 bellard
    }
627 27503323 bellard
628 27503323 bellard
    return net;
629 27503323 bellard
}
630 27503323 bellard
631 f9e92e97 bellard
static int SB_read_DMA (void *opaque, target_ulong addr, int size)
632 27503323 bellard
{
633 5e2a6443 bellard
    SB16State *dsp = opaque;
634 27503323 bellard
    int free, till, copy, written;
635 27503323 bellard
636 5e2a6443 bellard
    if (0 == dsp->speaker)
637 27503323 bellard
        return 0;
638 27503323 bellard
639 5e2a6443 bellard
    if (dsp->left_till_irq < 0) {
640 5e2a6443 bellard
        dsp->left_till_irq += dsp->dma_buffer_size;
641 5e2a6443 bellard
        return dsp->dma_pos;
642 27503323 bellard
    }
643 27503323 bellard
644 27503323 bellard
    free = AUD_get_free ();
645 27503323 bellard
646 27503323 bellard
    if ((free <= 0) || (0 == size)) {
647 5e2a6443 bellard
        return dsp->dma_pos;
648 27503323 bellard
    }
649 27503323 bellard
650 27503323 bellard
    if (mix_block > 0) {
651 27503323 bellard
        copy = MIN (free, mix_block);
652 27503323 bellard
    }
653 27503323 bellard
    else {
654 27503323 bellard
        copy = free;
655 27503323 bellard
    }
656 27503323 bellard
657 5e2a6443 bellard
    till = dsp->left_till_irq;
658 27503323 bellard
659 27503323 bellard
    ldebug ("addr:%#010x free:%d till:%d size:%d\n",
660 27503323 bellard
            addr, free, till, size);
661 27503323 bellard
    if (till <= copy) {
662 5e2a6443 bellard
        if (0 == dsp->dma_auto) {
663 27503323 bellard
            copy = till;
664 27503323 bellard
        }
665 27503323 bellard
    }
666 27503323 bellard
667 27503323 bellard
    written = write_audio (addr, size, copy);
668 5e2a6443 bellard
    dsp->left_till_irq -= written;
669 27503323 bellard
    AUD_adjust_estimate (free - written);
670 27503323 bellard
671 5e2a6443 bellard
    if (dsp->left_till_irq <= 0) {
672 5e2a6443 bellard
        dsp->mixer_regs[0x82] |= dsp->mixer_regs[0x80];
673 bc0b1dc1 bellard
        if (0 == noirq) {
674 bc0b1dc1 bellard
            ldebug ("request irq\n");
675 f9e92e97 bellard
            pic_set_irq(sb.irq, 1);
676 bc0b1dc1 bellard
        }
677 27503323 bellard
678 5e2a6443 bellard
        if (0 == dsp->dma_auto) {
679 27503323 bellard
            control (0);
680 27503323 bellard
        }
681 27503323 bellard
    }
682 27503323 bellard
683 27503323 bellard
    ldebug ("pos %5d free %5d size %5d till % 5d copy %5d dma size %5d\n",
684 5e2a6443 bellard
            dsp->dma_pos, free, size, dsp->left_till_irq, copy,
685 5e2a6443 bellard
            dsp->dma_buffer_size);
686 27503323 bellard
687 5e2a6443 bellard
    if (dsp->left_till_irq <= 0) {
688 5e2a6443 bellard
        dsp->left_till_irq += dsp->dma_buffer_size;
689 27503323 bellard
    }
690 27503323 bellard
691 5e2a6443 bellard
    return dsp->dma_pos;
692 27503323 bellard
}
693 27503323 bellard
694 27503323 bellard
static int magic_of_irq (int irq)
695 27503323 bellard
{
696 27503323 bellard
    switch (irq) {
697 27503323 bellard
    case 2:
698 27503323 bellard
        return 1;
699 27503323 bellard
    case 5:
700 27503323 bellard
        return 2;
701 27503323 bellard
    case 7:
702 27503323 bellard
        return 4;
703 27503323 bellard
    case 10:
704 27503323 bellard
        return 8;
705 27503323 bellard
    default:
706 d329a6fb bellard
        log ("bad irq %d", irq);
707 27503323 bellard
        return 2;
708 27503323 bellard
    }
709 27503323 bellard
}
710 27503323 bellard
711 202a456a bellard
#if 0
712 27503323 bellard
static int irq_of_magic (int magic)
713 27503323 bellard
{
714 27503323 bellard
    switch (magic) {
715 27503323 bellard
    case 1:
716 27503323 bellard
        return 2;
717 27503323 bellard
    case 2:
718 27503323 bellard
        return 5;
719 27503323 bellard
    case 4:
720 27503323 bellard
        return 7;
721 27503323 bellard
    case 8:
722 27503323 bellard
        return 10;
723 27503323 bellard
    default:
724 d329a6fb bellard
        log ("bad irq magic %d", magic);
725 27503323 bellard
        return 2;
726 27503323 bellard
    }
727 27503323 bellard
}
728 202a456a bellard
#endif
729 27503323 bellard
730 27503323 bellard
void SB16_init (void)
731 27503323 bellard
{
732 5e2a6443 bellard
    SB16State *s = &dsp;
733 27503323 bellard
    int i;
734 27503323 bellard
    static const uint8_t dsp_write_ports[] = {0x6, 0xc};
735 27503323 bellard
    static const uint8_t dsp_read_ports[] = {0x6, 0xa, 0xc, 0xd, 0xe, 0xf};
736 27503323 bellard
737 202a456a bellard
    memset(s->mixer_regs, 0xff, sizeof(s->mixer_regs));
738 202a456a bellard
739 5e2a6443 bellard
    s->mixer_regs[0x0e] = ~0;
740 5e2a6443 bellard
    s->mixer_regs[0x80] = magic_of_irq (sb.irq);
741 5e2a6443 bellard
    s->mixer_regs[0x81] = 0x20 | (sb.dma << 1);
742 27503323 bellard
743 27503323 bellard
    for (i = 0x30; i < 0x48; i++) {
744 5e2a6443 bellard
        s->mixer_regs[i] = 0x20;
745 27503323 bellard
    }
746 27503323 bellard
747 27503323 bellard
    for (i = 0; i < LENOFA (dsp_write_ports); i++) {
748 5e2a6443 bellard
        register_ioport_write (sb.port + dsp_write_ports[i], 1, 1, dsp_write, s);
749 27503323 bellard
    }
750 27503323 bellard
751 27503323 bellard
    for (i = 0; i < LENOFA (dsp_read_ports); i++) {
752 5e2a6443 bellard
        register_ioport_read (sb.port + dsp_read_ports[i], 1, 1, dsp_read, s);
753 27503323 bellard
    }
754 27503323 bellard
755 5e2a6443 bellard
    register_ioport_write (sb.port + 0x4, 1, 1, mixer_write_indexb, s);
756 5e2a6443 bellard
    register_ioport_write (sb.port + 0x4, 1, 2, mixer_write_indexw, s);
757 5e2a6443 bellard
    register_ioport_read (sb.port + 0x5, 1, 1, mixer_read, s);
758 5e2a6443 bellard
    register_ioport_write (sb.port + 0x5, 1, 1, mixer_write_datab, s);
759 27503323 bellard
760 5e2a6443 bellard
    DMA_register_channel (sb.hdma, SB_read_DMA, s);
761 5e2a6443 bellard
    DMA_register_channel (sb.dma, SB_read_DMA, s);
762 27503323 bellard
}