Revision 7fa9ae1a hw/macio.c
b/hw/macio.c | ||
---|---|---|
25 | 25 |
#include "hw.h" |
26 | 26 |
#include "ppc_mac.h" |
27 | 27 |
#include "pci.h" |
28 |
#include "escc.h" |
|
28 | 29 |
|
29 | 30 |
typedef struct macio_state_t macio_state_t; |
30 | 31 |
struct macio_state_t { |
... | ... | |
32 | 33 |
int pic_mem_index; |
33 | 34 |
int dbdma_mem_index; |
34 | 35 |
int cuda_mem_index; |
36 |
int escc_mem_index; |
|
35 | 37 |
void *nvram; |
36 | 38 |
int nb_ide; |
37 | 39 |
int ide_mem_index[4]; |
... | ... | |
59 | 61 |
cpu_register_physical_memory(addr + 0x08000, 0x1000, |
60 | 62 |
macio_state->dbdma_mem_index); |
61 | 63 |
} |
64 |
if (macio_state->escc_mem_index >= 0) { |
|
65 |
cpu_register_physical_memory(addr + 0x13000, ESCC_SIZE << 4, |
|
66 |
macio_state->escc_mem_index); |
|
67 |
} |
|
62 | 68 |
if (macio_state->cuda_mem_index >= 0) { |
63 | 69 |
cpu_register_physical_memory(addr + 0x16000, 0x2000, |
64 | 70 |
macio_state->cuda_mem_index); |
... | ... | |
75 | 81 |
|
76 | 82 |
void macio_init (PCIBus *bus, int device_id, int is_oldworld, int pic_mem_index, |
77 | 83 |
int dbdma_mem_index, int cuda_mem_index, void *nvram, |
78 |
int nb_ide, int *ide_mem_index) |
|
84 |
int nb_ide, int *ide_mem_index, int escc_mem_index)
|
|
79 | 85 |
{ |
80 | 86 |
PCIDevice *d; |
81 | 87 |
macio_state_t *macio_state; |
... | ... | |
89 | 95 |
macio_state->pic_mem_index = pic_mem_index; |
90 | 96 |
macio_state->dbdma_mem_index = dbdma_mem_index; |
91 | 97 |
macio_state->cuda_mem_index = cuda_mem_index; |
98 |
macio_state->escc_mem_index = escc_mem_index; |
|
92 | 99 |
macio_state->nvram = nvram; |
93 | 100 |
if (nb_ide > 4) |
94 | 101 |
nb_ide = 4; |
Also available in: Unified diff