root / hw / sun4m.c @ 7fb4fdcf
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1 | 420557e8 | bellard | /*
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2 | ee76f82e | blueswir1 | * QEMU Sun4m & Sun4d & Sun4c System Emulator
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3 | 5fafdf24 | ths | *
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4 | b81b3b10 | bellard | * Copyright (c) 2003-2005 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 420557e8 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 420557e8 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 420557e8 | bellard | * in the Software without restriction, including without limitation the rights
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9 | 420557e8 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 420557e8 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 420557e8 | bellard | * furnished to do so, subject to the following conditions:
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12 | 420557e8 | bellard | *
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13 | 420557e8 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 420557e8 | bellard | * all copies or substantial portions of the Software.
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15 | 420557e8 | bellard | *
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16 | 420557e8 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 420557e8 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 420557e8 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 420557e8 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 420557e8 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 420557e8 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 420557e8 | bellard | * THE SOFTWARE.
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23 | 420557e8 | bellard | */
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24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "qemu-timer.h" |
26 | 87ecb68b | pbrook | #include "sun4m.h" |
27 | 87ecb68b | pbrook | #include "nvram.h" |
28 | 87ecb68b | pbrook | #include "sparc32_dma.h" |
29 | 87ecb68b | pbrook | #include "fdc.h" |
30 | 87ecb68b | pbrook | #include "sysemu.h" |
31 | 87ecb68b | pbrook | #include "net.h" |
32 | 87ecb68b | pbrook | #include "boards.h" |
33 | d2c63fc1 | blueswir1 | #include "firmware_abi.h" |
34 | 8b17de88 | blueswir1 | #include "scsi.h" |
35 | d2c63fc1 | blueswir1 | |
36 | b3a23197 | blueswir1 | //#define DEBUG_IRQ
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37 | 420557e8 | bellard | |
38 | 36cd9210 | blueswir1 | /*
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39 | 36cd9210 | blueswir1 | * Sun4m architecture was used in the following machines:
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40 | 36cd9210 | blueswir1 | *
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41 | 36cd9210 | blueswir1 | * SPARCserver 6xxMP/xx
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42 | 36cd9210 | blueswir1 | * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15), SPARCclassic X (4/10)
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43 | 36cd9210 | blueswir1 | * SPARCstation LX/ZX (4/30)
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44 | 36cd9210 | blueswir1 | * SPARCstation Voyager
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45 | 36cd9210 | blueswir1 | * SPARCstation 10/xx, SPARCserver 10/xx
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46 | 36cd9210 | blueswir1 | * SPARCstation 5, SPARCserver 5
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47 | 36cd9210 | blueswir1 | * SPARCstation 20/xx, SPARCserver 20
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48 | 36cd9210 | blueswir1 | * SPARCstation 4
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49 | 36cd9210 | blueswir1 | *
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50 | 7d85892b | blueswir1 | * Sun4d architecture was used in the following machines:
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51 | 7d85892b | blueswir1 | *
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52 | 7d85892b | blueswir1 | * SPARCcenter 2000
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53 | 7d85892b | blueswir1 | * SPARCserver 1000
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54 | 7d85892b | blueswir1 | *
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55 | ee76f82e | blueswir1 | * Sun4c architecture was used in the following machines:
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56 | ee76f82e | blueswir1 | * SPARCstation 1/1+, SPARCserver 1/1+
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57 | ee76f82e | blueswir1 | * SPARCstation SLC
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58 | ee76f82e | blueswir1 | * SPARCstation IPC
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59 | ee76f82e | blueswir1 | * SPARCstation ELC
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60 | ee76f82e | blueswir1 | * SPARCstation IPX
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61 | ee76f82e | blueswir1 | *
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62 | 36cd9210 | blueswir1 | * See for example: http://www.sunhelp.org/faq/sunref1.html
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63 | 36cd9210 | blueswir1 | */
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64 | 36cd9210 | blueswir1 | |
65 | b3a23197 | blueswir1 | #ifdef DEBUG_IRQ
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66 | b3a23197 | blueswir1 | #define DPRINTF(fmt, args...) \
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67 | b3a23197 | blueswir1 | do { printf("CPUIRQ: " fmt , ##args); } while (0) |
68 | b3a23197 | blueswir1 | #else
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69 | b3a23197 | blueswir1 | #define DPRINTF(fmt, args...)
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70 | b3a23197 | blueswir1 | #endif
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71 | b3a23197 | blueswir1 | |
72 | 420557e8 | bellard | #define KERNEL_LOAD_ADDR 0x00004000 |
73 | b6f479d3 | bellard | #define CMDLINE_ADDR 0x007ff000 |
74 | 713c45fa | bellard | #define INITRD_LOAD_ADDR 0x00800000 |
75 | aa6ad6fe | blueswir1 | #define PROM_SIZE_MAX (512 * 1024) |
76 | 40ce0a9a | blueswir1 | #define PROM_VADDR 0xffd00000 |
77 | f930d07e | blueswir1 | #define PROM_FILENAME "openbios-sparc32" |
78 | b8174937 | bellard | |
79 | ba3c64fb | bellard | #define MAX_CPUS 16 |
80 | b3a23197 | blueswir1 | #define MAX_PILS 16 |
81 | 420557e8 | bellard | |
82 | 36cd9210 | blueswir1 | struct hwdef {
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83 | 5dcb6b91 | blueswir1 | target_phys_addr_t iommu_base, slavio_base; |
84 | 5dcb6b91 | blueswir1 | target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base; |
85 | 5dcb6b91 | blueswir1 | target_phys_addr_t serial_base, fd_base; |
86 | 4c2485de | blueswir1 | target_phys_addr_t idreg_base, dma_base, esp_base, le_base; |
87 | 0019ad53 | blueswir1 | target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base; |
88 | 7eb0c8e8 | blueswir1 | target_phys_addr_t ecc_base; |
89 | 7eb0c8e8 | blueswir1 | uint32_t ecc_version; |
90 | ee76f82e | blueswir1 | target_phys_addr_t sun4c_intctl_base, sun4c_counter_base; |
91 | 36cd9210 | blueswir1 | long vram_size, nvram_size;
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92 | 6341fdcb | blueswir1 | // IRQ numbers are not PIL ones, but master interrupt controller
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93 | e3a79bca | blueswir1 | // register bit numbers
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94 | d7edfd27 | blueswir1 | int intctl_g_intr, esp_irq, le_irq, clock_irq, clock1_irq;
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95 | e42c20b4 | blueswir1 | int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq, ecc_irq;
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96 | 36cd9210 | blueswir1 | int machine_id; // For NVRAM |
97 | 7fbfb139 | blueswir1 | uint32_t iommu_version; |
98 | e0353fe2 | blueswir1 | uint32_t intbit_to_level[32];
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99 | 3ebf5aaf | blueswir1 | uint64_t max_mem; |
100 | 3ebf5aaf | blueswir1 | const char * const default_cpu_model; |
101 | 36cd9210 | blueswir1 | }; |
102 | 36cd9210 | blueswir1 | |
103 | 7d85892b | blueswir1 | #define MAX_IOUNITS 5 |
104 | 7d85892b | blueswir1 | |
105 | 7d85892b | blueswir1 | struct sun4d_hwdef {
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106 | 7d85892b | blueswir1 | target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base; |
107 | 7d85892b | blueswir1 | target_phys_addr_t counter_base, nvram_base, ms_kb_base; |
108 | 7d85892b | blueswir1 | target_phys_addr_t serial_base; |
109 | 7d85892b | blueswir1 | target_phys_addr_t espdma_base, esp_base; |
110 | 7d85892b | blueswir1 | target_phys_addr_t ledma_base, le_base; |
111 | 7d85892b | blueswir1 | target_phys_addr_t tcx_base; |
112 | 7d85892b | blueswir1 | target_phys_addr_t sbi_base; |
113 | 7d85892b | blueswir1 | unsigned long vram_size, nvram_size; |
114 | 7d85892b | blueswir1 | // IRQ numbers are not PIL ones, but SBI register bit numbers
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115 | 7d85892b | blueswir1 | int esp_irq, le_irq, clock_irq, clock1_irq;
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116 | 7d85892b | blueswir1 | int ser_irq, ms_kb_irq, me_irq;
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117 | 7d85892b | blueswir1 | int machine_id; // For NVRAM |
118 | 7d85892b | blueswir1 | uint32_t iounit_version; |
119 | 7d85892b | blueswir1 | uint64_t max_mem; |
120 | 7d85892b | blueswir1 | const char * const default_cpu_model; |
121 | 7d85892b | blueswir1 | }; |
122 | 7d85892b | blueswir1 | |
123 | 420557e8 | bellard | /* TSC handling */
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124 | 420557e8 | bellard | |
125 | 420557e8 | bellard | uint64_t cpu_get_tsc() |
126 | 420557e8 | bellard | { |
127 | 420557e8 | bellard | return qemu_get_clock(vm_clock);
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128 | 420557e8 | bellard | } |
129 | 420557e8 | bellard | |
130 | 6f7e9aec | bellard | int DMA_get_channel_mode (int nchan) |
131 | 6f7e9aec | bellard | { |
132 | 6f7e9aec | bellard | return 0; |
133 | 6f7e9aec | bellard | } |
134 | 6f7e9aec | bellard | int DMA_read_memory (int nchan, void *buf, int pos, int size) |
135 | 6f7e9aec | bellard | { |
136 | 6f7e9aec | bellard | return 0; |
137 | 6f7e9aec | bellard | } |
138 | 6f7e9aec | bellard | int DMA_write_memory (int nchan, void *buf, int pos, int size) |
139 | 6f7e9aec | bellard | { |
140 | 6f7e9aec | bellard | return 0; |
141 | 6f7e9aec | bellard | } |
142 | 6f7e9aec | bellard | void DMA_hold_DREQ (int nchan) {} |
143 | 6f7e9aec | bellard | void DMA_release_DREQ (int nchan) {} |
144 | 6f7e9aec | bellard | void DMA_schedule(int nchan) {} |
145 | 6f7e9aec | bellard | void DMA_run (void) {} |
146 | 6f7e9aec | bellard | void DMA_init (int high_page_enable) {} |
147 | 6f7e9aec | bellard | void DMA_register_channel (int nchan, |
148 | 6f7e9aec | bellard | DMA_transfer_handler transfer_handler, |
149 | 6f7e9aec | bellard | void *opaque)
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150 | 6f7e9aec | bellard | { |
151 | 6f7e9aec | bellard | } |
152 | 6f7e9aec | bellard | |
153 | 6f7e9aec | bellard | extern int nographic; |
154 | 6f7e9aec | bellard | |
155 | 819385c5 | bellard | static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline, |
156 | d2c63fc1 | blueswir1 | const char *boot_devices, uint32_t RAM_size, |
157 | f930d07e | blueswir1 | uint32_t kernel_size, |
158 | f930d07e | blueswir1 | int width, int height, int depth, |
159 | 7d85892b | blueswir1 | int machine_id, const char *arch) |
160 | e80cfcfc | bellard | { |
161 | d2c63fc1 | blueswir1 | unsigned int i; |
162 | 66508601 | blueswir1 | uint32_t start, end; |
163 | d2c63fc1 | blueswir1 | uint8_t image[0x1ff0];
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164 | d2c63fc1 | blueswir1 | ohwcfg_v3_t *header = (ohwcfg_v3_t *)ℑ |
165 | d2c63fc1 | blueswir1 | struct sparc_arch_cfg *sparc_header;
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166 | d2c63fc1 | blueswir1 | struct OpenBIOS_nvpart_v1 *part_header;
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167 | d2c63fc1 | blueswir1 | |
168 | d2c63fc1 | blueswir1 | memset(image, '\0', sizeof(image)); |
169 | e80cfcfc | bellard | |
170 | 6f7e9aec | bellard | // Try to match PPC NVRAM
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171 | d2c63fc1 | blueswir1 | strcpy(header->struct_ident, "QEMU_BIOS");
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172 | d2c63fc1 | blueswir1 | header->struct_version = cpu_to_be32(3); /* structure v3 */ |
173 | d2c63fc1 | blueswir1 | |
174 | d2c63fc1 | blueswir1 | header->nvram_size = cpu_to_be16(0x2000);
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175 | d2c63fc1 | blueswir1 | header->nvram_arch_ptr = cpu_to_be16(sizeof(ohwcfg_v3_t));
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176 | d2c63fc1 | blueswir1 | header->nvram_arch_size = cpu_to_be16(sizeof(struct sparc_arch_cfg)); |
177 | 7d85892b | blueswir1 | strcpy(header->arch, arch); |
178 | d2c63fc1 | blueswir1 | header->nb_cpus = smp_cpus & 0xff;
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179 | d2c63fc1 | blueswir1 | header->RAM0_base = 0;
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180 | d2c63fc1 | blueswir1 | header->RAM0_size = cpu_to_be64((uint64_t)RAM_size); |
181 | d2c63fc1 | blueswir1 | strcpy(header->boot_devices, boot_devices); |
182 | d2c63fc1 | blueswir1 | header->nboot_devices = strlen(boot_devices) & 0xff;
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183 | d2c63fc1 | blueswir1 | header->kernel_image = cpu_to_be64((uint64_t)KERNEL_LOAD_ADDR); |
184 | d2c63fc1 | blueswir1 | header->kernel_size = cpu_to_be64((uint64_t)kernel_size); |
185 | b6f479d3 | bellard | if (cmdline) {
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186 | f930d07e | blueswir1 | strcpy(phys_ram_base + CMDLINE_ADDR, cmdline); |
187 | d2c63fc1 | blueswir1 | header->cmdline = cpu_to_be64((uint64_t)CMDLINE_ADDR); |
188 | d2c63fc1 | blueswir1 | header->cmdline_size = cpu_to_be64((uint64_t)strlen(cmdline)); |
189 | b6f479d3 | bellard | } |
190 | d2c63fc1 | blueswir1 | // XXX add initrd_image, initrd_size
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191 | d2c63fc1 | blueswir1 | header->width = cpu_to_be16(width); |
192 | d2c63fc1 | blueswir1 | header->height = cpu_to_be16(height); |
193 | d2c63fc1 | blueswir1 | header->depth = cpu_to_be16(depth); |
194 | d2c63fc1 | blueswir1 | if (nographic)
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195 | d2c63fc1 | blueswir1 | header->graphic_flags = cpu_to_be16(OHW_GF_NOGRAPHICS); |
196 | d2c63fc1 | blueswir1 | |
197 | d2c63fc1 | blueswir1 | header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8)); |
198 | d2c63fc1 | blueswir1 | |
199 | d2c63fc1 | blueswir1 | // Architecture specific header
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200 | d2c63fc1 | blueswir1 | start = sizeof(ohwcfg_v3_t);
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201 | d2c63fc1 | blueswir1 | sparc_header = (struct sparc_arch_cfg *)&image[start];
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202 | d2c63fc1 | blueswir1 | sparc_header->valid = 0;
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203 | d2c63fc1 | blueswir1 | start += sizeof(struct sparc_arch_cfg); |
204 | b6f479d3 | bellard | |
205 | 66508601 | blueswir1 | // OpenBIOS nvram variables
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206 | 66508601 | blueswir1 | // Variable partition
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207 | d2c63fc1 | blueswir1 | part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
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208 | d2c63fc1 | blueswir1 | part_header->signature = OPENBIOS_PART_SYSTEM; |
209 | d2c63fc1 | blueswir1 | strcpy(part_header->name, "system");
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210 | 66508601 | blueswir1 | |
211 | d2c63fc1 | blueswir1 | end = start + sizeof(struct OpenBIOS_nvpart_v1); |
212 | 66508601 | blueswir1 | for (i = 0; i < nb_prom_envs; i++) |
213 | d2c63fc1 | blueswir1 | end = OpenBIOS_set_var(image, end, prom_envs[i]); |
214 | d2c63fc1 | blueswir1 | |
215 | d2c63fc1 | blueswir1 | // End marker
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216 | d2c63fc1 | blueswir1 | image[end++] = '\0';
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217 | 66508601 | blueswir1 | |
218 | 66508601 | blueswir1 | end = start + ((end - start + 15) & ~15); |
219 | d2c63fc1 | blueswir1 | OpenBIOS_finish_partition(part_header, end - start); |
220 | 66508601 | blueswir1 | |
221 | 66508601 | blueswir1 | // free partition
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222 | 66508601 | blueswir1 | start = end; |
223 | d2c63fc1 | blueswir1 | part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
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224 | d2c63fc1 | blueswir1 | part_header->signature = OPENBIOS_PART_FREE; |
225 | d2c63fc1 | blueswir1 | strcpy(part_header->name, "free");
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226 | 66508601 | blueswir1 | |
227 | 66508601 | blueswir1 | end = 0x1fd0;
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228 | d2c63fc1 | blueswir1 | OpenBIOS_finish_partition(part_header, end - start); |
229 | d2c63fc1 | blueswir1 | |
230 | d2c63fc1 | blueswir1 | Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, machine_id); |
231 | d2c63fc1 | blueswir1 | |
232 | d2c63fc1 | blueswir1 | for (i = 0; i < sizeof(image); i++) |
233 | d2c63fc1 | blueswir1 | m48t59_write(nvram, i, image[i]); |
234 | e80cfcfc | bellard | } |
235 | e80cfcfc | bellard | |
236 | e80cfcfc | bellard | static void *slavio_intctl; |
237 | e80cfcfc | bellard | |
238 | e80cfcfc | bellard | void pic_info()
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239 | e80cfcfc | bellard | { |
240 | 7d85892b | blueswir1 | if (slavio_intctl)
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241 | 7d85892b | blueswir1 | slavio_pic_info(slavio_intctl); |
242 | e80cfcfc | bellard | } |
243 | e80cfcfc | bellard | |
244 | e80cfcfc | bellard | void irq_info()
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245 | e80cfcfc | bellard | { |
246 | 7d85892b | blueswir1 | if (slavio_intctl)
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247 | 7d85892b | blueswir1 | slavio_irq_info(slavio_intctl); |
248 | e80cfcfc | bellard | } |
249 | e80cfcfc | bellard | |
250 | 327ac2e7 | blueswir1 | void cpu_check_irqs(CPUState *env)
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251 | 327ac2e7 | blueswir1 | { |
252 | 327ac2e7 | blueswir1 | if (env->pil_in && (env->interrupt_index == 0 || |
253 | 327ac2e7 | blueswir1 | (env->interrupt_index & ~15) == TT_EXTINT)) {
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254 | 327ac2e7 | blueswir1 | unsigned int i; |
255 | 327ac2e7 | blueswir1 | |
256 | 327ac2e7 | blueswir1 | for (i = 15; i > 0; i--) { |
257 | 327ac2e7 | blueswir1 | if (env->pil_in & (1 << i)) { |
258 | 327ac2e7 | blueswir1 | int old_interrupt = env->interrupt_index;
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259 | 327ac2e7 | blueswir1 | |
260 | 327ac2e7 | blueswir1 | env->interrupt_index = TT_EXTINT | i; |
261 | f32d7ec5 | blueswir1 | if (old_interrupt != env->interrupt_index) {
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262 | f32d7ec5 | blueswir1 | DPRINTF("Set CPU IRQ %d\n", i);
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263 | 327ac2e7 | blueswir1 | cpu_interrupt(env, CPU_INTERRUPT_HARD); |
264 | f32d7ec5 | blueswir1 | } |
265 | 327ac2e7 | blueswir1 | break;
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266 | 327ac2e7 | blueswir1 | } |
267 | 327ac2e7 | blueswir1 | } |
268 | 327ac2e7 | blueswir1 | } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) { |
269 | f32d7ec5 | blueswir1 | DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15); |
270 | 327ac2e7 | blueswir1 | env->interrupt_index = 0;
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271 | 327ac2e7 | blueswir1 | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
272 | 327ac2e7 | blueswir1 | } |
273 | 327ac2e7 | blueswir1 | } |
274 | 327ac2e7 | blueswir1 | |
275 | b3a23197 | blueswir1 | static void cpu_set_irq(void *opaque, int irq, int level) |
276 | b3a23197 | blueswir1 | { |
277 | b3a23197 | blueswir1 | CPUState *env = opaque; |
278 | b3a23197 | blueswir1 | |
279 | b3a23197 | blueswir1 | if (level) {
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280 | b3a23197 | blueswir1 | DPRINTF("Raise CPU IRQ %d\n", irq);
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281 | b3a23197 | blueswir1 | env->halted = 0;
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282 | 327ac2e7 | blueswir1 | env->pil_in |= 1 << irq;
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283 | 327ac2e7 | blueswir1 | cpu_check_irqs(env); |
284 | b3a23197 | blueswir1 | } else {
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285 | b3a23197 | blueswir1 | DPRINTF("Lower CPU IRQ %d\n", irq);
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286 | 327ac2e7 | blueswir1 | env->pil_in &= ~(1 << irq);
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287 | 327ac2e7 | blueswir1 | cpu_check_irqs(env); |
288 | b3a23197 | blueswir1 | } |
289 | b3a23197 | blueswir1 | } |
290 | b3a23197 | blueswir1 | |
291 | b3a23197 | blueswir1 | static void dummy_cpu_set_irq(void *opaque, int irq, int level) |
292 | b3a23197 | blueswir1 | { |
293 | b3a23197 | blueswir1 | } |
294 | b3a23197 | blueswir1 | |
295 | 3475187d | bellard | static void *slavio_misc; |
296 | 3475187d | bellard | |
297 | 3475187d | bellard | void qemu_system_powerdown(void) |
298 | 3475187d | bellard | { |
299 | 3475187d | bellard | slavio_set_power_fail(slavio_misc, 1);
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300 | 3475187d | bellard | } |
301 | 3475187d | bellard | |
302 | c68ea704 | bellard | static void main_cpu_reset(void *opaque) |
303 | c68ea704 | bellard | { |
304 | c68ea704 | bellard | CPUState *env = opaque; |
305 | 3d29fbef | blueswir1 | |
306 | 3d29fbef | blueswir1 | cpu_reset(env); |
307 | 3d29fbef | blueswir1 | env->halted = 0;
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308 | 3d29fbef | blueswir1 | } |
309 | 3d29fbef | blueswir1 | |
310 | 3d29fbef | blueswir1 | static void secondary_cpu_reset(void *opaque) |
311 | 3d29fbef | blueswir1 | { |
312 | 3d29fbef | blueswir1 | CPUState *env = opaque; |
313 | 3d29fbef | blueswir1 | |
314 | c68ea704 | bellard | cpu_reset(env); |
315 | 3d29fbef | blueswir1 | env->halted = 1;
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316 | c68ea704 | bellard | } |
317 | c68ea704 | bellard | |
318 | 3ebf5aaf | blueswir1 | static unsigned long sun4m_load_kernel(const char *kernel_filename, |
319 | 3ebf5aaf | blueswir1 | const char *kernel_cmdline, |
320 | 3ebf5aaf | blueswir1 | const char *initrd_filename) |
321 | 3ebf5aaf | blueswir1 | { |
322 | 3ebf5aaf | blueswir1 | int linux_boot;
|
323 | 3ebf5aaf | blueswir1 | unsigned int i; |
324 | 3ebf5aaf | blueswir1 | long initrd_size, kernel_size;
|
325 | 3ebf5aaf | blueswir1 | |
326 | 3ebf5aaf | blueswir1 | linux_boot = (kernel_filename != NULL);
|
327 | 3ebf5aaf | blueswir1 | |
328 | 3ebf5aaf | blueswir1 | kernel_size = 0;
|
329 | 3ebf5aaf | blueswir1 | if (linux_boot) {
|
330 | 3ebf5aaf | blueswir1 | kernel_size = load_elf(kernel_filename, -0xf0000000ULL, NULL, NULL, |
331 | 3ebf5aaf | blueswir1 | NULL);
|
332 | 3ebf5aaf | blueswir1 | if (kernel_size < 0) |
333 | 3ebf5aaf | blueswir1 | kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); |
334 | 3ebf5aaf | blueswir1 | if (kernel_size < 0) |
335 | 3ebf5aaf | blueswir1 | kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); |
336 | 3ebf5aaf | blueswir1 | if (kernel_size < 0) { |
337 | 3ebf5aaf | blueswir1 | fprintf(stderr, "qemu: could not load kernel '%s'\n",
|
338 | 3ebf5aaf | blueswir1 | kernel_filename); |
339 | 3ebf5aaf | blueswir1 | exit(1);
|
340 | 3ebf5aaf | blueswir1 | } |
341 | 3ebf5aaf | blueswir1 | |
342 | 3ebf5aaf | blueswir1 | /* load initrd */
|
343 | 3ebf5aaf | blueswir1 | initrd_size = 0;
|
344 | 3ebf5aaf | blueswir1 | if (initrd_filename) {
|
345 | 3ebf5aaf | blueswir1 | initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR); |
346 | 3ebf5aaf | blueswir1 | if (initrd_size < 0) { |
347 | 3ebf5aaf | blueswir1 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
|
348 | 3ebf5aaf | blueswir1 | initrd_filename); |
349 | 3ebf5aaf | blueswir1 | exit(1);
|
350 | 3ebf5aaf | blueswir1 | } |
351 | 3ebf5aaf | blueswir1 | } |
352 | 3ebf5aaf | blueswir1 | if (initrd_size > 0) { |
353 | 3ebf5aaf | blueswir1 | for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { |
354 | 3ebf5aaf | blueswir1 | if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i)
|
355 | 3ebf5aaf | blueswir1 | == 0x48647253) { // HdrS |
356 | 3ebf5aaf | blueswir1 | stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
|
357 | 3ebf5aaf | blueswir1 | stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size);
|
358 | 3ebf5aaf | blueswir1 | break;
|
359 | 3ebf5aaf | blueswir1 | } |
360 | 3ebf5aaf | blueswir1 | } |
361 | 3ebf5aaf | blueswir1 | } |
362 | 3ebf5aaf | blueswir1 | } |
363 | 3ebf5aaf | blueswir1 | return kernel_size;
|
364 | 3ebf5aaf | blueswir1 | } |
365 | 3ebf5aaf | blueswir1 | |
366 | 3ebf5aaf | blueswir1 | static void sun4m_hw_init(const struct hwdef *hwdef, int RAM_size, |
367 | 3ebf5aaf | blueswir1 | const char *boot_device, |
368 | 3ebf5aaf | blueswir1 | DisplayState *ds, const char *kernel_filename, |
369 | 3ebf5aaf | blueswir1 | const char *kernel_cmdline, |
370 | 3ebf5aaf | blueswir1 | const char *initrd_filename, const char *cpu_model) |
371 | 36cd9210 | blueswir1 | |
372 | 420557e8 | bellard | { |
373 | ba3c64fb | bellard | CPUState *env, *envs[MAX_CPUS]; |
374 | 713c45fa | bellard | unsigned int i; |
375 | b3ceef24 | blueswir1 | void *iommu, *espdma, *ledma, *main_esp, *nvram;
|
376 | b3a23197 | blueswir1 | qemu_irq *cpu_irqs[MAX_CPUS], *slavio_irq, *slavio_cpu_irq, |
377 | d7edfd27 | blueswir1 | *espdma_irq, *ledma_irq; |
378 | 2d069bab | blueswir1 | qemu_irq *esp_reset, *le_reset; |
379 | 2be17ebd | blueswir1 | qemu_irq *fdc_tc; |
380 | 3ebf5aaf | blueswir1 | unsigned long prom_offset, kernel_size; |
381 | 3ebf5aaf | blueswir1 | int ret;
|
382 | 3ebf5aaf | blueswir1 | char buf[1024]; |
383 | e4bcb14c | ths | BlockDriverState *fd[MAX_FD]; |
384 | e4bcb14c | ths | int index;
|
385 | 420557e8 | bellard | |
386 | ba3c64fb | bellard | /* init CPUs */
|
387 | 3ebf5aaf | blueswir1 | if (!cpu_model)
|
388 | 3ebf5aaf | blueswir1 | cpu_model = hwdef->default_cpu_model; |
389 | b3a23197 | blueswir1 | |
390 | ba3c64fb | bellard | for(i = 0; i < smp_cpus; i++) { |
391 | aaed909a | bellard | env = cpu_init(cpu_model); |
392 | aaed909a | bellard | if (!env) {
|
393 | 8e82c6a8 | blueswir1 | fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
|
394 | aaed909a | bellard | exit(1);
|
395 | aaed909a | bellard | } |
396 | aaed909a | bellard | cpu_sparc_set_id(env, i); |
397 | ba3c64fb | bellard | envs[i] = env; |
398 | 3d29fbef | blueswir1 | if (i == 0) { |
399 | 3d29fbef | blueswir1 | qemu_register_reset(main_cpu_reset, env); |
400 | 3d29fbef | blueswir1 | } else {
|
401 | 3d29fbef | blueswir1 | qemu_register_reset(secondary_cpu_reset, env); |
402 | ba3c64fb | bellard | env->halted = 1;
|
403 | 3d29fbef | blueswir1 | } |
404 | ba3c64fb | bellard | register_savevm("cpu", i, 3, cpu_save, cpu_load, env); |
405 | b3a23197 | blueswir1 | cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS); |
406 | 3ebf5aaf | blueswir1 | env->prom_addr = hwdef->slavio_base; |
407 | ba3c64fb | bellard | } |
408 | b3a23197 | blueswir1 | |
409 | b3a23197 | blueswir1 | for (i = smp_cpus; i < MAX_CPUS; i++)
|
410 | b3a23197 | blueswir1 | cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
|
411 | b3a23197 | blueswir1 | |
412 | 3ebf5aaf | blueswir1 | |
413 | 420557e8 | bellard | /* allocate RAM */
|
414 | 3ebf5aaf | blueswir1 | if ((uint64_t)RAM_size > hwdef->max_mem) {
|
415 | 3ebf5aaf | blueswir1 | fprintf(stderr, "qemu: Too much memory for this machine: %d, maximum %d\n",
|
416 | 3ebf5aaf | blueswir1 | (unsigned int)RAM_size / (1024 * 1024), |
417 | 3ebf5aaf | blueswir1 | (unsigned int)(hwdef->max_mem / (1024 * 1024))); |
418 | 3ebf5aaf | blueswir1 | exit(1);
|
419 | 3ebf5aaf | blueswir1 | } |
420 | b3ceef24 | blueswir1 | cpu_register_physical_memory(0, RAM_size, 0); |
421 | 420557e8 | bellard | |
422 | 3ebf5aaf | blueswir1 | /* load boot prom */
|
423 | 3ebf5aaf | blueswir1 | prom_offset = RAM_size + hwdef->vram_size; |
424 | 3ebf5aaf | blueswir1 | cpu_register_physical_memory(hwdef->slavio_base, |
425 | 3ebf5aaf | blueswir1 | (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
|
426 | 3ebf5aaf | blueswir1 | TARGET_PAGE_MASK, |
427 | 3ebf5aaf | blueswir1 | prom_offset | IO_MEM_ROM); |
428 | 3ebf5aaf | blueswir1 | |
429 | 3ebf5aaf | blueswir1 | if (bios_name == NULL) |
430 | 3ebf5aaf | blueswir1 | bios_name = PROM_FILENAME; |
431 | 3ebf5aaf | blueswir1 | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); |
432 | 3ebf5aaf | blueswir1 | ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL); |
433 | 3ebf5aaf | blueswir1 | if (ret < 0 || ret > PROM_SIZE_MAX) |
434 | 3ebf5aaf | blueswir1 | ret = load_image(buf, phys_ram_base + prom_offset); |
435 | 3ebf5aaf | blueswir1 | if (ret < 0 || ret > PROM_SIZE_MAX) { |
436 | 3ebf5aaf | blueswir1 | fprintf(stderr, "qemu: could not load prom '%s'\n",
|
437 | 3ebf5aaf | blueswir1 | buf); |
438 | 3ebf5aaf | blueswir1 | exit(1);
|
439 | 3ebf5aaf | blueswir1 | } |
440 | 4c2485de | blueswir1 | prom_offset += (ret + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
|
441 | 3ebf5aaf | blueswir1 | |
442 | 3ebf5aaf | blueswir1 | /* set up devices */
|
443 | 36cd9210 | blueswir1 | slavio_intctl = slavio_intctl_init(hwdef->intctl_base, |
444 | 5dcb6b91 | blueswir1 | hwdef->intctl_base + 0x10000ULL,
|
445 | d537cf6c | pbrook | &hwdef->intbit_to_level[0],
|
446 | d7edfd27 | blueswir1 | &slavio_irq, &slavio_cpu_irq, |
447 | b3a23197 | blueswir1 | cpu_irqs, |
448 | d7edfd27 | blueswir1 | hwdef->clock_irq); |
449 | b3a23197 | blueswir1 | |
450 | 4c2485de | blueswir1 | if (hwdef->idreg_base != (target_phys_addr_t)-1) { |
451 | 4c2485de | blueswir1 | stl_raw(phys_ram_base + prom_offset, 0xfe810103);
|
452 | 4c2485de | blueswir1 | |
453 | 4c2485de | blueswir1 | cpu_register_physical_memory(hwdef->idreg_base, sizeof(uint32_t),
|
454 | 4c2485de | blueswir1 | prom_offset | IO_MEM_ROM); |
455 | 4c2485de | blueswir1 | } |
456 | 4c2485de | blueswir1 | |
457 | ff403da6 | blueswir1 | iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version, |
458 | ff403da6 | blueswir1 | slavio_irq[hwdef->me_irq]); |
459 | ff403da6 | blueswir1 | |
460 | 5aca8c3b | blueswir1 | espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq], |
461 | 2d069bab | blueswir1 | iommu, &espdma_irq, &esp_reset); |
462 | 2d069bab | blueswir1 | |
463 | 5aca8c3b | blueswir1 | ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
|
464 | 2d069bab | blueswir1 | slavio_irq[hwdef->le_irq], iommu, &ledma_irq, |
465 | 2d069bab | blueswir1 | &le_reset); |
466 | ba3c64fb | bellard | |
467 | eee0b836 | blueswir1 | if (graphic_depth != 8 && graphic_depth != 24) { |
468 | eee0b836 | blueswir1 | fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
|
469 | eee0b836 | blueswir1 | exit (1);
|
470 | eee0b836 | blueswir1 | } |
471 | b3ceef24 | blueswir1 | tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size, |
472 | eee0b836 | blueswir1 | hwdef->vram_size, graphic_width, graphic_height, graphic_depth); |
473 | dbe06e18 | blueswir1 | |
474 | dbe06e18 | blueswir1 | if (nd_table[0].model == NULL |
475 | dbe06e18 | blueswir1 | || strcmp(nd_table[0].model, "lance") == 0) { |
476 | 2d069bab | blueswir1 | lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
|
477 | c4a7060c | blueswir1 | } else if (strcmp(nd_table[0].model, "?") == 0) { |
478 | c4a7060c | blueswir1 | fprintf(stderr, "qemu: Supported NICs: lance\n");
|
479 | c4a7060c | blueswir1 | exit (1);
|
480 | dbe06e18 | blueswir1 | } else {
|
481 | dbe06e18 | blueswir1 | fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model); |
482 | dbe06e18 | blueswir1 | exit (1);
|
483 | a41b2ff2 | pbrook | } |
484 | dbe06e18 | blueswir1 | |
485 | d537cf6c | pbrook | nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, |
486 | d537cf6c | pbrook | hwdef->nvram_size, 8);
|
487 | 81732d19 | blueswir1 | |
488 | 81732d19 | blueswir1 | slavio_timer_init_all(hwdef->counter_base, slavio_irq[hwdef->clock1_irq], |
489 | 19f8e5dd | blueswir1 | slavio_cpu_irq, smp_cpus); |
490 | 81732d19 | blueswir1 | |
491 | 577390ff | blueswir1 | slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq], |
492 | 577390ff | blueswir1 | nographic); |
493 | b81b3b10 | bellard | // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
|
494 | b81b3b10 | bellard | // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
|
495 | d537cf6c | pbrook | slavio_serial_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq], |
496 | d537cf6c | pbrook | serial_hds[1], serial_hds[0]); |
497 | 741402f9 | blueswir1 | |
498 | 2be17ebd | blueswir1 | slavio_misc = slavio_misc_init(hwdef->slavio_base, hwdef->apc_base, |
499 | 2be17ebd | blueswir1 | hwdef->aux1_base, hwdef->aux2_base, |
500 | 2be17ebd | blueswir1 | slavio_irq[hwdef->me_irq], envs[0],
|
501 | 2be17ebd | blueswir1 | &fdc_tc); |
502 | 2be17ebd | blueswir1 | |
503 | e4bcb14c | ths | if (hwdef->fd_base != (target_phys_addr_t)-1) { |
504 | e4bcb14c | ths | /* there is zero or one floppy drive */
|
505 | 309e60bd | blueswir1 | memset(fd, 0, sizeof(fd)); |
506 | e4bcb14c | ths | index = drive_get_index(IF_FLOPPY, 0, 0); |
507 | e4bcb14c | ths | if (index != -1) |
508 | e4bcb14c | ths | fd[0] = drives_table[index].bdrv;
|
509 | 2d069bab | blueswir1 | |
510 | 2be17ebd | blueswir1 | sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd, |
511 | 2be17ebd | blueswir1 | fdc_tc); |
512 | e4bcb14c | ths | } |
513 | e4bcb14c | ths | |
514 | e4bcb14c | ths | if (drive_get_max_bus(IF_SCSI) > 0) { |
515 | e4bcb14c | ths | fprintf(stderr, "qemu: too many SCSI bus\n");
|
516 | e4bcb14c | ths | exit(1);
|
517 | e4bcb14c | ths | } |
518 | e4bcb14c | ths | |
519 | 5d20fa6b | blueswir1 | main_esp = esp_init(hwdef->esp_base, 2,
|
520 | 8b17de88 | blueswir1 | espdma_memory_read, espdma_memory_write, |
521 | 8b17de88 | blueswir1 | espdma, *espdma_irq, esp_reset); |
522 | f1587550 | ths | |
523 | e4bcb14c | ths | for (i = 0; i < ESP_MAX_DEVS; i++) { |
524 | e4bcb14c | ths | index = drive_get_index(IF_SCSI, 0, i);
|
525 | e4bcb14c | ths | if (index == -1) |
526 | e4bcb14c | ths | continue;
|
527 | e4bcb14c | ths | esp_scsi_attach(main_esp, drives_table[index].bdrv, i); |
528 | f1587550 | ths | } |
529 | f1587550 | ths | |
530 | 5dcb6b91 | blueswir1 | if (hwdef->cs_base != (target_phys_addr_t)-1) |
531 | 803b3c7b | blueswir1 | cs_init(hwdef->cs_base, hwdef->cs_irq, slavio_intctl); |
532 | b3ceef24 | blueswir1 | |
533 | 3ebf5aaf | blueswir1 | kernel_size = sun4m_load_kernel(kernel_filename, kernel_cmdline, |
534 | 3ebf5aaf | blueswir1 | initrd_filename); |
535 | 36cd9210 | blueswir1 | |
536 | 36cd9210 | blueswir1 | nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
|
537 | b3ceef24 | blueswir1 | boot_device, RAM_size, kernel_size, graphic_width, |
538 | 7d85892b | blueswir1 | graphic_height, graphic_depth, hwdef->machine_id, "Sun4m");
|
539 | 7eb0c8e8 | blueswir1 | |
540 | 7eb0c8e8 | blueswir1 | if (hwdef->ecc_base != (target_phys_addr_t)-1) |
541 | e42c20b4 | blueswir1 | ecc_init(hwdef->ecc_base, slavio_irq[hwdef->ecc_irq], |
542 | e42c20b4 | blueswir1 | hwdef->ecc_version); |
543 | 36cd9210 | blueswir1 | } |
544 | 36cd9210 | blueswir1 | |
545 | ee76f82e | blueswir1 | static void sun4c_hw_init(const struct hwdef *hwdef, int RAM_size, |
546 | ee76f82e | blueswir1 | const char *boot_device, |
547 | ee76f82e | blueswir1 | DisplayState *ds, const char *kernel_filename, |
548 | ee76f82e | blueswir1 | const char *kernel_cmdline, |
549 | ee76f82e | blueswir1 | const char *initrd_filename, const char *cpu_model) |
550 | ee76f82e | blueswir1 | { |
551 | ee76f82e | blueswir1 | CPUState *env; |
552 | ee76f82e | blueswir1 | unsigned int i; |
553 | ee76f82e | blueswir1 | void *iommu, *espdma, *ledma, *main_esp, *nvram;
|
554 | ee76f82e | blueswir1 | qemu_irq *cpu_irqs, *slavio_irq, *espdma_irq, *ledma_irq; |
555 | ee76f82e | blueswir1 | qemu_irq *esp_reset, *le_reset; |
556 | 2be17ebd | blueswir1 | qemu_irq *fdc_tc; |
557 | ee76f82e | blueswir1 | unsigned long prom_offset, kernel_size; |
558 | ee76f82e | blueswir1 | int ret;
|
559 | ee76f82e | blueswir1 | char buf[1024]; |
560 | ee76f82e | blueswir1 | BlockDriverState *fd[MAX_FD]; |
561 | ee76f82e | blueswir1 | int index;
|
562 | ee76f82e | blueswir1 | |
563 | ee76f82e | blueswir1 | /* init CPU */
|
564 | ee76f82e | blueswir1 | if (!cpu_model)
|
565 | ee76f82e | blueswir1 | cpu_model = hwdef->default_cpu_model; |
566 | ee76f82e | blueswir1 | |
567 | ee76f82e | blueswir1 | env = cpu_init(cpu_model); |
568 | ee76f82e | blueswir1 | if (!env) {
|
569 | 8e82c6a8 | blueswir1 | fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
|
570 | ee76f82e | blueswir1 | exit(1);
|
571 | ee76f82e | blueswir1 | } |
572 | ee76f82e | blueswir1 | |
573 | ee76f82e | blueswir1 | cpu_sparc_set_id(env, 0);
|
574 | ee76f82e | blueswir1 | |
575 | ee76f82e | blueswir1 | qemu_register_reset(main_cpu_reset, env); |
576 | ee76f82e | blueswir1 | register_savevm("cpu", 0, 3, cpu_save, cpu_load, env); |
577 | ee76f82e | blueswir1 | cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS); |
578 | cebb73aa | blueswir1 | env->prom_addr = hwdef->slavio_base; |
579 | ee76f82e | blueswir1 | |
580 | ee76f82e | blueswir1 | /* allocate RAM */
|
581 | ee76f82e | blueswir1 | if ((uint64_t)RAM_size > hwdef->max_mem) {
|
582 | ee76f82e | blueswir1 | fprintf(stderr, "qemu: Too much memory for this machine: %d, maximum %d\n",
|
583 | ee76f82e | blueswir1 | (unsigned int)RAM_size / (1024 * 1024), |
584 | ee76f82e | blueswir1 | (unsigned int)hwdef->max_mem / (1024 * 1024)); |
585 | ee76f82e | blueswir1 | exit(1);
|
586 | ee76f82e | blueswir1 | } |
587 | ee76f82e | blueswir1 | cpu_register_physical_memory(0, RAM_size, 0); |
588 | ee76f82e | blueswir1 | |
589 | ee76f82e | blueswir1 | /* load boot prom */
|
590 | ee76f82e | blueswir1 | prom_offset = RAM_size + hwdef->vram_size; |
591 | ee76f82e | blueswir1 | cpu_register_physical_memory(hwdef->slavio_base, |
592 | ee76f82e | blueswir1 | (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
|
593 | ee76f82e | blueswir1 | TARGET_PAGE_MASK, |
594 | ee76f82e | blueswir1 | prom_offset | IO_MEM_ROM); |
595 | ee76f82e | blueswir1 | |
596 | ee76f82e | blueswir1 | if (bios_name == NULL) |
597 | ee76f82e | blueswir1 | bios_name = PROM_FILENAME; |
598 | ee76f82e | blueswir1 | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); |
599 | ee76f82e | blueswir1 | ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL); |
600 | ee76f82e | blueswir1 | if (ret < 0 || ret > PROM_SIZE_MAX) |
601 | ee76f82e | blueswir1 | ret = load_image(buf, phys_ram_base + prom_offset); |
602 | ee76f82e | blueswir1 | if (ret < 0 || ret > PROM_SIZE_MAX) { |
603 | ee76f82e | blueswir1 | fprintf(stderr, "qemu: could not load prom '%s'\n",
|
604 | ee76f82e | blueswir1 | buf); |
605 | ee76f82e | blueswir1 | exit(1);
|
606 | ee76f82e | blueswir1 | } |
607 | ee76f82e | blueswir1 | prom_offset += (ret + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
|
608 | ee76f82e | blueswir1 | |
609 | ee76f82e | blueswir1 | /* set up devices */
|
610 | ee76f82e | blueswir1 | slavio_intctl = sun4c_intctl_init(hwdef->sun4c_intctl_base, |
611 | ee76f82e | blueswir1 | &slavio_irq, cpu_irqs); |
612 | ee76f82e | blueswir1 | |
613 | ff403da6 | blueswir1 | iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version, |
614 | ff403da6 | blueswir1 | slavio_irq[hwdef->me_irq]); |
615 | ee76f82e | blueswir1 | |
616 | ee76f82e | blueswir1 | espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq], |
617 | ee76f82e | blueswir1 | iommu, &espdma_irq, &esp_reset); |
618 | ee76f82e | blueswir1 | |
619 | ee76f82e | blueswir1 | ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
|
620 | ee76f82e | blueswir1 | slavio_irq[hwdef->le_irq], iommu, &ledma_irq, |
621 | ee76f82e | blueswir1 | &le_reset); |
622 | ee76f82e | blueswir1 | |
623 | ee76f82e | blueswir1 | if (graphic_depth != 8 && graphic_depth != 24) { |
624 | ee76f82e | blueswir1 | fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
|
625 | ee76f82e | blueswir1 | exit (1);
|
626 | ee76f82e | blueswir1 | } |
627 | ee76f82e | blueswir1 | tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size, |
628 | ee76f82e | blueswir1 | hwdef->vram_size, graphic_width, graphic_height, graphic_depth); |
629 | ee76f82e | blueswir1 | |
630 | ee76f82e | blueswir1 | if (nd_table[0].model == NULL |
631 | ee76f82e | blueswir1 | || strcmp(nd_table[0].model, "lance") == 0) { |
632 | ee76f82e | blueswir1 | lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
|
633 | ee76f82e | blueswir1 | } else if (strcmp(nd_table[0].model, "?") == 0) { |
634 | ee76f82e | blueswir1 | fprintf(stderr, "qemu: Supported NICs: lance\n");
|
635 | ee76f82e | blueswir1 | exit (1);
|
636 | ee76f82e | blueswir1 | } else {
|
637 | ee76f82e | blueswir1 | fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model); |
638 | ee76f82e | blueswir1 | exit (1);
|
639 | ee76f82e | blueswir1 | } |
640 | ee76f82e | blueswir1 | |
641 | ee76f82e | blueswir1 | nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, |
642 | 4aed2c33 | blueswir1 | hwdef->nvram_size, 2);
|
643 | ee76f82e | blueswir1 | |
644 | ee76f82e | blueswir1 | slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq], |
645 | ee76f82e | blueswir1 | nographic); |
646 | ee76f82e | blueswir1 | // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
|
647 | ee76f82e | blueswir1 | // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
|
648 | ee76f82e | blueswir1 | slavio_serial_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq], |
649 | ee76f82e | blueswir1 | serial_hds[1], serial_hds[0]); |
650 | ee76f82e | blueswir1 | |
651 | 2be17ebd | blueswir1 | slavio_misc = slavio_misc_init(-1, hwdef->apc_base,
|
652 | 2be17ebd | blueswir1 | hwdef->aux1_base, hwdef->aux2_base, |
653 | 2be17ebd | blueswir1 | slavio_irq[hwdef->me_irq], env, &fdc_tc); |
654 | 2be17ebd | blueswir1 | |
655 | ee76f82e | blueswir1 | if (hwdef->fd_base != (target_phys_addr_t)-1) { |
656 | ee76f82e | blueswir1 | /* there is zero or one floppy drive */
|
657 | ee76f82e | blueswir1 | fd[1] = fd[0] = NULL; |
658 | ee76f82e | blueswir1 | index = drive_get_index(IF_FLOPPY, 0, 0); |
659 | ee76f82e | blueswir1 | if (index != -1) |
660 | ee76f82e | blueswir1 | fd[0] = drives_table[index].bdrv;
|
661 | ee76f82e | blueswir1 | |
662 | 2be17ebd | blueswir1 | sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd, |
663 | 2be17ebd | blueswir1 | fdc_tc); |
664 | ee76f82e | blueswir1 | } |
665 | ee76f82e | blueswir1 | |
666 | ee76f82e | blueswir1 | if (drive_get_max_bus(IF_SCSI) > 0) { |
667 | ee76f82e | blueswir1 | fprintf(stderr, "qemu: too many SCSI bus\n");
|
668 | ee76f82e | blueswir1 | exit(1);
|
669 | ee76f82e | blueswir1 | } |
670 | ee76f82e | blueswir1 | |
671 | 5d20fa6b | blueswir1 | main_esp = esp_init(hwdef->esp_base, 2,
|
672 | 8b17de88 | blueswir1 | espdma_memory_read, espdma_memory_write, |
673 | 8b17de88 | blueswir1 | espdma, *espdma_irq, esp_reset); |
674 | ee76f82e | blueswir1 | |
675 | ee76f82e | blueswir1 | for (i = 0; i < ESP_MAX_DEVS; i++) { |
676 | ee76f82e | blueswir1 | index = drive_get_index(IF_SCSI, 0, i);
|
677 | ee76f82e | blueswir1 | if (index == -1) |
678 | ee76f82e | blueswir1 | continue;
|
679 | ee76f82e | blueswir1 | esp_scsi_attach(main_esp, drives_table[index].bdrv, i); |
680 | ee76f82e | blueswir1 | } |
681 | ee76f82e | blueswir1 | |
682 | ee76f82e | blueswir1 | kernel_size = sun4m_load_kernel(kernel_filename, kernel_cmdline, |
683 | ee76f82e | blueswir1 | initrd_filename); |
684 | ee76f82e | blueswir1 | |
685 | ee76f82e | blueswir1 | nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
|
686 | ee76f82e | blueswir1 | boot_device, RAM_size, kernel_size, graphic_width, |
687 | ee76f82e | blueswir1 | graphic_height, graphic_depth, hwdef->machine_id, "Sun4c");
|
688 | ee76f82e | blueswir1 | } |
689 | ee76f82e | blueswir1 | |
690 | 36cd9210 | blueswir1 | static const struct hwdef hwdefs[] = { |
691 | 36cd9210 | blueswir1 | /* SS-5 */
|
692 | 36cd9210 | blueswir1 | { |
693 | 36cd9210 | blueswir1 | .iommu_base = 0x10000000,
|
694 | 36cd9210 | blueswir1 | .tcx_base = 0x50000000,
|
695 | 36cd9210 | blueswir1 | .cs_base = 0x6c000000,
|
696 | 384ccb5d | blueswir1 | .slavio_base = 0x70000000,
|
697 | 36cd9210 | blueswir1 | .ms_kb_base = 0x71000000,
|
698 | 36cd9210 | blueswir1 | .serial_base = 0x71100000,
|
699 | 36cd9210 | blueswir1 | .nvram_base = 0x71200000,
|
700 | 36cd9210 | blueswir1 | .fd_base = 0x71400000,
|
701 | 36cd9210 | blueswir1 | .counter_base = 0x71d00000,
|
702 | 36cd9210 | blueswir1 | .intctl_base = 0x71e00000,
|
703 | 4c2485de | blueswir1 | .idreg_base = 0x78000000,
|
704 | 36cd9210 | blueswir1 | .dma_base = 0x78400000,
|
705 | 36cd9210 | blueswir1 | .esp_base = 0x78800000,
|
706 | 36cd9210 | blueswir1 | .le_base = 0x78c00000,
|
707 | 127fc407 | blueswir1 | .apc_base = 0x6a000000,
|
708 | 0019ad53 | blueswir1 | .aux1_base = 0x71900000,
|
709 | 0019ad53 | blueswir1 | .aux2_base = 0x71910000,
|
710 | 7eb0c8e8 | blueswir1 | .ecc_base = -1,
|
711 | ee76f82e | blueswir1 | .sun4c_intctl_base = -1,
|
712 | ee76f82e | blueswir1 | .sun4c_counter_base = -1,
|
713 | 36cd9210 | blueswir1 | .vram_size = 0x00100000,
|
714 | 36cd9210 | blueswir1 | .nvram_size = 0x2000,
|
715 | 36cd9210 | blueswir1 | .esp_irq = 18,
|
716 | 36cd9210 | blueswir1 | .le_irq = 16,
|
717 | e3a79bca | blueswir1 | .clock_irq = 7,
|
718 | 36cd9210 | blueswir1 | .clock1_irq = 19,
|
719 | 36cd9210 | blueswir1 | .ms_kb_irq = 14,
|
720 | 36cd9210 | blueswir1 | .ser_irq = 15,
|
721 | 36cd9210 | blueswir1 | .fd_irq = 22,
|
722 | 36cd9210 | blueswir1 | .me_irq = 30,
|
723 | 36cd9210 | blueswir1 | .cs_irq = 5,
|
724 | 36cd9210 | blueswir1 | .machine_id = 0x80,
|
725 | cf3102ac | blueswir1 | .iommu_version = 0x05000000,
|
726 | e0353fe2 | blueswir1 | .intbit_to_level = { |
727 | f930d07e | blueswir1 | 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, |
728 | f930d07e | blueswir1 | 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, |
729 | e0353fe2 | blueswir1 | }, |
730 | 3ebf5aaf | blueswir1 | .max_mem = 0x10000000,
|
731 | 3ebf5aaf | blueswir1 | .default_cpu_model = "Fujitsu MB86904",
|
732 | e0353fe2 | blueswir1 | }, |
733 | e0353fe2 | blueswir1 | /* SS-10 */
|
734 | e0353fe2 | blueswir1 | { |
735 | 5dcb6b91 | blueswir1 | .iommu_base = 0xfe0000000ULL,
|
736 | 5dcb6b91 | blueswir1 | .tcx_base = 0xe20000000ULL,
|
737 | 803b3c7b | blueswir1 | .cs_base = -1,
|
738 | 5dcb6b91 | blueswir1 | .slavio_base = 0xff0000000ULL,
|
739 | 5dcb6b91 | blueswir1 | .ms_kb_base = 0xff1000000ULL,
|
740 | 5dcb6b91 | blueswir1 | .serial_base = 0xff1100000ULL,
|
741 | 5dcb6b91 | blueswir1 | .nvram_base = 0xff1200000ULL,
|
742 | 5dcb6b91 | blueswir1 | .fd_base = 0xff1700000ULL,
|
743 | 5dcb6b91 | blueswir1 | .counter_base = 0xff1300000ULL,
|
744 | 5dcb6b91 | blueswir1 | .intctl_base = 0xff1400000ULL,
|
745 | 4c2485de | blueswir1 | .idreg_base = 0xef0000000ULL,
|
746 | 5dcb6b91 | blueswir1 | .dma_base = 0xef0400000ULL,
|
747 | 5dcb6b91 | blueswir1 | .esp_base = 0xef0800000ULL,
|
748 | 5dcb6b91 | blueswir1 | .le_base = 0xef0c00000ULL,
|
749 | 0019ad53 | blueswir1 | .apc_base = 0xefa000000ULL, // XXX should not exist |
750 | 127fc407 | blueswir1 | .aux1_base = 0xff1800000ULL,
|
751 | 127fc407 | blueswir1 | .aux2_base = 0xff1a01000ULL,
|
752 | 7eb0c8e8 | blueswir1 | .ecc_base = 0xf00000000ULL,
|
753 | 7eb0c8e8 | blueswir1 | .ecc_version = 0x10000000, // version 0, implementation 1 |
754 | ee76f82e | blueswir1 | .sun4c_intctl_base = -1,
|
755 | ee76f82e | blueswir1 | .sun4c_counter_base = -1,
|
756 | e0353fe2 | blueswir1 | .vram_size = 0x00100000,
|
757 | e0353fe2 | blueswir1 | .nvram_size = 0x2000,
|
758 | e0353fe2 | blueswir1 | .esp_irq = 18,
|
759 | e0353fe2 | blueswir1 | .le_irq = 16,
|
760 | e3a79bca | blueswir1 | .clock_irq = 7,
|
761 | e0353fe2 | blueswir1 | .clock1_irq = 19,
|
762 | e0353fe2 | blueswir1 | .ms_kb_irq = 14,
|
763 | e0353fe2 | blueswir1 | .ser_irq = 15,
|
764 | e0353fe2 | blueswir1 | .fd_irq = 22,
|
765 | e0353fe2 | blueswir1 | .me_irq = 30,
|
766 | 803b3c7b | blueswir1 | .cs_irq = -1,
|
767 | e42c20b4 | blueswir1 | .ecc_irq = 28,
|
768 | 803b3c7b | blueswir1 | .machine_id = 0x72,
|
769 | 7fbfb139 | blueswir1 | .iommu_version = 0x03000000,
|
770 | e0353fe2 | blueswir1 | .intbit_to_level = { |
771 | f930d07e | blueswir1 | 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, |
772 | f930d07e | blueswir1 | 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, |
773 | e0353fe2 | blueswir1 | }, |
774 | 3ebf5aaf | blueswir1 | .max_mem = 0xffffffff, // XXX actually first 62GB ok |
775 | 3ebf5aaf | blueswir1 | .default_cpu_model = "TI SuperSparc II",
|
776 | 36cd9210 | blueswir1 | }, |
777 | 6a3b9cc9 | blueswir1 | /* SS-600MP */
|
778 | 6a3b9cc9 | blueswir1 | { |
779 | 6a3b9cc9 | blueswir1 | .iommu_base = 0xfe0000000ULL,
|
780 | 6a3b9cc9 | blueswir1 | .tcx_base = 0xe20000000ULL,
|
781 | 6a3b9cc9 | blueswir1 | .cs_base = -1,
|
782 | 6a3b9cc9 | blueswir1 | .slavio_base = 0xff0000000ULL,
|
783 | 6a3b9cc9 | blueswir1 | .ms_kb_base = 0xff1000000ULL,
|
784 | 6a3b9cc9 | blueswir1 | .serial_base = 0xff1100000ULL,
|
785 | 6a3b9cc9 | blueswir1 | .nvram_base = 0xff1200000ULL,
|
786 | 6a3b9cc9 | blueswir1 | .fd_base = -1,
|
787 | 6a3b9cc9 | blueswir1 | .counter_base = 0xff1300000ULL,
|
788 | 6a3b9cc9 | blueswir1 | .intctl_base = 0xff1400000ULL,
|
789 | 4c2485de | blueswir1 | .idreg_base = -1,
|
790 | 6a3b9cc9 | blueswir1 | .dma_base = 0xef0081000ULL,
|
791 | 6a3b9cc9 | blueswir1 | .esp_base = 0xef0080000ULL,
|
792 | 6a3b9cc9 | blueswir1 | .le_base = 0xef0060000ULL,
|
793 | 0019ad53 | blueswir1 | .apc_base = 0xefa000000ULL, // XXX should not exist |
794 | 127fc407 | blueswir1 | .aux1_base = 0xff1800000ULL,
|
795 | 127fc407 | blueswir1 | .aux2_base = 0xff1a01000ULL, // XXX should not exist |
796 | 7eb0c8e8 | blueswir1 | .ecc_base = 0xf00000000ULL,
|
797 | 7eb0c8e8 | blueswir1 | .ecc_version = 0x00000000, // version 0, implementation 0 |
798 | ee76f82e | blueswir1 | .sun4c_intctl_base = -1,
|
799 | ee76f82e | blueswir1 | .sun4c_counter_base = -1,
|
800 | 6a3b9cc9 | blueswir1 | .vram_size = 0x00100000,
|
801 | 6a3b9cc9 | blueswir1 | .nvram_size = 0x2000,
|
802 | 6a3b9cc9 | blueswir1 | .esp_irq = 18,
|
803 | 6a3b9cc9 | blueswir1 | .le_irq = 16,
|
804 | e3a79bca | blueswir1 | .clock_irq = 7,
|
805 | 6a3b9cc9 | blueswir1 | .clock1_irq = 19,
|
806 | 6a3b9cc9 | blueswir1 | .ms_kb_irq = 14,
|
807 | 6a3b9cc9 | blueswir1 | .ser_irq = 15,
|
808 | 6a3b9cc9 | blueswir1 | .fd_irq = 22,
|
809 | 6a3b9cc9 | blueswir1 | .me_irq = 30,
|
810 | 6a3b9cc9 | blueswir1 | .cs_irq = -1,
|
811 | e42c20b4 | blueswir1 | .ecc_irq = 28,
|
812 | 6a3b9cc9 | blueswir1 | .machine_id = 0x71,
|
813 | 7fbfb139 | blueswir1 | .iommu_version = 0x01000000,
|
814 | 6a3b9cc9 | blueswir1 | .intbit_to_level = { |
815 | 6a3b9cc9 | blueswir1 | 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, |
816 | 6a3b9cc9 | blueswir1 | 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, |
817 | 6a3b9cc9 | blueswir1 | }, |
818 | 3ebf5aaf | blueswir1 | .max_mem = 0xffffffff, // XXX actually first 62GB ok |
819 | 3ebf5aaf | blueswir1 | .default_cpu_model = "TI SuperSparc II",
|
820 | 6a3b9cc9 | blueswir1 | }, |
821 | ae40972f | blueswir1 | /* SS-20 */
|
822 | ae40972f | blueswir1 | { |
823 | ae40972f | blueswir1 | .iommu_base = 0xfe0000000ULL,
|
824 | ae40972f | blueswir1 | .tcx_base = 0xe20000000ULL,
|
825 | ae40972f | blueswir1 | .cs_base = -1,
|
826 | ae40972f | blueswir1 | .slavio_base = 0xff0000000ULL,
|
827 | ae40972f | blueswir1 | .ms_kb_base = 0xff1000000ULL,
|
828 | ae40972f | blueswir1 | .serial_base = 0xff1100000ULL,
|
829 | ae40972f | blueswir1 | .nvram_base = 0xff1200000ULL,
|
830 | ae40972f | blueswir1 | .fd_base = 0xff1700000ULL,
|
831 | ae40972f | blueswir1 | .counter_base = 0xff1300000ULL,
|
832 | ae40972f | blueswir1 | .intctl_base = 0xff1400000ULL,
|
833 | 4c2485de | blueswir1 | .idreg_base = 0xef0000000ULL,
|
834 | ae40972f | blueswir1 | .dma_base = 0xef0400000ULL,
|
835 | ae40972f | blueswir1 | .esp_base = 0xef0800000ULL,
|
836 | ae40972f | blueswir1 | .le_base = 0xef0c00000ULL,
|
837 | 0019ad53 | blueswir1 | .apc_base = 0xefa000000ULL, // XXX should not exist |
838 | 577d8dd4 | blueswir1 | .aux1_base = 0xff1800000ULL,
|
839 | 577d8dd4 | blueswir1 | .aux2_base = 0xff1a01000ULL,
|
840 | ae40972f | blueswir1 | .ecc_base = 0xf00000000ULL,
|
841 | ae40972f | blueswir1 | .ecc_version = 0x20000000, // version 0, implementation 2 |
842 | ee76f82e | blueswir1 | .sun4c_intctl_base = -1,
|
843 | ee76f82e | blueswir1 | .sun4c_counter_base = -1,
|
844 | ae40972f | blueswir1 | .vram_size = 0x00100000,
|
845 | ae40972f | blueswir1 | .nvram_size = 0x2000,
|
846 | ae40972f | blueswir1 | .esp_irq = 18,
|
847 | ae40972f | blueswir1 | .le_irq = 16,
|
848 | e3a79bca | blueswir1 | .clock_irq = 7,
|
849 | ae40972f | blueswir1 | .clock1_irq = 19,
|
850 | ae40972f | blueswir1 | .ms_kb_irq = 14,
|
851 | ae40972f | blueswir1 | .ser_irq = 15,
|
852 | ae40972f | blueswir1 | .fd_irq = 22,
|
853 | ae40972f | blueswir1 | .me_irq = 30,
|
854 | ae40972f | blueswir1 | .cs_irq = -1,
|
855 | e42c20b4 | blueswir1 | .ecc_irq = 28,
|
856 | ae40972f | blueswir1 | .machine_id = 0x72,
|
857 | ae40972f | blueswir1 | .iommu_version = 0x13000000,
|
858 | ae40972f | blueswir1 | .intbit_to_level = { |
859 | ae40972f | blueswir1 | 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, |
860 | ae40972f | blueswir1 | 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, |
861 | ae40972f | blueswir1 | }, |
862 | ae40972f | blueswir1 | .max_mem = 0xffffffff, // XXX actually first 62GB ok |
863 | ae40972f | blueswir1 | .default_cpu_model = "TI SuperSparc II",
|
864 | ae40972f | blueswir1 | }, |
865 | ee76f82e | blueswir1 | /* SS-2 */
|
866 | ee76f82e | blueswir1 | { |
867 | ee76f82e | blueswir1 | .iommu_base = 0xf8000000,
|
868 | ee76f82e | blueswir1 | .tcx_base = 0xfe000000,
|
869 | ee76f82e | blueswir1 | .cs_base = -1,
|
870 | ee76f82e | blueswir1 | .slavio_base = 0xf6000000,
|
871 | ee76f82e | blueswir1 | .ms_kb_base = 0xf0000000,
|
872 | ee76f82e | blueswir1 | .serial_base = 0xf1000000,
|
873 | ee76f82e | blueswir1 | .nvram_base = 0xf2000000,
|
874 | ee76f82e | blueswir1 | .fd_base = 0xf7200000,
|
875 | ee76f82e | blueswir1 | .counter_base = -1,
|
876 | ee76f82e | blueswir1 | .intctl_base = -1,
|
877 | ee76f82e | blueswir1 | .dma_base = 0xf8400000,
|
878 | ee76f82e | blueswir1 | .esp_base = 0xf8800000,
|
879 | ee76f82e | blueswir1 | .le_base = 0xf8c00000,
|
880 | 0019ad53 | blueswir1 | .apc_base = -1,
|
881 | 0019ad53 | blueswir1 | .aux1_base = 0xf7400003,
|
882 | 0019ad53 | blueswir1 | .aux2_base = -1,
|
883 | ee76f82e | blueswir1 | .sun4c_intctl_base = 0xf5000000,
|
884 | ee76f82e | blueswir1 | .sun4c_counter_base = 0xf3000000,
|
885 | ee76f82e | blueswir1 | .vram_size = 0x00100000,
|
886 | 4aed2c33 | blueswir1 | .nvram_size = 0x800,
|
887 | ee76f82e | blueswir1 | .esp_irq = 2,
|
888 | ee76f82e | blueswir1 | .le_irq = 3,
|
889 | ee76f82e | blueswir1 | .clock_irq = 5,
|
890 | ee76f82e | blueswir1 | .clock1_irq = 7,
|
891 | ee76f82e | blueswir1 | .ms_kb_irq = 1,
|
892 | ee76f82e | blueswir1 | .ser_irq = 1,
|
893 | ee76f82e | blueswir1 | .fd_irq = 1,
|
894 | ee76f82e | blueswir1 | .me_irq = 1,
|
895 | ee76f82e | blueswir1 | .cs_irq = -1,
|
896 | ee76f82e | blueswir1 | .machine_id = 0x55,
|
897 | ee76f82e | blueswir1 | .max_mem = 0x10000000,
|
898 | ee76f82e | blueswir1 | .default_cpu_model = "Cypress CY7C601",
|
899 | ee76f82e | blueswir1 | }, |
900 | a526a31c | blueswir1 | /* Voyager */
|
901 | a526a31c | blueswir1 | { |
902 | a526a31c | blueswir1 | .iommu_base = 0x10000000,
|
903 | a526a31c | blueswir1 | .tcx_base = 0x50000000,
|
904 | a526a31c | blueswir1 | .cs_base = -1,
|
905 | a526a31c | blueswir1 | .slavio_base = 0x70000000,
|
906 | a526a31c | blueswir1 | .ms_kb_base = 0x71000000,
|
907 | a526a31c | blueswir1 | .serial_base = 0x71100000,
|
908 | a526a31c | blueswir1 | .nvram_base = 0x71200000,
|
909 | a526a31c | blueswir1 | .fd_base = 0x71400000,
|
910 | a526a31c | blueswir1 | .counter_base = 0x71d00000,
|
911 | a526a31c | blueswir1 | .intctl_base = 0x71e00000,
|
912 | a526a31c | blueswir1 | .idreg_base = 0x78000000,
|
913 | a526a31c | blueswir1 | .dma_base = 0x78400000,
|
914 | a526a31c | blueswir1 | .esp_base = 0x78800000,
|
915 | a526a31c | blueswir1 | .le_base = 0x78c00000,
|
916 | a526a31c | blueswir1 | .apc_base = 0x71300000, // pmc |
917 | a526a31c | blueswir1 | .aux1_base = 0x71900000,
|
918 | a526a31c | blueswir1 | .aux2_base = 0x71910000,
|
919 | a526a31c | blueswir1 | .ecc_base = -1,
|
920 | a526a31c | blueswir1 | .sun4c_intctl_base = -1,
|
921 | a526a31c | blueswir1 | .sun4c_counter_base = -1,
|
922 | a526a31c | blueswir1 | .vram_size = 0x00100000,
|
923 | a526a31c | blueswir1 | .nvram_size = 0x2000,
|
924 | a526a31c | blueswir1 | .esp_irq = 18,
|
925 | a526a31c | blueswir1 | .le_irq = 16,
|
926 | a526a31c | blueswir1 | .clock_irq = 7,
|
927 | a526a31c | blueswir1 | .clock1_irq = 19,
|
928 | a526a31c | blueswir1 | .ms_kb_irq = 14,
|
929 | a526a31c | blueswir1 | .ser_irq = 15,
|
930 | a526a31c | blueswir1 | .fd_irq = 22,
|
931 | a526a31c | blueswir1 | .me_irq = 30,
|
932 | a526a31c | blueswir1 | .cs_irq = -1,
|
933 | a526a31c | blueswir1 | .machine_id = 0x80,
|
934 | a526a31c | blueswir1 | .iommu_version = 0x05000000,
|
935 | a526a31c | blueswir1 | .intbit_to_level = { |
936 | a526a31c | blueswir1 | 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, |
937 | a526a31c | blueswir1 | 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, |
938 | a526a31c | blueswir1 | }, |
939 | a526a31c | blueswir1 | .max_mem = 0x10000000,
|
940 | a526a31c | blueswir1 | .default_cpu_model = "Fujitsu MB86904",
|
941 | a526a31c | blueswir1 | }, |
942 | a526a31c | blueswir1 | /* LX */
|
943 | a526a31c | blueswir1 | { |
944 | a526a31c | blueswir1 | .iommu_base = 0x10000000,
|
945 | a526a31c | blueswir1 | .tcx_base = 0x50000000,
|
946 | a526a31c | blueswir1 | .cs_base = -1,
|
947 | a526a31c | blueswir1 | .slavio_base = 0x70000000,
|
948 | a526a31c | blueswir1 | .ms_kb_base = 0x71000000,
|
949 | a526a31c | blueswir1 | .serial_base = 0x71100000,
|
950 | a526a31c | blueswir1 | .nvram_base = 0x71200000,
|
951 | a526a31c | blueswir1 | .fd_base = 0x71400000,
|
952 | a526a31c | blueswir1 | .counter_base = 0x71d00000,
|
953 | a526a31c | blueswir1 | .intctl_base = 0x71e00000,
|
954 | a526a31c | blueswir1 | .idreg_base = 0x78000000,
|
955 | a526a31c | blueswir1 | .dma_base = 0x78400000,
|
956 | a526a31c | blueswir1 | .esp_base = 0x78800000,
|
957 | a526a31c | blueswir1 | .le_base = 0x78c00000,
|
958 | a526a31c | blueswir1 | .apc_base = -1,
|
959 | a526a31c | blueswir1 | .aux1_base = 0x71900000,
|
960 | a526a31c | blueswir1 | .aux2_base = 0x71910000,
|
961 | a526a31c | blueswir1 | .ecc_base = -1,
|
962 | a526a31c | blueswir1 | .sun4c_intctl_base = -1,
|
963 | a526a31c | blueswir1 | .sun4c_counter_base = -1,
|
964 | a526a31c | blueswir1 | .vram_size = 0x00100000,
|
965 | a526a31c | blueswir1 | .nvram_size = 0x2000,
|
966 | a526a31c | blueswir1 | .esp_irq = 18,
|
967 | a526a31c | blueswir1 | .le_irq = 16,
|
968 | a526a31c | blueswir1 | .clock_irq = 7,
|
969 | a526a31c | blueswir1 | .clock1_irq = 19,
|
970 | a526a31c | blueswir1 | .ms_kb_irq = 14,
|
971 | a526a31c | blueswir1 | .ser_irq = 15,
|
972 | a526a31c | blueswir1 | .fd_irq = 22,
|
973 | a526a31c | blueswir1 | .me_irq = 30,
|
974 | a526a31c | blueswir1 | .cs_irq = -1,
|
975 | a526a31c | blueswir1 | .machine_id = 0x80,
|
976 | a526a31c | blueswir1 | .iommu_version = 0x04000000,
|
977 | a526a31c | blueswir1 | .intbit_to_level = { |
978 | a526a31c | blueswir1 | 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, |
979 | a526a31c | blueswir1 | 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, |
980 | a526a31c | blueswir1 | }, |
981 | a526a31c | blueswir1 | .max_mem = 0x10000000,
|
982 | a526a31c | blueswir1 | .default_cpu_model = "TI MicroSparc I",
|
983 | a526a31c | blueswir1 | }, |
984 | a526a31c | blueswir1 | /* SS-4 */
|
985 | a526a31c | blueswir1 | { |
986 | a526a31c | blueswir1 | .iommu_base = 0x10000000,
|
987 | a526a31c | blueswir1 | .tcx_base = 0x50000000,
|
988 | a526a31c | blueswir1 | .cs_base = 0x6c000000,
|
989 | a526a31c | blueswir1 | .slavio_base = 0x70000000,
|
990 | a526a31c | blueswir1 | .ms_kb_base = 0x71000000,
|
991 | a526a31c | blueswir1 | .serial_base = 0x71100000,
|
992 | a526a31c | blueswir1 | .nvram_base = 0x71200000,
|
993 | a526a31c | blueswir1 | .fd_base = 0x71400000,
|
994 | a526a31c | blueswir1 | .counter_base = 0x71d00000,
|
995 | a526a31c | blueswir1 | .intctl_base = 0x71e00000,
|
996 | a526a31c | blueswir1 | .idreg_base = 0x78000000,
|
997 | a526a31c | blueswir1 | .dma_base = 0x78400000,
|
998 | a526a31c | blueswir1 | .esp_base = 0x78800000,
|
999 | a526a31c | blueswir1 | .le_base = 0x78c00000,
|
1000 | a526a31c | blueswir1 | .apc_base = 0x6a000000,
|
1001 | a526a31c | blueswir1 | .aux1_base = 0x71900000,
|
1002 | a526a31c | blueswir1 | .aux2_base = 0x71910000,
|
1003 | a526a31c | blueswir1 | .ecc_base = -1,
|
1004 | a526a31c | blueswir1 | .sun4c_intctl_base = -1,
|
1005 | a526a31c | blueswir1 | .sun4c_counter_base = -1,
|
1006 | a526a31c | blueswir1 | .vram_size = 0x00100000,
|
1007 | a526a31c | blueswir1 | .nvram_size = 0x2000,
|
1008 | a526a31c | blueswir1 | .esp_irq = 18,
|
1009 | a526a31c | blueswir1 | .le_irq = 16,
|
1010 | a526a31c | blueswir1 | .clock_irq = 7,
|
1011 | a526a31c | blueswir1 | .clock1_irq = 19,
|
1012 | a526a31c | blueswir1 | .ms_kb_irq = 14,
|
1013 | a526a31c | blueswir1 | .ser_irq = 15,
|
1014 | a526a31c | blueswir1 | .fd_irq = 22,
|
1015 | a526a31c | blueswir1 | .me_irq = 30,
|
1016 | a526a31c | blueswir1 | .cs_irq = 5,
|
1017 | a526a31c | blueswir1 | .machine_id = 0x80,
|
1018 | a526a31c | blueswir1 | .iommu_version = 0x05000000,
|
1019 | a526a31c | blueswir1 | .intbit_to_level = { |
1020 | a526a31c | blueswir1 | 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, |
1021 | a526a31c | blueswir1 | 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, |
1022 | a526a31c | blueswir1 | }, |
1023 | a526a31c | blueswir1 | .max_mem = 0x10000000,
|
1024 | a526a31c | blueswir1 | .default_cpu_model = "Fujitsu MB86904",
|
1025 | a526a31c | blueswir1 | }, |
1026 | a526a31c | blueswir1 | /* SPARCClassic */
|
1027 | a526a31c | blueswir1 | { |
1028 | a526a31c | blueswir1 | .iommu_base = 0x10000000,
|
1029 | a526a31c | blueswir1 | .tcx_base = 0x50000000,
|
1030 | a526a31c | blueswir1 | .cs_base = -1,
|
1031 | a526a31c | blueswir1 | .slavio_base = 0x70000000,
|
1032 | a526a31c | blueswir1 | .ms_kb_base = 0x71000000,
|
1033 | a526a31c | blueswir1 | .serial_base = 0x71100000,
|
1034 | a526a31c | blueswir1 | .nvram_base = 0x71200000,
|
1035 | a526a31c | blueswir1 | .fd_base = 0x71400000,
|
1036 | a526a31c | blueswir1 | .counter_base = 0x71d00000,
|
1037 | a526a31c | blueswir1 | .intctl_base = 0x71e00000,
|
1038 | a526a31c | blueswir1 | .idreg_base = 0x78000000,
|
1039 | a526a31c | blueswir1 | .dma_base = 0x78400000,
|
1040 | a526a31c | blueswir1 | .esp_base = 0x78800000,
|
1041 | a526a31c | blueswir1 | .le_base = 0x78c00000,
|
1042 | a526a31c | blueswir1 | .apc_base = 0x6a000000,
|
1043 | a526a31c | blueswir1 | .aux1_base = 0x71900000,
|
1044 | a526a31c | blueswir1 | .aux2_base = 0x71910000,
|
1045 | a526a31c | blueswir1 | .ecc_base = -1,
|
1046 | a526a31c | blueswir1 | .sun4c_intctl_base = -1,
|
1047 | a526a31c | blueswir1 | .sun4c_counter_base = -1,
|
1048 | a526a31c | blueswir1 | .vram_size = 0x00100000,
|
1049 | a526a31c | blueswir1 | .nvram_size = 0x2000,
|
1050 | a526a31c | blueswir1 | .esp_irq = 18,
|
1051 | a526a31c | blueswir1 | .le_irq = 16,
|
1052 | a526a31c | blueswir1 | .clock_irq = 7,
|
1053 | a526a31c | blueswir1 | .clock1_irq = 19,
|
1054 | a526a31c | blueswir1 | .ms_kb_irq = 14,
|
1055 | a526a31c | blueswir1 | .ser_irq = 15,
|
1056 | a526a31c | blueswir1 | .fd_irq = 22,
|
1057 | a526a31c | blueswir1 | .me_irq = 30,
|
1058 | a526a31c | blueswir1 | .cs_irq = -1,
|
1059 | a526a31c | blueswir1 | .machine_id = 0x80,
|
1060 | a526a31c | blueswir1 | .iommu_version = 0x05000000,
|
1061 | a526a31c | blueswir1 | .intbit_to_level = { |
1062 | a526a31c | blueswir1 | 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, |
1063 | a526a31c | blueswir1 | 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, |
1064 | a526a31c | blueswir1 | }, |
1065 | a526a31c | blueswir1 | .max_mem = 0x10000000,
|
1066 | a526a31c | blueswir1 | .default_cpu_model = "TI MicroSparc I",
|
1067 | a526a31c | blueswir1 | }, |
1068 | a526a31c | blueswir1 | /* SPARCbook */
|
1069 | a526a31c | blueswir1 | { |
1070 | a526a31c | blueswir1 | .iommu_base = 0x10000000,
|
1071 | a526a31c | blueswir1 | .tcx_base = 0x50000000, // XXX |
1072 | a526a31c | blueswir1 | .cs_base = -1,
|
1073 | a526a31c | blueswir1 | .slavio_base = 0x70000000,
|
1074 | a526a31c | blueswir1 | .ms_kb_base = 0x71000000,
|
1075 | a526a31c | blueswir1 | .serial_base = 0x71100000,
|
1076 | a526a31c | blueswir1 | .nvram_base = 0x71200000,
|
1077 | a526a31c | blueswir1 | .fd_base = 0x71400000,
|
1078 | a526a31c | blueswir1 | .counter_base = 0x71d00000,
|
1079 | a526a31c | blueswir1 | .intctl_base = 0x71e00000,
|
1080 | a526a31c | blueswir1 | .idreg_base = 0x78000000,
|
1081 | a526a31c | blueswir1 | .dma_base = 0x78400000,
|
1082 | a526a31c | blueswir1 | .esp_base = 0x78800000,
|
1083 | a526a31c | blueswir1 | .le_base = 0x78c00000,
|
1084 | a526a31c | blueswir1 | .apc_base = 0x6a000000,
|
1085 | a526a31c | blueswir1 | .aux1_base = 0x71900000,
|
1086 | a526a31c | blueswir1 | .aux2_base = 0x71910000,
|
1087 | a526a31c | blueswir1 | .ecc_base = -1,
|
1088 | a526a31c | blueswir1 | .sun4c_intctl_base = -1,
|
1089 | a526a31c | blueswir1 | .sun4c_counter_base = -1,
|
1090 | a526a31c | blueswir1 | .vram_size = 0x00100000,
|
1091 | a526a31c | blueswir1 | .nvram_size = 0x2000,
|
1092 | a526a31c | blueswir1 | .esp_irq = 18,
|
1093 | a526a31c | blueswir1 | .le_irq = 16,
|
1094 | a526a31c | blueswir1 | .clock_irq = 7,
|
1095 | a526a31c | blueswir1 | .clock1_irq = 19,
|
1096 | a526a31c | blueswir1 | .ms_kb_irq = 14,
|
1097 | a526a31c | blueswir1 | .ser_irq = 15,
|
1098 | a526a31c | blueswir1 | .fd_irq = 22,
|
1099 | a526a31c | blueswir1 | .me_irq = 30,
|
1100 | a526a31c | blueswir1 | .cs_irq = -1,
|
1101 | a526a31c | blueswir1 | .machine_id = 0x80,
|
1102 | a526a31c | blueswir1 | .iommu_version = 0x05000000,
|
1103 | a526a31c | blueswir1 | .intbit_to_level = { |
1104 | a526a31c | blueswir1 | 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, |
1105 | a526a31c | blueswir1 | 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, |
1106 | a526a31c | blueswir1 | }, |
1107 | a526a31c | blueswir1 | .max_mem = 0x10000000,
|
1108 | a526a31c | blueswir1 | .default_cpu_model = "TI MicroSparc I",
|
1109 | a526a31c | blueswir1 | }, |
1110 | 36cd9210 | blueswir1 | }; |
1111 | 36cd9210 | blueswir1 | |
1112 | 36cd9210 | blueswir1 | /* SPARCstation 5 hardware initialisation */
|
1113 | 03875444 | aurel32 | static void ss5_init(int RAM_size, int vga_ram_size, |
1114 | b881c2c6 | blueswir1 | const char *boot_device, DisplayState *ds, |
1115 | b881c2c6 | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1116 | b881c2c6 | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1117 | 36cd9210 | blueswir1 | { |
1118 | 3ebf5aaf | blueswir1 | sun4m_hw_init(&hwdefs[0], RAM_size, boot_device, ds, kernel_filename,
|
1119 | 3ebf5aaf | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1120 | 420557e8 | bellard | } |
1121 | c0e564d5 | bellard | |
1122 | e0353fe2 | blueswir1 | /* SPARCstation 10 hardware initialisation */
|
1123 | 03875444 | aurel32 | static void ss10_init(int RAM_size, int vga_ram_size, |
1124 | b881c2c6 | blueswir1 | const char *boot_device, DisplayState *ds, |
1125 | b881c2c6 | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1126 | b881c2c6 | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1127 | e0353fe2 | blueswir1 | { |
1128 | 3ebf5aaf | blueswir1 | sun4m_hw_init(&hwdefs[1], RAM_size, boot_device, ds, kernel_filename,
|
1129 | 3ebf5aaf | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1130 | e0353fe2 | blueswir1 | } |
1131 | e0353fe2 | blueswir1 | |
1132 | 6a3b9cc9 | blueswir1 | /* SPARCserver 600MP hardware initialisation */
|
1133 | 03875444 | aurel32 | static void ss600mp_init(int RAM_size, int vga_ram_size, |
1134 | b881c2c6 | blueswir1 | const char *boot_device, DisplayState *ds, |
1135 | 6a3b9cc9 | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1136 | 6a3b9cc9 | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1137 | 6a3b9cc9 | blueswir1 | { |
1138 | 3ebf5aaf | blueswir1 | sun4m_hw_init(&hwdefs[2], RAM_size, boot_device, ds, kernel_filename,
|
1139 | 3ebf5aaf | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1140 | 6a3b9cc9 | blueswir1 | } |
1141 | 6a3b9cc9 | blueswir1 | |
1142 | ae40972f | blueswir1 | /* SPARCstation 20 hardware initialisation */
|
1143 | 03875444 | aurel32 | static void ss20_init(int RAM_size, int vga_ram_size, |
1144 | ae40972f | blueswir1 | const char *boot_device, DisplayState *ds, |
1145 | ae40972f | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1146 | ae40972f | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1147 | ae40972f | blueswir1 | { |
1148 | ae40972f | blueswir1 | sun4m_hw_init(&hwdefs[3], RAM_size, boot_device, ds, kernel_filename,
|
1149 | ae40972f | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1150 | ae40972f | blueswir1 | } |
1151 | ae40972f | blueswir1 | |
1152 | ee76f82e | blueswir1 | /* SPARCstation 2 hardware initialisation */
|
1153 | 03875444 | aurel32 | static void ss2_init(int RAM_size, int vga_ram_size, |
1154 | ee76f82e | blueswir1 | const char *boot_device, DisplayState *ds, |
1155 | ee76f82e | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1156 | ee76f82e | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1157 | ee76f82e | blueswir1 | { |
1158 | ee76f82e | blueswir1 | sun4c_hw_init(&hwdefs[4], RAM_size, boot_device, ds, kernel_filename,
|
1159 | ee76f82e | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1160 | ee76f82e | blueswir1 | } |
1161 | ee76f82e | blueswir1 | |
1162 | a526a31c | blueswir1 | /* SPARCstation Voyager hardware initialisation */
|
1163 | a526a31c | blueswir1 | static void vger_init(int RAM_size, int vga_ram_size, |
1164 | a526a31c | blueswir1 | const char *boot_device, DisplayState *ds, |
1165 | a526a31c | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1166 | a526a31c | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1167 | a526a31c | blueswir1 | { |
1168 | a526a31c | blueswir1 | sun4m_hw_init(&hwdefs[5], RAM_size, boot_device, ds, kernel_filename,
|
1169 | a526a31c | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1170 | a526a31c | blueswir1 | } |
1171 | a526a31c | blueswir1 | |
1172 | a526a31c | blueswir1 | /* SPARCstation LX hardware initialisation */
|
1173 | a526a31c | blueswir1 | static void ss_lx_init(int RAM_size, int vga_ram_size, |
1174 | a526a31c | blueswir1 | const char *boot_device, DisplayState *ds, |
1175 | a526a31c | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1176 | a526a31c | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1177 | a526a31c | blueswir1 | { |
1178 | a526a31c | blueswir1 | sun4m_hw_init(&hwdefs[6], RAM_size, boot_device, ds, kernel_filename,
|
1179 | a526a31c | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1180 | a526a31c | blueswir1 | } |
1181 | a526a31c | blueswir1 | |
1182 | a526a31c | blueswir1 | /* SPARCstation 4 hardware initialisation */
|
1183 | a526a31c | blueswir1 | static void ss4_init(int RAM_size, int vga_ram_size, |
1184 | a526a31c | blueswir1 | const char *boot_device, DisplayState *ds, |
1185 | a526a31c | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1186 | a526a31c | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1187 | a526a31c | blueswir1 | { |
1188 | a526a31c | blueswir1 | sun4m_hw_init(&hwdefs[7], RAM_size, boot_device, ds, kernel_filename,
|
1189 | a526a31c | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1190 | a526a31c | blueswir1 | } |
1191 | a526a31c | blueswir1 | |
1192 | a526a31c | blueswir1 | /* SPARCClassic hardware initialisation */
|
1193 | a526a31c | blueswir1 | static void scls_init(int RAM_size, int vga_ram_size, |
1194 | a526a31c | blueswir1 | const char *boot_device, DisplayState *ds, |
1195 | a526a31c | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1196 | a526a31c | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1197 | a526a31c | blueswir1 | { |
1198 | a526a31c | blueswir1 | sun4m_hw_init(&hwdefs[8], RAM_size, boot_device, ds, kernel_filename,
|
1199 | a526a31c | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1200 | a526a31c | blueswir1 | } |
1201 | a526a31c | blueswir1 | |
1202 | a526a31c | blueswir1 | /* SPARCbook hardware initialisation */
|
1203 | a526a31c | blueswir1 | static void sbook_init(int RAM_size, int vga_ram_size, |
1204 | a526a31c | blueswir1 | const char *boot_device, DisplayState *ds, |
1205 | a526a31c | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1206 | a526a31c | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1207 | a526a31c | blueswir1 | { |
1208 | a526a31c | blueswir1 | sun4m_hw_init(&hwdefs[9], RAM_size, boot_device, ds, kernel_filename,
|
1209 | a526a31c | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1210 | a526a31c | blueswir1 | } |
1211 | a526a31c | blueswir1 | |
1212 | 36cd9210 | blueswir1 | QEMUMachine ss5_machine = { |
1213 | 36cd9210 | blueswir1 | "SS-5",
|
1214 | 36cd9210 | blueswir1 | "Sun4m platform, SPARCstation 5",
|
1215 | 36cd9210 | blueswir1 | ss5_init, |
1216 | 7fb4fdcf | balrog | PROM_SIZE_MAX + 0x00100000,
|
1217 | c0e564d5 | bellard | }; |
1218 | e0353fe2 | blueswir1 | |
1219 | e0353fe2 | blueswir1 | QEMUMachine ss10_machine = { |
1220 | e0353fe2 | blueswir1 | "SS-10",
|
1221 | e0353fe2 | blueswir1 | "Sun4m platform, SPARCstation 10",
|
1222 | e0353fe2 | blueswir1 | ss10_init, |
1223 | 7fb4fdcf | balrog | PROM_SIZE_MAX + 0x00100000,
|
1224 | e0353fe2 | blueswir1 | }; |
1225 | 6a3b9cc9 | blueswir1 | |
1226 | 6a3b9cc9 | blueswir1 | QEMUMachine ss600mp_machine = { |
1227 | 6a3b9cc9 | blueswir1 | "SS-600MP",
|
1228 | 6a3b9cc9 | blueswir1 | "Sun4m platform, SPARCserver 600MP",
|
1229 | 6a3b9cc9 | blueswir1 | ss600mp_init, |
1230 | 7fb4fdcf | balrog | PROM_SIZE_MAX + 0x00100000,
|
1231 | 6a3b9cc9 | blueswir1 | }; |
1232 | ae40972f | blueswir1 | |
1233 | ae40972f | blueswir1 | QEMUMachine ss20_machine = { |
1234 | ae40972f | blueswir1 | "SS-20",
|
1235 | ae40972f | blueswir1 | "Sun4m platform, SPARCstation 20",
|
1236 | ae40972f | blueswir1 | ss20_init, |
1237 | 7fb4fdcf | balrog | PROM_SIZE_MAX + 0x00100000,
|
1238 | ae40972f | blueswir1 | }; |
1239 | ae40972f | blueswir1 | |
1240 | ee76f82e | blueswir1 | QEMUMachine ss2_machine = { |
1241 | ee76f82e | blueswir1 | "SS-2",
|
1242 | ee76f82e | blueswir1 | "Sun4c platform, SPARCstation 2",
|
1243 | ee76f82e | blueswir1 | ss2_init, |
1244 | 7fb4fdcf | balrog | PROM_SIZE_MAX + 0x00100000,
|
1245 | ee76f82e | blueswir1 | }; |
1246 | 7d85892b | blueswir1 | |
1247 | a526a31c | blueswir1 | QEMUMachine voyager_machine = { |
1248 | a526a31c | blueswir1 | "Voyager",
|
1249 | a526a31c | blueswir1 | "Sun4m platform, SPARCstation Voyager",
|
1250 | a526a31c | blueswir1 | vger_init, |
1251 | 7fb4fdcf | balrog | PROM_SIZE_MAX + 0x00100000,
|
1252 | a526a31c | blueswir1 | }; |
1253 | a526a31c | blueswir1 | |
1254 | a526a31c | blueswir1 | QEMUMachine ss_lx_machine = { |
1255 | a526a31c | blueswir1 | "LX",
|
1256 | a526a31c | blueswir1 | "Sun4m platform, SPARCstation LX",
|
1257 | a526a31c | blueswir1 | ss_lx_init, |
1258 | 7fb4fdcf | balrog | PROM_SIZE_MAX + 0x00100000,
|
1259 | a526a31c | blueswir1 | }; |
1260 | a526a31c | blueswir1 | |
1261 | a526a31c | blueswir1 | QEMUMachine ss4_machine = { |
1262 | a526a31c | blueswir1 | "SS-4",
|
1263 | a526a31c | blueswir1 | "Sun4m platform, SPARCstation 4",
|
1264 | a526a31c | blueswir1 | ss4_init, |
1265 | 7fb4fdcf | balrog | PROM_SIZE_MAX + 0x00100000,
|
1266 | a526a31c | blueswir1 | }; |
1267 | a526a31c | blueswir1 | |
1268 | a526a31c | blueswir1 | QEMUMachine scls_machine = { |
1269 | a526a31c | blueswir1 | "SPARCClassic",
|
1270 | a526a31c | blueswir1 | "Sun4m platform, SPARCClassic",
|
1271 | a526a31c | blueswir1 | scls_init, |
1272 | 7fb4fdcf | balrog | PROM_SIZE_MAX + 0x00100000,
|
1273 | a526a31c | blueswir1 | }; |
1274 | a526a31c | blueswir1 | |
1275 | a526a31c | blueswir1 | QEMUMachine sbook_machine = { |
1276 | a526a31c | blueswir1 | "SPARCbook",
|
1277 | a526a31c | blueswir1 | "Sun4m platform, SPARCbook",
|
1278 | a526a31c | blueswir1 | sbook_init, |
1279 | 7fb4fdcf | balrog | PROM_SIZE_MAX + 0x00100000,
|
1280 | a526a31c | blueswir1 | }; |
1281 | a526a31c | blueswir1 | |
1282 | 7d85892b | blueswir1 | static const struct sun4d_hwdef sun4d_hwdefs[] = { |
1283 | 7d85892b | blueswir1 | /* SS-1000 */
|
1284 | 7d85892b | blueswir1 | { |
1285 | 7d85892b | blueswir1 | .iounit_bases = { |
1286 | 7d85892b | blueswir1 | 0xfe0200000ULL,
|
1287 | 7d85892b | blueswir1 | 0xfe1200000ULL,
|
1288 | 7d85892b | blueswir1 | 0xfe2200000ULL,
|
1289 | 7d85892b | blueswir1 | 0xfe3200000ULL,
|
1290 | 7d85892b | blueswir1 | -1,
|
1291 | 7d85892b | blueswir1 | }, |
1292 | 7d85892b | blueswir1 | .tcx_base = 0x820000000ULL,
|
1293 | 7d85892b | blueswir1 | .slavio_base = 0xf00000000ULL,
|
1294 | 7d85892b | blueswir1 | .ms_kb_base = 0xf00240000ULL,
|
1295 | 7d85892b | blueswir1 | .serial_base = 0xf00200000ULL,
|
1296 | 7d85892b | blueswir1 | .nvram_base = 0xf00280000ULL,
|
1297 | 7d85892b | blueswir1 | .counter_base = 0xf00300000ULL,
|
1298 | 7d85892b | blueswir1 | .espdma_base = 0x800081000ULL,
|
1299 | 7d85892b | blueswir1 | .esp_base = 0x800080000ULL,
|
1300 | 7d85892b | blueswir1 | .ledma_base = 0x800040000ULL,
|
1301 | 7d85892b | blueswir1 | .le_base = 0x800060000ULL,
|
1302 | 7d85892b | blueswir1 | .sbi_base = 0xf02800000ULL,
|
1303 | 7d85892b | blueswir1 | .vram_size = 0x00100000,
|
1304 | 7d85892b | blueswir1 | .nvram_size = 0x2000,
|
1305 | 7d85892b | blueswir1 | .esp_irq = 3,
|
1306 | 7d85892b | blueswir1 | .le_irq = 4,
|
1307 | 7d85892b | blueswir1 | .clock_irq = 14,
|
1308 | 7d85892b | blueswir1 | .clock1_irq = 10,
|
1309 | 7d85892b | blueswir1 | .ms_kb_irq = 12,
|
1310 | 7d85892b | blueswir1 | .ser_irq = 12,
|
1311 | 7d85892b | blueswir1 | .machine_id = 0x80,
|
1312 | 7d85892b | blueswir1 | .iounit_version = 0x03000000,
|
1313 | 7d85892b | blueswir1 | .max_mem = 0xffffffff, // XXX actually first 62GB ok |
1314 | 7d85892b | blueswir1 | .default_cpu_model = "TI SuperSparc II",
|
1315 | 7d85892b | blueswir1 | }, |
1316 | 7d85892b | blueswir1 | /* SS-2000 */
|
1317 | 7d85892b | blueswir1 | { |
1318 | 7d85892b | blueswir1 | .iounit_bases = { |
1319 | 7d85892b | blueswir1 | 0xfe0200000ULL,
|
1320 | 7d85892b | blueswir1 | 0xfe1200000ULL,
|
1321 | 7d85892b | blueswir1 | 0xfe2200000ULL,
|
1322 | 7d85892b | blueswir1 | 0xfe3200000ULL,
|
1323 | 7d85892b | blueswir1 | 0xfe4200000ULL,
|
1324 | 7d85892b | blueswir1 | }, |
1325 | 7d85892b | blueswir1 | .tcx_base = 0x820000000ULL,
|
1326 | 7d85892b | blueswir1 | .slavio_base = 0xf00000000ULL,
|
1327 | 7d85892b | blueswir1 | .ms_kb_base = 0xf00240000ULL,
|
1328 | 7d85892b | blueswir1 | .serial_base = 0xf00200000ULL,
|
1329 | 7d85892b | blueswir1 | .nvram_base = 0xf00280000ULL,
|
1330 | 7d85892b | blueswir1 | .counter_base = 0xf00300000ULL,
|
1331 | 7d85892b | blueswir1 | .espdma_base = 0x800081000ULL,
|
1332 | 7d85892b | blueswir1 | .esp_base = 0x800080000ULL,
|
1333 | 7d85892b | blueswir1 | .ledma_base = 0x800040000ULL,
|
1334 | 7d85892b | blueswir1 | .le_base = 0x800060000ULL,
|
1335 | 7d85892b | blueswir1 | .sbi_base = 0xf02800000ULL,
|
1336 | 7d85892b | blueswir1 | .vram_size = 0x00100000,
|
1337 | 7d85892b | blueswir1 | .nvram_size = 0x2000,
|
1338 | 7d85892b | blueswir1 | .esp_irq = 3,
|
1339 | 7d85892b | blueswir1 | .le_irq = 4,
|
1340 | 7d85892b | blueswir1 | .clock_irq = 14,
|
1341 | 7d85892b | blueswir1 | .clock1_irq = 10,
|
1342 | 7d85892b | blueswir1 | .ms_kb_irq = 12,
|
1343 | 7d85892b | blueswir1 | .ser_irq = 12,
|
1344 | 7d85892b | blueswir1 | .machine_id = 0x80,
|
1345 | 7d85892b | blueswir1 | .iounit_version = 0x03000000,
|
1346 | 7d85892b | blueswir1 | .max_mem = 0xffffffff, // XXX actually first 62GB ok |
1347 | 7d85892b | blueswir1 | .default_cpu_model = "TI SuperSparc II",
|
1348 | 7d85892b | blueswir1 | }, |
1349 | 7d85892b | blueswir1 | }; |
1350 | 7d85892b | blueswir1 | |
1351 | 7d85892b | blueswir1 | static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, int RAM_size, |
1352 | 7d85892b | blueswir1 | const char *boot_device, |
1353 | 7d85892b | blueswir1 | DisplayState *ds, const char *kernel_filename, |
1354 | 7d85892b | blueswir1 | const char *kernel_cmdline, |
1355 | 7d85892b | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1356 | 7d85892b | blueswir1 | { |
1357 | 7d85892b | blueswir1 | CPUState *env, *envs[MAX_CPUS]; |
1358 | 7d85892b | blueswir1 | unsigned int i; |
1359 | 7d85892b | blueswir1 | void *iounits[MAX_IOUNITS], *espdma, *ledma, *main_esp, *nvram, *sbi;
|
1360 | 7d85892b | blueswir1 | qemu_irq *cpu_irqs[MAX_CPUS], *sbi_irq, *sbi_cpu_irq, |
1361 | 7d85892b | blueswir1 | *espdma_irq, *ledma_irq; |
1362 | 7d85892b | blueswir1 | qemu_irq *esp_reset, *le_reset; |
1363 | 7d85892b | blueswir1 | unsigned long prom_offset, kernel_size; |
1364 | 7d85892b | blueswir1 | int ret;
|
1365 | 7d85892b | blueswir1 | char buf[1024]; |
1366 | 7d85892b | blueswir1 | int index;
|
1367 | 7d85892b | blueswir1 | |
1368 | 7d85892b | blueswir1 | /* init CPUs */
|
1369 | 7d85892b | blueswir1 | if (!cpu_model)
|
1370 | 7d85892b | blueswir1 | cpu_model = hwdef->default_cpu_model; |
1371 | 7d85892b | blueswir1 | |
1372 | 7d85892b | blueswir1 | for (i = 0; i < smp_cpus; i++) { |
1373 | 7d85892b | blueswir1 | env = cpu_init(cpu_model); |
1374 | 7d85892b | blueswir1 | if (!env) {
|
1375 | 8e82c6a8 | blueswir1 | fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
|
1376 | 7d85892b | blueswir1 | exit(1);
|
1377 | 7d85892b | blueswir1 | } |
1378 | 7d85892b | blueswir1 | cpu_sparc_set_id(env, i); |
1379 | 7d85892b | blueswir1 | envs[i] = env; |
1380 | 7d85892b | blueswir1 | if (i == 0) { |
1381 | 7d85892b | blueswir1 | qemu_register_reset(main_cpu_reset, env); |
1382 | 7d85892b | blueswir1 | } else {
|
1383 | 7d85892b | blueswir1 | qemu_register_reset(secondary_cpu_reset, env); |
1384 | 7d85892b | blueswir1 | env->halted = 1;
|
1385 | 7d85892b | blueswir1 | } |
1386 | 7d85892b | blueswir1 | register_savevm("cpu", i, 3, cpu_save, cpu_load, env); |
1387 | 7d85892b | blueswir1 | cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS); |
1388 | 7d85892b | blueswir1 | env->prom_addr = hwdef->slavio_base; |
1389 | 7d85892b | blueswir1 | } |
1390 | 7d85892b | blueswir1 | |
1391 | 7d85892b | blueswir1 | for (i = smp_cpus; i < MAX_CPUS; i++)
|
1392 | 7d85892b | blueswir1 | cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
|
1393 | 7d85892b | blueswir1 | |
1394 | 7d85892b | blueswir1 | /* allocate RAM */
|
1395 | 7d85892b | blueswir1 | if ((uint64_t)RAM_size > hwdef->max_mem) {
|
1396 | 7d85892b | blueswir1 | fprintf(stderr, "qemu: Too much memory for this machine: %d, maximum %d\n",
|
1397 | 7d85892b | blueswir1 | (unsigned int)RAM_size / (1024 * 1024), |
1398 | 7d85892b | blueswir1 | (unsigned int)(hwdef->max_mem / (1024 * 1024))); |
1399 | 7d85892b | blueswir1 | exit(1);
|
1400 | 7d85892b | blueswir1 | } |
1401 | 7d85892b | blueswir1 | cpu_register_physical_memory(0, RAM_size, 0); |
1402 | 7d85892b | blueswir1 | |
1403 | 7d85892b | blueswir1 | /* load boot prom */
|
1404 | 7d85892b | blueswir1 | prom_offset = RAM_size + hwdef->vram_size; |
1405 | 7d85892b | blueswir1 | cpu_register_physical_memory(hwdef->slavio_base, |
1406 | 7d85892b | blueswir1 | (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
|
1407 | 7d85892b | blueswir1 | TARGET_PAGE_MASK, |
1408 | 7d85892b | blueswir1 | prom_offset | IO_MEM_ROM); |
1409 | 7d85892b | blueswir1 | |
1410 | 7d85892b | blueswir1 | if (bios_name == NULL) |
1411 | 7d85892b | blueswir1 | bios_name = PROM_FILENAME; |
1412 | 7d85892b | blueswir1 | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); |
1413 | 7d85892b | blueswir1 | ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL); |
1414 | 7d85892b | blueswir1 | if (ret < 0 || ret > PROM_SIZE_MAX) |
1415 | 7d85892b | blueswir1 | ret = load_image(buf, phys_ram_base + prom_offset); |
1416 | 7d85892b | blueswir1 | if (ret < 0 || ret > PROM_SIZE_MAX) { |
1417 | 7d85892b | blueswir1 | fprintf(stderr, "qemu: could not load prom '%s'\n",
|
1418 | 7d85892b | blueswir1 | buf); |
1419 | 7d85892b | blueswir1 | exit(1);
|
1420 | 7d85892b | blueswir1 | } |
1421 | 7d85892b | blueswir1 | |
1422 | 7d85892b | blueswir1 | /* set up devices */
|
1423 | 7d85892b | blueswir1 | sbi = sbi_init(hwdef->sbi_base, &sbi_irq, &sbi_cpu_irq, cpu_irqs); |
1424 | 7d85892b | blueswir1 | |
1425 | 7d85892b | blueswir1 | for (i = 0; i < MAX_IOUNITS; i++) |
1426 | 7d85892b | blueswir1 | if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1) |
1427 | ff403da6 | blueswir1 | iounits[i] = iommu_init(hwdef->iounit_bases[i], |
1428 | ff403da6 | blueswir1 | hwdef->iounit_version, |
1429 | ff403da6 | blueswir1 | sbi_irq[hwdef->me_irq]); |
1430 | 7d85892b | blueswir1 | |
1431 | 7d85892b | blueswir1 | espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[hwdef->esp_irq], |
1432 | 7d85892b | blueswir1 | iounits[0], &espdma_irq, &esp_reset);
|
1433 | 7d85892b | blueswir1 | |
1434 | 7d85892b | blueswir1 | ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[hwdef->le_irq], |
1435 | 7d85892b | blueswir1 | iounits[0], &ledma_irq, &le_reset);
|
1436 | 7d85892b | blueswir1 | |
1437 | 7d85892b | blueswir1 | if (graphic_depth != 8 && graphic_depth != 24) { |
1438 | 7d85892b | blueswir1 | fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
|
1439 | 7d85892b | blueswir1 | exit (1);
|
1440 | 7d85892b | blueswir1 | } |
1441 | 7d85892b | blueswir1 | tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size, |
1442 | 7d85892b | blueswir1 | hwdef->vram_size, graphic_width, graphic_height, graphic_depth); |
1443 | 7d85892b | blueswir1 | |
1444 | 7d85892b | blueswir1 | if (nd_table[0].model == NULL |
1445 | 7d85892b | blueswir1 | || strcmp(nd_table[0].model, "lance") == 0) { |
1446 | 7d85892b | blueswir1 | lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
|
1447 | 7d85892b | blueswir1 | } else if (strcmp(nd_table[0].model, "?") == 0) { |
1448 | 7d85892b | blueswir1 | fprintf(stderr, "qemu: Supported NICs: lance\n");
|
1449 | 7d85892b | blueswir1 | exit (1);
|
1450 | 7d85892b | blueswir1 | } else {
|
1451 | 7d85892b | blueswir1 | fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model); |
1452 | 7d85892b | blueswir1 | exit (1);
|
1453 | 7d85892b | blueswir1 | } |
1454 | 7d85892b | blueswir1 | |
1455 | 7d85892b | blueswir1 | nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0, |
1456 | 7d85892b | blueswir1 | hwdef->nvram_size, 8);
|
1457 | 7d85892b | blueswir1 | |
1458 | 7d85892b | blueswir1 | slavio_timer_init_all(hwdef->counter_base, sbi_irq[hwdef->clock1_irq], |
1459 | 7d85892b | blueswir1 | sbi_cpu_irq, smp_cpus); |
1460 | 7d85892b | blueswir1 | |
1461 | 7d85892b | blueswir1 | slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[hwdef->ms_kb_irq], |
1462 | 7d85892b | blueswir1 | nographic); |
1463 | 7d85892b | blueswir1 | // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
|
1464 | 7d85892b | blueswir1 | // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
|
1465 | 7d85892b | blueswir1 | slavio_serial_init(hwdef->serial_base, sbi_irq[hwdef->ser_irq], |
1466 | 7d85892b | blueswir1 | serial_hds[1], serial_hds[0]); |
1467 | 7d85892b | blueswir1 | |
1468 | 7d85892b | blueswir1 | if (drive_get_max_bus(IF_SCSI) > 0) { |
1469 | 7d85892b | blueswir1 | fprintf(stderr, "qemu: too many SCSI bus\n");
|
1470 | 7d85892b | blueswir1 | exit(1);
|
1471 | 7d85892b | blueswir1 | } |
1472 | 7d85892b | blueswir1 | |
1473 | 5d20fa6b | blueswir1 | main_esp = esp_init(hwdef->esp_base, 2,
|
1474 | 8b17de88 | blueswir1 | espdma_memory_read, espdma_memory_write, |
1475 | 8b17de88 | blueswir1 | espdma, *espdma_irq, esp_reset); |
1476 | 7d85892b | blueswir1 | |
1477 | 7d85892b | blueswir1 | for (i = 0; i < ESP_MAX_DEVS; i++) { |
1478 | 7d85892b | blueswir1 | index = drive_get_index(IF_SCSI, 0, i);
|
1479 | 7d85892b | blueswir1 | if (index == -1) |
1480 | 7d85892b | blueswir1 | continue;
|
1481 | 7d85892b | blueswir1 | esp_scsi_attach(main_esp, drives_table[index].bdrv, i); |
1482 | 7d85892b | blueswir1 | } |
1483 | 7d85892b | blueswir1 | |
1484 | 7d85892b | blueswir1 | kernel_size = sun4m_load_kernel(kernel_filename, kernel_cmdline, |
1485 | 7d85892b | blueswir1 | initrd_filename); |
1486 | 7d85892b | blueswir1 | |
1487 | 7d85892b | blueswir1 | nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
|
1488 | 7d85892b | blueswir1 | boot_device, RAM_size, kernel_size, graphic_width, |
1489 | 7d85892b | blueswir1 | graphic_height, graphic_depth, hwdef->machine_id, "Sun4d");
|
1490 | 7d85892b | blueswir1 | } |
1491 | 7d85892b | blueswir1 | |
1492 | 7d85892b | blueswir1 | /* SPARCserver 1000 hardware initialisation */
|
1493 | 03875444 | aurel32 | static void ss1000_init(int RAM_size, int vga_ram_size, |
1494 | 7d85892b | blueswir1 | const char *boot_device, DisplayState *ds, |
1495 | 7d85892b | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1496 | 7d85892b | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1497 | 7d85892b | blueswir1 | { |
1498 | 7d85892b | blueswir1 | sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, ds, kernel_filename,
|
1499 | 7d85892b | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1500 | 7d85892b | blueswir1 | } |
1501 | 7d85892b | blueswir1 | |
1502 | 7d85892b | blueswir1 | /* SPARCcenter 2000 hardware initialisation */
|
1503 | 03875444 | aurel32 | static void ss2000_init(int RAM_size, int vga_ram_size, |
1504 | 7d85892b | blueswir1 | const char *boot_device, DisplayState *ds, |
1505 | 7d85892b | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1506 | 7d85892b | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1507 | 7d85892b | blueswir1 | { |
1508 | 7d85892b | blueswir1 | sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, ds, kernel_filename,
|
1509 | 7d85892b | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1510 | 7d85892b | blueswir1 | } |
1511 | 7d85892b | blueswir1 | |
1512 | 7d85892b | blueswir1 | QEMUMachine ss1000_machine = { |
1513 | 7d85892b | blueswir1 | "SS-1000",
|
1514 | 7d85892b | blueswir1 | "Sun4d platform, SPARCserver 1000",
|
1515 | 7d85892b | blueswir1 | ss1000_init, |
1516 | 7fb4fdcf | balrog | PROM_SIZE_MAX + 0x00100000,
|
1517 | 7d85892b | blueswir1 | }; |
1518 | 7d85892b | blueswir1 | |
1519 | 7d85892b | blueswir1 | QEMUMachine ss2000_machine = { |
1520 | 7d85892b | blueswir1 | "SS-2000",
|
1521 | 7d85892b | blueswir1 | "Sun4d platform, SPARCcenter 2000",
|
1522 | 7d85892b | blueswir1 | ss2000_init, |
1523 | 7fb4fdcf | balrog | PROM_SIZE_MAX + 0x00100000,
|
1524 | 7d85892b | blueswir1 | }; |