root / hw / soc_dma.h @ 7fc2f2c0
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1 | afbb5194 | balrog | /*
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2 | afbb5194 | balrog | * On-chip DMA controller framework.
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3 | afbb5194 | balrog | *
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4 | afbb5194 | balrog | * Copyright (C) 2008 Nokia Corporation
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5 | afbb5194 | balrog | * Written by Andrzej Zaborowski <andrew@openedhand.com>
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6 | afbb5194 | balrog | *
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7 | afbb5194 | balrog | * This program is free software; you can redistribute it and/or
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8 | afbb5194 | balrog | * modify it under the terms of the GNU General Public License as
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9 | afbb5194 | balrog | * published by the Free Software Foundation; either version 2 or
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10 | afbb5194 | balrog | * (at your option) version 3 of the License.
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11 | afbb5194 | balrog | *
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12 | afbb5194 | balrog | * This program is distributed in the hope that it will be useful,
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13 | afbb5194 | balrog | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 | afbb5194 | balrog | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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15 | afbb5194 | balrog | * GNU General Public License for more details.
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16 | afbb5194 | balrog | *
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17 | fad6cb1a | aurel32 | * You should have received a copy of the GNU General Public License along
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18 | 8167ee88 | Blue Swirl | * with this program; if not, see <http://www.gnu.org/licenses/>.
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19 | afbb5194 | balrog | */
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20 | afbb5194 | balrog | |
21 | afbb5194 | balrog | struct soc_dma_s;
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22 | afbb5194 | balrog | struct soc_dma_ch_s;
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23 | afbb5194 | balrog | typedef void (*soc_dma_io_t)(void *opaque, uint8_t *buf, int len); |
24 | afbb5194 | balrog | typedef void (*soc_dma_transfer_t)(struct soc_dma_ch_s *ch); |
25 | afbb5194 | balrog | |
26 | afbb5194 | balrog | enum soc_dma_port_type {
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27 | afbb5194 | balrog | soc_dma_port_mem, |
28 | afbb5194 | balrog | soc_dma_port_fifo, |
29 | afbb5194 | balrog | soc_dma_port_other, |
30 | afbb5194 | balrog | }; |
31 | afbb5194 | balrog | |
32 | afbb5194 | balrog | enum soc_dma_access_type {
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33 | afbb5194 | balrog | soc_dma_access_const, |
34 | afbb5194 | balrog | soc_dma_access_linear, |
35 | afbb5194 | balrog | soc_dma_access_other, |
36 | afbb5194 | balrog | }; |
37 | afbb5194 | balrog | |
38 | afbb5194 | balrog | struct soc_dma_ch_s {
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39 | afbb5194 | balrog | /* Private */
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40 | afbb5194 | balrog | struct soc_dma_s *dma;
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41 | afbb5194 | balrog | int num;
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42 | afbb5194 | balrog | QEMUTimer *timer; |
43 | afbb5194 | balrog | |
44 | afbb5194 | balrog | /* Set by soc_dma.c */
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45 | afbb5194 | balrog | int enable;
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46 | afbb5194 | balrog | int update;
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47 | afbb5194 | balrog | |
48 | afbb5194 | balrog | /* This should be set by dma->setup_fn(). */
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49 | afbb5194 | balrog | int bytes;
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50 | afbb5194 | balrog | /* Initialised by the DMA module, call soc_dma_ch_update after writing. */
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51 | afbb5194 | balrog | enum soc_dma_access_type type[2]; |
52 | afbb5194 | balrog | target_phys_addr_t vaddr[2]; /* Updated by .transfer_fn(). */ |
53 | afbb5194 | balrog | /* Private */
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54 | afbb5194 | balrog | void *paddr[2]; |
55 | afbb5194 | balrog | soc_dma_io_t io_fn[2];
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56 | afbb5194 | balrog | void *io_opaque[2]; |
57 | afbb5194 | balrog | |
58 | afbb5194 | balrog | int running;
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59 | afbb5194 | balrog | soc_dma_transfer_t transfer_fn; |
60 | afbb5194 | balrog | |
61 | afbb5194 | balrog | /* Set and used by the DMA module. */
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62 | afbb5194 | balrog | void *opaque;
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63 | afbb5194 | balrog | }; |
64 | afbb5194 | balrog | |
65 | afbb5194 | balrog | struct soc_dma_s {
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66 | afbb5194 | balrog | /* Following fields are set by the SoC DMA module and can be used
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67 | afbb5194 | balrog | * by anybody. */
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68 | afbb5194 | balrog | uint64_t drqbmp; /* Is zeroed by soc_dma_reset() */
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69 | afbb5194 | balrog | qemu_irq *drq; |
70 | afbb5194 | balrog | void *opaque;
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71 | afbb5194 | balrog | int64_t freq; |
72 | afbb5194 | balrog | soc_dma_transfer_t transfer_fn; |
73 | afbb5194 | balrog | soc_dma_transfer_t setup_fn; |
74 | afbb5194 | balrog | /* Set by soc_dma_init() for use by the DMA module. */
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75 | afbb5194 | balrog | struct soc_dma_ch_s *ch;
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76 | afbb5194 | balrog | }; |
77 | afbb5194 | balrog | |
78 | afbb5194 | balrog | /* Call to activate or stop a DMA channel. */
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79 | afbb5194 | balrog | void soc_dma_set_request(struct soc_dma_ch_s *ch, int level); |
80 | afbb5194 | balrog | /* Call after every write to one of the following fields and before
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81 | afbb5194 | balrog | * calling soc_dma_set_request(ch, 1):
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82 | afbb5194 | balrog | * ch->type[0...1],
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83 | afbb5194 | balrog | * ch->vaddr[0...1],
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84 | afbb5194 | balrog | * ch->paddr[0...1],
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85 | afbb5194 | balrog | * or after a soc_dma_port_add_fifo() or soc_dma_port_add_mem(). */
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86 | afbb5194 | balrog | void soc_dma_ch_update(struct soc_dma_ch_s *ch); |
87 | afbb5194 | balrog | |
88 | afbb5194 | balrog | /* The SoC should call this when the DMA module is being reset. */
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89 | afbb5194 | balrog | void soc_dma_reset(struct soc_dma_s *s); |
90 | afbb5194 | balrog | struct soc_dma_s *soc_dma_init(int n); |
91 | afbb5194 | balrog | |
92 | afbb5194 | balrog | void soc_dma_port_add_fifo(struct soc_dma_s *dma, target_phys_addr_t virt_base, |
93 | afbb5194 | balrog | soc_dma_io_t fn, void *opaque, int out); |
94 | afbb5194 | balrog | void soc_dma_port_add_mem(struct soc_dma_s *dma, uint8_t *phys_base, |
95 | afbb5194 | balrog | target_phys_addr_t virt_base, size_t size); |
96 | afbb5194 | balrog | |
97 | afbb5194 | balrog | static inline void soc_dma_port_add_fifo_in(struct soc_dma_s *dma, |
98 | afbb5194 | balrog | target_phys_addr_t virt_base, soc_dma_io_t fn, void *opaque)
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99 | afbb5194 | balrog | { |
100 | afbb5194 | balrog | return soc_dma_port_add_fifo(dma, virt_base, fn, opaque, 0); |
101 | afbb5194 | balrog | } |
102 | afbb5194 | balrog | |
103 | afbb5194 | balrog | static inline void soc_dma_port_add_fifo_out(struct soc_dma_s *dma, |
104 | afbb5194 | balrog | target_phys_addr_t virt_base, soc_dma_io_t fn, void *opaque)
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105 | afbb5194 | balrog | { |
106 | afbb5194 | balrog | return soc_dma_port_add_fifo(dma, virt_base, fn, opaque, 1); |
107 | afbb5194 | balrog | } |
108 | afbb5194 | balrog | |
109 | afbb5194 | balrog | static inline void soc_dma_port_add_mem_ram(struct soc_dma_s *dma, |
110 | afbb5194 | balrog | ram_addr_t offset, target_phys_addr_t virt_base, size_t size) |
111 | afbb5194 | balrog | { |
112 | 5c130f65 | pbrook | return soc_dma_port_add_mem(dma, qemu_get_ram_ptr(offset), virt_base, size);
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113 | afbb5194 | balrog | } |