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/*
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* QEMU 16550A UART emulation
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*
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* Copyright (c) 2003-2004 Fabrice Bellard
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* Copyright (c) 2008 Citrix Systems, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h" |
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#include "qemu-char.h" |
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#include "isa.h" |
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#include "pc.h" |
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#include "qemu-timer.h" |
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//#define DEBUG_SERIAL
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#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ |
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#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ |
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#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ |
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#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ |
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#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ |
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|
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#define UART_IIR_NO_INT 0x01 /* No interrupts pending */ |
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#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ |
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|
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#define UART_IIR_MSI 0x00 /* Modem status interrupt */ |
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#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ |
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#define UART_IIR_RDI 0x04 /* Receiver data interrupt */ |
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#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ |
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#define UART_IIR_CTI 0x0C /* Character Timeout Indication */ |
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#define UART_IIR_FENF 0x80 /* Fifo enabled, but not functionning */ |
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#define UART_IIR_FE 0xC0 /* Fifo enabled */ |
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/*
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* These are the definitions for the Modem Control Register
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*/
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#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ |
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#define UART_MCR_OUT2 0x08 /* Out2 complement */ |
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#define UART_MCR_OUT1 0x04 /* Out1 complement */ |
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#define UART_MCR_RTS 0x02 /* RTS complement */ |
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#define UART_MCR_DTR 0x01 /* DTR complement */ |
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|
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/*
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* These are the definitions for the Modem Status Register
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*/
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#define UART_MSR_DCD 0x80 /* Data Carrier Detect */ |
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#define UART_MSR_RI 0x40 /* Ring Indicator */ |
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#define UART_MSR_DSR 0x20 /* Data Set Ready */ |
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#define UART_MSR_CTS 0x10 /* Clear to Send */ |
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#define UART_MSR_DDCD 0x08 /* Delta DCD */ |
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#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ |
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#define UART_MSR_DDSR 0x02 /* Delta DSR */ |
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#define UART_MSR_DCTS 0x01 /* Delta CTS */ |
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#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */ |
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#define UART_LSR_TEMT 0x40 /* Transmitter empty */ |
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#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ |
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#define UART_LSR_BI 0x10 /* Break interrupt indicator */ |
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#define UART_LSR_FE 0x08 /* Frame error indicator */ |
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#define UART_LSR_PE 0x04 /* Parity error indicator */ |
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#define UART_LSR_OE 0x02 /* Overrun error indicator */ |
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#define UART_LSR_DR 0x01 /* Receiver data ready */ |
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#define UART_LSR_INT_ANY 0x1E /* Any of the lsr-interrupt-triggering status bits */ |
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/* Interrupt trigger levels. The byte-counts are for 16550A - in newer UARTs the byte-count for each ITL is higher. */
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#define UART_FCR_ITL_1 0x00 /* 1 byte ITL */ |
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#define UART_FCR_ITL_2 0x40 /* 4 bytes ITL */ |
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#define UART_FCR_ITL_3 0x80 /* 8 bytes ITL */ |
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#define UART_FCR_ITL_4 0xC0 /* 14 bytes ITL */ |
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#define UART_FCR_DMS 0x08 /* DMA Mode Select */ |
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#define UART_FCR_XFR 0x04 /* XMIT Fifo Reset */ |
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#define UART_FCR_RFR 0x02 /* RCVR Fifo Reset */ |
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#define UART_FCR_FE 0x01 /* FIFO Enable */ |
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#define UART_FIFO_LENGTH 16 /* 16550A Fifo Length */ |
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#define XMIT_FIFO 0 |
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#define RECV_FIFO 1 |
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#define MAX_XMIT_RETRY 4 |
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struct SerialFIFO {
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uint8_t data[UART_FIFO_LENGTH]; |
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uint8_t count; |
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uint8_t itl; /* Interrupt Trigger Level */
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uint8_t tail; |
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uint8_t head; |
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} typedef SerialFIFO;
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struct SerialState {
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uint16_t divider; |
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uint8_t rbr; /* receive register */
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uint8_t thr; /* transmit holding register */
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uint8_t tsr; /* transmit shift register */
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uint8_t ier; |
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uint8_t iir; /* read only */
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uint8_t lcr; |
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uint8_t mcr; |
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uint8_t lsr; /* read only */
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uint8_t msr; /* read only */
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uint8_t scr; |
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uint8_t fcr; |
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/* NOTE: this hidden state is necessary for tx irq generation as
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it can be reset while reading iir */
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int thr_ipending;
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qemu_irq irq; |
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CharDriverState *chr; |
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int last_break_enable;
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int it_shift;
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int baudbase;
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int tsr_retry;
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uint64_t last_xmit_ts; /* Time when the last byte was successfully sent out of the tsr */
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SerialFIFO recv_fifo; |
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SerialFIFO xmit_fifo; |
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struct QEMUTimer *fifo_timeout_timer;
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int timeout_ipending; /* timeout interrupt pending state */ |
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struct QEMUTimer *transmit_timer;
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uint64_t char_transmit_time; /* time to transmit a char in ticks*/
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int poll_msl;
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struct QEMUTimer *modem_status_poll;
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}; |
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static void serial_receive1(void *opaque, const uint8_t *buf, int size); |
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static void fifo_clear(SerialState *s, int fifo) |
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{ |
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SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo; |
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memset(f->data, 0, UART_FIFO_LENGTH);
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f->count = 0;
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f->head = 0;
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f->tail = 0;
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} |
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static int fifo_put(SerialState *s, int fifo, uint8_t chr) |
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{ |
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SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo; |
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f->data[f->head++] = chr; |
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if (f->head == UART_FIFO_LENGTH)
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f->head = 0;
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f->count++; |
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return 1; |
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} |
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static uint8_t fifo_get(SerialState *s, int fifo) |
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{ |
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SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo; |
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uint8_t c; |
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if(f->count == 0) |
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return 0; |
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c = f->data[f->tail++]; |
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if (f->tail == UART_FIFO_LENGTH)
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f->tail = 0;
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f->count--; |
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return c;
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} |
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static void serial_update_irq(SerialState *s) |
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{ |
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uint8_t tmp_iir = UART_IIR_NO_INT; |
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if ((s->ier & UART_IER_RLSI) && (s->lsr & UART_LSR_INT_ANY)) {
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tmp_iir = UART_IIR_RLSI; |
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} else if ((s->ier & UART_IER_RDI) && s->timeout_ipending) { |
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/* Note that(s->ier & UART_IER_RDI) can mask this interrupt,
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* this is not in the specification but is observed on existing
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* hardware. */
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tmp_iir = UART_IIR_CTI; |
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} else if ((s->ier & UART_IER_RDI) && (s->lsr & UART_LSR_DR)) { |
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if (!(s->fcr & UART_FCR_FE)) {
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tmp_iir = UART_IIR_RDI; |
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} else if (s->recv_fifo.count >= s->recv_fifo.itl) { |
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tmp_iir = UART_IIR_RDI; |
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} |
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} else if ((s->ier & UART_IER_THRI) && s->thr_ipending) { |
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tmp_iir = UART_IIR_THRI; |
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} else if ((s->ier & UART_IER_MSI) && (s->msr & UART_MSR_ANY_DELTA)) { |
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tmp_iir = UART_IIR_MSI; |
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} |
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s->iir = tmp_iir | (s->iir & 0xF0);
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if (tmp_iir != UART_IIR_NO_INT) {
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qemu_irq_raise(s->irq); |
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} else {
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qemu_irq_lower(s->irq); |
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} |
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} |
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static void serial_update_parameters(SerialState *s) |
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{ |
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int speed, parity, data_bits, stop_bits, frame_size;
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QEMUSerialSetParams ssp; |
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if (s->divider == 0) |
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return;
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frame_size = 1;
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if (s->lcr & 0x08) { |
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if (s->lcr & 0x10) |
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parity = 'E';
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else
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parity = 'O';
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} else {
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parity = 'N';
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frame_size = 0;
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} |
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if (s->lcr & 0x04) |
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stop_bits = 2;
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else
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stop_bits = 1;
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data_bits = (s->lcr & 0x03) + 5; |
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frame_size += data_bits + stop_bits; |
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speed = s->baudbase / s->divider; |
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ssp.speed = speed; |
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ssp.parity = parity; |
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ssp.data_bits = data_bits; |
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ssp.stop_bits = stop_bits; |
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s->char_transmit_time = (ticks_per_sec / speed) * frame_size; |
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qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); |
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#if 0
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printf("speed=%d parity=%c data=%d stop=%d\n",
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speed, parity, data_bits, stop_bits);
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#endif
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} |
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static void serial_update_msl(SerialState *s) |
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{ |
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uint8_t omsr; |
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int flags;
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qemu_del_timer(s->modem_status_poll); |
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if (qemu_chr_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags) == -ENOTSUP) {
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s->poll_msl = -1;
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return;
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} |
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omsr = s->msr; |
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s->msr = (flags & CHR_TIOCM_CTS) ? s->msr | UART_MSR_CTS : s->msr & ~UART_MSR_CTS; |
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s->msr = (flags & CHR_TIOCM_DSR) ? s->msr | UART_MSR_DSR : s->msr & ~UART_MSR_DSR; |
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s->msr = (flags & CHR_TIOCM_CAR) ? s->msr | UART_MSR_DCD : s->msr & ~UART_MSR_DCD; |
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s->msr = (flags & CHR_TIOCM_RI) ? s->msr | UART_MSR_RI : s->msr & ~UART_MSR_RI; |
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if (s->msr != omsr) {
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/* Set delta bits */
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s->msr = s->msr | ((s->msr >> 4) ^ (omsr >> 4)); |
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/* UART_MSR_TERI only if change was from 1 -> 0 */
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if ((s->msr & UART_MSR_TERI) && !(omsr & UART_MSR_RI))
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s->msr &= ~UART_MSR_TERI; |
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serial_update_irq(s); |
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} |
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/* The real 16550A apparently has a 250ns response latency to line status changes.
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We'll be lazy and poll only every 10ms, and only poll it at all if MSI interrupts are turned on */
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if (s->poll_msl)
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qemu_mod_timer(s->modem_status_poll, qemu_get_clock(vm_clock) + ticks_per_sec / 100);
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} |
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static void serial_xmit(void *opaque) |
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{ |
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SerialState *s = opaque; |
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uint64_t new_xmit_ts = qemu_get_clock(vm_clock); |
296 |
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if (s->tsr_retry <= 0) { |
298 |
if (s->fcr & UART_FCR_FE) {
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s->tsr = fifo_get(s,XMIT_FIFO); |
300 |
if (!s->xmit_fifo.count)
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s->lsr |= UART_LSR_THRE; |
302 |
} else {
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s->tsr = s->thr; |
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s->lsr |= UART_LSR_THRE; |
305 |
} |
306 |
} |
307 |
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if (s->mcr & UART_MCR_LOOP) {
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/* in loopback mode, say that we just received a char */
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serial_receive1(s, &s->tsr, 1);
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} else if (qemu_chr_write(s->chr, &s->tsr, 1) != 1) { |
312 |
if ((s->tsr_retry > 0) && (s->tsr_retry <= MAX_XMIT_RETRY)) { |
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s->tsr_retry++; |
314 |
qemu_mod_timer(s->transmit_timer, new_xmit_ts + s->char_transmit_time); |
315 |
return;
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} else if (s->poll_msl < 0) { |
317 |
/* If we exceed MAX_XMIT_RETRY and the backend is not a real serial port, then
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drop any further failed writes instantly, until we get one that goes through.
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This is to prevent guests that log to unconnected pipes or pty's from stalling. */
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s->tsr_retry = -1;
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} |
322 |
} |
323 |
else {
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s->tsr_retry = 0;
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} |
326 |
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s->last_xmit_ts = qemu_get_clock(vm_clock); |
328 |
if (!(s->lsr & UART_LSR_THRE))
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qemu_mod_timer(s->transmit_timer, s->last_xmit_ts + s->char_transmit_time); |
330 |
|
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if (s->lsr & UART_LSR_THRE) {
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s->lsr |= UART_LSR_TEMT; |
333 |
s->thr_ipending = 1;
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serial_update_irq(s); |
335 |
} |
336 |
} |
337 |
|
338 |
|
339 |
static void serial_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
340 |
{ |
341 |
SerialState *s = opaque; |
342 |
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343 |
addr &= 7;
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344 |
#ifdef DEBUG_SERIAL
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printf("serial: write addr=0x%02x val=0x%02x\n", addr, val);
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#endif
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347 |
switch(addr) {
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348 |
default:
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349 |
case 0: |
350 |
if (s->lcr & UART_LCR_DLAB) {
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351 |
s->divider = (s->divider & 0xff00) | val;
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serial_update_parameters(s); |
353 |
} else {
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354 |
s->thr = (uint8_t) val; |
355 |
if(s->fcr & UART_FCR_FE) {
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fifo_put(s, XMIT_FIFO, s->thr); |
357 |
s->thr_ipending = 0;
|
358 |
s->lsr &= ~UART_LSR_TEMT; |
359 |
s->lsr &= ~UART_LSR_THRE; |
360 |
serial_update_irq(s); |
361 |
} else {
|
362 |
s->thr_ipending = 0;
|
363 |
s->lsr &= ~UART_LSR_THRE; |
364 |
serial_update_irq(s); |
365 |
} |
366 |
serial_xmit(s); |
367 |
} |
368 |
break;
|
369 |
case 1: |
370 |
if (s->lcr & UART_LCR_DLAB) {
|
371 |
s->divider = (s->divider & 0x00ff) | (val << 8); |
372 |
serial_update_parameters(s); |
373 |
} else {
|
374 |
s->ier = val & 0x0f;
|
375 |
/* If the backend device is a real serial port, turn polling of the modem
|
376 |
status lines on physical port on or off depending on UART_IER_MSI state */
|
377 |
if (s->poll_msl >= 0) { |
378 |
if (s->ier & UART_IER_MSI) {
|
379 |
s->poll_msl = 1;
|
380 |
serial_update_msl(s); |
381 |
} else {
|
382 |
qemu_del_timer(s->modem_status_poll); |
383 |
s->poll_msl = 0;
|
384 |
} |
385 |
} |
386 |
if (s->lsr & UART_LSR_THRE) {
|
387 |
s->thr_ipending = 1;
|
388 |
serial_update_irq(s); |
389 |
} |
390 |
} |
391 |
break;
|
392 |
case 2: |
393 |
val = val & 0xFF;
|
394 |
|
395 |
if (s->fcr == val)
|
396 |
break;
|
397 |
|
398 |
/* Did the enable/disable flag change? If so, make sure FIFOs get flushed */
|
399 |
if ((val ^ s->fcr) & UART_FCR_FE)
|
400 |
val |= UART_FCR_XFR | UART_FCR_RFR; |
401 |
|
402 |
/* FIFO clear */
|
403 |
|
404 |
if (val & UART_FCR_RFR) {
|
405 |
qemu_del_timer(s->fifo_timeout_timer); |
406 |
s->timeout_ipending=0;
|
407 |
fifo_clear(s,RECV_FIFO); |
408 |
} |
409 |
|
410 |
if (val & UART_FCR_XFR) {
|
411 |
fifo_clear(s,XMIT_FIFO); |
412 |
} |
413 |
|
414 |
if (val & UART_FCR_FE) {
|
415 |
s->iir |= UART_IIR_FE; |
416 |
/* Set RECV_FIFO trigger Level */
|
417 |
switch (val & 0xC0) { |
418 |
case UART_FCR_ITL_1:
|
419 |
s->recv_fifo.itl = 1;
|
420 |
break;
|
421 |
case UART_FCR_ITL_2:
|
422 |
s->recv_fifo.itl = 4;
|
423 |
break;
|
424 |
case UART_FCR_ITL_3:
|
425 |
s->recv_fifo.itl = 8;
|
426 |
break;
|
427 |
case UART_FCR_ITL_4:
|
428 |
s->recv_fifo.itl = 14;
|
429 |
break;
|
430 |
} |
431 |
} else
|
432 |
s->iir &= ~UART_IIR_FE; |
433 |
|
434 |
/* Set fcr - or at least the bits in it that are supposed to "stick" */
|
435 |
s->fcr = val & 0xC9;
|
436 |
serial_update_irq(s); |
437 |
break;
|
438 |
case 3: |
439 |
{ |
440 |
int break_enable;
|
441 |
s->lcr = val; |
442 |
serial_update_parameters(s); |
443 |
break_enable = (val >> 6) & 1; |
444 |
if (break_enable != s->last_break_enable) {
|
445 |
s->last_break_enable = break_enable; |
446 |
qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK, |
447 |
&break_enable); |
448 |
} |
449 |
} |
450 |
break;
|
451 |
case 4: |
452 |
{ |
453 |
int flags;
|
454 |
int old_mcr = s->mcr;
|
455 |
s->mcr = val & 0x1f;
|
456 |
if (val & UART_MCR_LOOP)
|
457 |
break;
|
458 |
|
459 |
if (s->poll_msl >= 0 && old_mcr != s->mcr) { |
460 |
|
461 |
qemu_chr_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags); |
462 |
|
463 |
flags &= ~(CHR_TIOCM_RTS | CHR_TIOCM_DTR); |
464 |
|
465 |
if (val & UART_MCR_RTS)
|
466 |
flags |= CHR_TIOCM_RTS; |
467 |
if (val & UART_MCR_DTR)
|
468 |
flags |= CHR_TIOCM_DTR; |
469 |
|
470 |
qemu_chr_ioctl(s->chr,CHR_IOCTL_SERIAL_SET_TIOCM, &flags); |
471 |
/* Update the modem status after a one-character-send wait-time, since there may be a response
|
472 |
from the device/computer at the other end of the serial line */
|
473 |
qemu_mod_timer(s->modem_status_poll, qemu_get_clock(vm_clock) + s->char_transmit_time); |
474 |
} |
475 |
} |
476 |
break;
|
477 |
case 5: |
478 |
break;
|
479 |
case 6: |
480 |
break;
|
481 |
case 7: |
482 |
s->scr = val; |
483 |
break;
|
484 |
} |
485 |
} |
486 |
|
487 |
static uint32_t serial_ioport_read(void *opaque, uint32_t addr) |
488 |
{ |
489 |
SerialState *s = opaque; |
490 |
uint32_t ret; |
491 |
|
492 |
addr &= 7;
|
493 |
switch(addr) {
|
494 |
default:
|
495 |
case 0: |
496 |
if (s->lcr & UART_LCR_DLAB) {
|
497 |
ret = s->divider & 0xff;
|
498 |
} else {
|
499 |
if(s->fcr & UART_FCR_FE) {
|
500 |
ret = fifo_get(s,RECV_FIFO); |
501 |
if (s->recv_fifo.count == 0) |
502 |
s->lsr &= ~(UART_LSR_DR | UART_LSR_BI); |
503 |
else
|
504 |
qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock (vm_clock) + s->char_transmit_time * 4);
|
505 |
s->timeout_ipending = 0;
|
506 |
} else {
|
507 |
ret = s->rbr; |
508 |
s->lsr &= ~(UART_LSR_DR | UART_LSR_BI); |
509 |
} |
510 |
serial_update_irq(s); |
511 |
if (!(s->mcr & UART_MCR_LOOP)) {
|
512 |
/* in loopback mode, don't receive any data */
|
513 |
qemu_chr_accept_input(s->chr); |
514 |
} |
515 |
} |
516 |
break;
|
517 |
case 1: |
518 |
if (s->lcr & UART_LCR_DLAB) {
|
519 |
ret = (s->divider >> 8) & 0xff; |
520 |
} else {
|
521 |
ret = s->ier; |
522 |
} |
523 |
break;
|
524 |
case 2: |
525 |
ret = s->iir; |
526 |
s->thr_ipending = 0;
|
527 |
serial_update_irq(s); |
528 |
break;
|
529 |
case 3: |
530 |
ret = s->lcr; |
531 |
break;
|
532 |
case 4: |
533 |
ret = s->mcr; |
534 |
break;
|
535 |
case 5: |
536 |
ret = s->lsr; |
537 |
/* Clear break interrupt */
|
538 |
if (s->lsr & UART_LSR_BI) {
|
539 |
s->lsr &= ~UART_LSR_BI; |
540 |
serial_update_irq(s); |
541 |
} |
542 |
break;
|
543 |
case 6: |
544 |
if (s->mcr & UART_MCR_LOOP) {
|
545 |
/* in loopback, the modem output pins are connected to the
|
546 |
inputs */
|
547 |
ret = (s->mcr & 0x0c) << 4; |
548 |
ret |= (s->mcr & 0x02) << 3; |
549 |
ret |= (s->mcr & 0x01) << 5; |
550 |
} else {
|
551 |
if (s->poll_msl >= 0) |
552 |
serial_update_msl(s); |
553 |
ret = s->msr; |
554 |
/* Clear delta bits & msr int after read, if they were set */
|
555 |
if (s->msr & UART_MSR_ANY_DELTA) {
|
556 |
s->msr &= 0xF0;
|
557 |
serial_update_irq(s); |
558 |
} |
559 |
} |
560 |
break;
|
561 |
case 7: |
562 |
ret = s->scr; |
563 |
break;
|
564 |
} |
565 |
#ifdef DEBUG_SERIAL
|
566 |
printf("serial: read addr=0x%02x val=0x%02x\n", addr, ret);
|
567 |
#endif
|
568 |
return ret;
|
569 |
} |
570 |
|
571 |
static int serial_can_receive(SerialState *s) |
572 |
{ |
573 |
if(s->fcr & UART_FCR_FE) {
|
574 |
if(s->recv_fifo.count < UART_FIFO_LENGTH)
|
575 |
/* Advertise (fifo.itl - fifo.count) bytes when count < ITL, and 1 if above. If UART_FIFO_LENGTH - fifo.count is
|
576 |
advertised the effect will be to almost always fill the fifo completely before the guest has a chance to respond,
|
577 |
effectively overriding the ITL that the guest has set. */
|
578 |
return (s->recv_fifo.count <= s->recv_fifo.itl) ? s->recv_fifo.itl - s->recv_fifo.count : 1; |
579 |
else
|
580 |
return 0; |
581 |
} else {
|
582 |
return !(s->lsr & UART_LSR_DR);
|
583 |
} |
584 |
} |
585 |
|
586 |
static void serial_receive_break(SerialState *s) |
587 |
{ |
588 |
s->rbr = 0;
|
589 |
/* When the LSR_DR is set a null byte is pushed into the fifo */
|
590 |
fifo_put(s, RECV_FIFO, '\0');
|
591 |
s->lsr |= UART_LSR_BI | UART_LSR_DR; |
592 |
serial_update_irq(s); |
593 |
} |
594 |
|
595 |
/* There's data in recv_fifo and s->rbr has not been read for 4 char transmit times */
|
596 |
static void fifo_timeout_int (void *opaque) { |
597 |
SerialState *s = opaque; |
598 |
if (s->recv_fifo.count) {
|
599 |
s->timeout_ipending = 1;
|
600 |
serial_update_irq(s); |
601 |
} |
602 |
} |
603 |
|
604 |
static int serial_can_receive1(void *opaque) |
605 |
{ |
606 |
SerialState *s = opaque; |
607 |
return serial_can_receive(s);
|
608 |
} |
609 |
|
610 |
static void serial_receive1(void *opaque, const uint8_t *buf, int size) |
611 |
{ |
612 |
SerialState *s = opaque; |
613 |
if(s->fcr & UART_FCR_FE) {
|
614 |
int i;
|
615 |
for (i = 0; i < size; i++) { |
616 |
fifo_put(s, RECV_FIFO, buf[i]); |
617 |
} |
618 |
s->lsr |= UART_LSR_DR; |
619 |
/* call the timeout receive callback in 4 char transmit time */
|
620 |
qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock (vm_clock) + s->char_transmit_time * 4);
|
621 |
} else {
|
622 |
s->rbr = buf[0];
|
623 |
s->lsr |= UART_LSR_DR; |
624 |
} |
625 |
serial_update_irq(s); |
626 |
} |
627 |
|
628 |
static void serial_event(void *opaque, int event) |
629 |
{ |
630 |
SerialState *s = opaque; |
631 |
#ifdef DEBUG_SERIAL
|
632 |
printf("serial: event %x\n", event);
|
633 |
#endif
|
634 |
if (event == CHR_EVENT_BREAK)
|
635 |
serial_receive_break(s); |
636 |
} |
637 |
|
638 |
static void serial_save(QEMUFile *f, void *opaque) |
639 |
{ |
640 |
SerialState *s = opaque; |
641 |
|
642 |
qemu_put_be16s(f,&s->divider); |
643 |
qemu_put_8s(f,&s->rbr); |
644 |
qemu_put_8s(f,&s->ier); |
645 |
qemu_put_8s(f,&s->iir); |
646 |
qemu_put_8s(f,&s->lcr); |
647 |
qemu_put_8s(f,&s->mcr); |
648 |
qemu_put_8s(f,&s->lsr); |
649 |
qemu_put_8s(f,&s->msr); |
650 |
qemu_put_8s(f,&s->scr); |
651 |
qemu_put_8s(f,&s->fcr); |
652 |
} |
653 |
|
654 |
static int serial_load(QEMUFile *f, void *opaque, int version_id) |
655 |
{ |
656 |
SerialState *s = opaque; |
657 |
uint8_t fcr = 0;
|
658 |
|
659 |
if(version_id > 3) |
660 |
return -EINVAL;
|
661 |
|
662 |
if (version_id >= 2) |
663 |
qemu_get_be16s(f, &s->divider); |
664 |
else
|
665 |
s->divider = qemu_get_byte(f); |
666 |
qemu_get_8s(f,&s->rbr); |
667 |
qemu_get_8s(f,&s->ier); |
668 |
qemu_get_8s(f,&s->iir); |
669 |
qemu_get_8s(f,&s->lcr); |
670 |
qemu_get_8s(f,&s->mcr); |
671 |
qemu_get_8s(f,&s->lsr); |
672 |
qemu_get_8s(f,&s->msr); |
673 |
qemu_get_8s(f,&s->scr); |
674 |
|
675 |
if (version_id >= 3) |
676 |
qemu_get_8s(f,&fcr); |
677 |
|
678 |
/* Initialize fcr via setter to perform essential side-effects */
|
679 |
serial_ioport_write(s, 0x02, fcr);
|
680 |
return 0; |
681 |
} |
682 |
|
683 |
static void serial_reset(void *opaque) |
684 |
{ |
685 |
SerialState *s = opaque; |
686 |
|
687 |
s->rbr = 0;
|
688 |
s->ier = 0;
|
689 |
s->iir = UART_IIR_NO_INT; |
690 |
s->lcr = 0;
|
691 |
s->lsr = UART_LSR_TEMT | UART_LSR_THRE; |
692 |
s->msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS; |
693 |
/* Default to 9600 baud, no parity, one stop bit */
|
694 |
s->divider = 0x0C;
|
695 |
s->mcr = UART_MCR_OUT2; |
696 |
s->scr = 0;
|
697 |
s->tsr_retry = 0;
|
698 |
s->char_transmit_time = (ticks_per_sec / 9600) * 9; |
699 |
s->poll_msl = 0;
|
700 |
|
701 |
fifo_clear(s,RECV_FIFO); |
702 |
fifo_clear(s,XMIT_FIFO); |
703 |
|
704 |
s->last_xmit_ts = qemu_get_clock(vm_clock); |
705 |
|
706 |
s->thr_ipending = 0;
|
707 |
s->last_break_enable = 0;
|
708 |
qemu_irq_lower(s->irq); |
709 |
} |
710 |
|
711 |
static void serial_init_core(SerialState *s, qemu_irq irq, int baudbase, |
712 |
CharDriverState *chr) |
713 |
{ |
714 |
s->irq = irq; |
715 |
s->baudbase = baudbase; |
716 |
s->chr = chr ?: qemu_chr_open("null", "null", NULL); |
717 |
|
718 |
s->modem_status_poll = qemu_new_timer(vm_clock, (QEMUTimerCB *) serial_update_msl, s); |
719 |
|
720 |
s->fifo_timeout_timer = qemu_new_timer(vm_clock, (QEMUTimerCB *) fifo_timeout_int, s); |
721 |
s->transmit_timer = qemu_new_timer(vm_clock, (QEMUTimerCB *) serial_xmit, s); |
722 |
|
723 |
qemu_register_reset(serial_reset, s); |
724 |
serial_reset(s); |
725 |
|
726 |
qemu_chr_add_handlers(s->chr, serial_can_receive1, serial_receive1, |
727 |
serial_event, s); |
728 |
} |
729 |
|
730 |
/* If fd is zero, it means that the serial device uses the console */
|
731 |
SerialState *serial_init(int base, qemu_irq irq, int baudbase, |
732 |
CharDriverState *chr) |
733 |
{ |
734 |
SerialState *s; |
735 |
|
736 |
s = qemu_mallocz(sizeof(SerialState));
|
737 |
|
738 |
serial_init_core(s, irq, baudbase, chr); |
739 |
|
740 |
register_savevm("serial", base, 3, serial_save, serial_load, s); |
741 |
|
742 |
register_ioport_write(base, 8, 1, serial_ioport_write, s); |
743 |
register_ioport_read(base, 8, 1, serial_ioport_read, s); |
744 |
return s;
|
745 |
} |
746 |
|
747 |
/* Memory mapped interface */
|
748 |
static uint32_t serial_mm_readb(void *opaque, target_phys_addr_t addr) |
749 |
{ |
750 |
SerialState *s = opaque; |
751 |
|
752 |
return serial_ioport_read(s, addr >> s->it_shift) & 0xFF; |
753 |
} |
754 |
|
755 |
static void serial_mm_writeb(void *opaque, target_phys_addr_t addr, |
756 |
uint32_t value) |
757 |
{ |
758 |
SerialState *s = opaque; |
759 |
|
760 |
serial_ioport_write(s, addr >> s->it_shift, value & 0xFF);
|
761 |
} |
762 |
|
763 |
static uint32_t serial_mm_readw(void *opaque, target_phys_addr_t addr) |
764 |
{ |
765 |
SerialState *s = opaque; |
766 |
uint32_t val; |
767 |
|
768 |
val = serial_ioport_read(s, addr >> s->it_shift) & 0xFFFF;
|
769 |
#ifdef TARGET_WORDS_BIGENDIAN
|
770 |
val = bswap16(val); |
771 |
#endif
|
772 |
return val;
|
773 |
} |
774 |
|
775 |
static void serial_mm_writew(void *opaque, target_phys_addr_t addr, |
776 |
uint32_t value) |
777 |
{ |
778 |
SerialState *s = opaque; |
779 |
#ifdef TARGET_WORDS_BIGENDIAN
|
780 |
value = bswap16(value); |
781 |
#endif
|
782 |
serial_ioport_write(s, addr >> s->it_shift, value & 0xFFFF);
|
783 |
} |
784 |
|
785 |
static uint32_t serial_mm_readl(void *opaque, target_phys_addr_t addr) |
786 |
{ |
787 |
SerialState *s = opaque; |
788 |
uint32_t val; |
789 |
|
790 |
val = serial_ioport_read(s, addr >> s->it_shift); |
791 |
#ifdef TARGET_WORDS_BIGENDIAN
|
792 |
val = bswap32(val); |
793 |
#endif
|
794 |
return val;
|
795 |
} |
796 |
|
797 |
static void serial_mm_writel(void *opaque, target_phys_addr_t addr, |
798 |
uint32_t value) |
799 |
{ |
800 |
SerialState *s = opaque; |
801 |
#ifdef TARGET_WORDS_BIGENDIAN
|
802 |
value = bswap32(value); |
803 |
#endif
|
804 |
serial_ioport_write(s, addr >> s->it_shift, value); |
805 |
} |
806 |
|
807 |
static CPUReadMemoryFunc * const serial_mm_read[] = { |
808 |
&serial_mm_readb, |
809 |
&serial_mm_readw, |
810 |
&serial_mm_readl, |
811 |
}; |
812 |
|
813 |
static CPUWriteMemoryFunc * const serial_mm_write[] = { |
814 |
&serial_mm_writeb, |
815 |
&serial_mm_writew, |
816 |
&serial_mm_writel, |
817 |
}; |
818 |
|
819 |
SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
|
820 |
qemu_irq irq, int baudbase,
|
821 |
CharDriverState *chr, int ioregister)
|
822 |
{ |
823 |
SerialState *s; |
824 |
int s_io_memory;
|
825 |
|
826 |
s = qemu_mallocz(sizeof(SerialState));
|
827 |
|
828 |
s->it_shift = it_shift; |
829 |
|
830 |
serial_init_core(s, irq, baudbase, chr); |
831 |
register_savevm("serial", base, 3, serial_save, serial_load, s); |
832 |
|
833 |
if (ioregister) {
|
834 |
s_io_memory = cpu_register_io_memory(serial_mm_read, |
835 |
serial_mm_write, s); |
836 |
cpu_register_physical_memory(base, 8 << it_shift, s_io_memory);
|
837 |
} |
838 |
serial_update_msl(s); |
839 |
return s;
|
840 |
} |